LXR linux/drivers/net/sfc/phy.h

   1/****************************************************************************
   2 * Driver for Solarflare Solarstorm network controllers and boards
   3 * Copyright 2007-2010 Solarflare Communications Inc.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published
   7 * by the Free Software Foundation, incorporated herein by reference.
   8 */
   9
  10#ifndef EFX_PHY_H
  11#define EFX_PHY_H
  12
  13/****************************************************************************
  14 * 10Xpress (SFX7101) PHY
  15 */
  16extern const struct efx_phy_operations falcon_sfx7101_phy_ops;
  17
  18extern void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode);
  19
  20/****************************************************************************
  21 * AMCC/Quake QT202x PHYs
  22 */
  23extern const struct efx_phy_operations falcon_qt202x_phy_ops;
  24
  25/* These PHYs provide various H/W control states for LEDs */
  26#define QUAKE_LED_LINK_INVAL    (0)
  27#define QUAKE_LED_LINK_STAT     (1)
  28#define QUAKE_LED_LINK_ACT      (2)
  29#define QUAKE_LED_LINK_ACTSTAT  (3)
  30#define QUAKE_LED_OFF           (4)
  31#define QUAKE_LED_ON            (5)
  32#define QUAKE_LED_LINK_INPUT    (6)     /* Pin is an input. */
  33/* What link the LED tracks */
  34#define QUAKE_LED_TXLINK        (0)
  35#define QUAKE_LED_RXLINK        (8)
  36
  37extern void falcon_qt202x_set_led(struct efx_nic *p, int led, int state);
  38
  39/****************************************************************************
  40* Transwitch CX4 retimer
  41*/
  42extern const struct efx_phy_operations falcon_txc_phy_ops;
  43
  44#define TXC_GPIO_DIR_INPUT      0
  45#define TXC_GPIO_DIR_OUTPUT     1
  46
  47extern void falcon_txc_set_gpio_dir(struct efx_nic *efx, int pin, int dir);
  48extern void falcon_txc_set_gpio_val(struct efx_nic *efx, int pin, int val);
  49
  50/****************************************************************************
  51 * Siena managed PHYs
  52 */
  53extern const struct efx_phy_operations efx_mcdi_phy_ops;
  54
  55extern int efx_mcdi_mdio_read(struct efx_nic *efx, unsigned int bus,
  56                              unsigned int prtad, unsigned int devad,
  57                              u16 addr, u16 *value_out, u32 *status_out);
  58extern int efx_mcdi_mdio_write(struct efx_nic *efx, unsigned int bus,
  59                               unsigned int prtad, unsigned int devad,
  60                               u16 addr, u16 value, u32 *status_out);
  61extern void efx_mcdi_phy_decode_link(struct efx_nic *efx,
  62                                     struct efx_link_state *link_state,
  63                                     u32 speed, u32 flags, u32 fcntl);
  64extern int efx_mcdi_phy_reconfigure(struct efx_nic *efx);
  65extern void efx_mcdi_phy_check_fcntl(struct efx_nic *efx, u32 lpa);
  66
  67#endif
  68