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11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/random.h>
17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
21#include "mac.h"
22#include "spi.h"
23#include "regs.h"
24#include "io.h"
25#include "phy.h"
26#include "workarounds.h"
27#include "mcdi.h"
28#include "mcdi_pcol.h"
29
30
31
32static void siena_init_wol(struct efx_nic *efx);
33
34
35static void siena_push_irq_moderation(struct efx_channel *channel)
36{
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52}
53
54static void siena_push_multicast_hash(struct efx_nic *efx)
55{
56 WARN_ON(!mutex_is_locked(&efx->mac_lock));
57
58 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
59 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
60 NULL, 0, NULL);
61}
62
63static int siena_mdio_write(struct net_device *net_dev,
64 int prtad, int devad, u16 addr, u16 value)
65{
66 struct efx_nic *efx = netdev_priv(net_dev);
67 uint32_t status;
68 int rc;
69
70 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
71 addr, value, &status);
72 if (rc)
73 return rc;
74 if (status != MC_CMD_MDIO_STATUS_GOOD)
75 return -EIO;
76
77 return 0;
78}
79
80static int siena_mdio_read(struct net_device *net_dev,
81 int prtad, int devad, u16 addr)
82{
83 struct efx_nic *efx = netdev_priv(net_dev);
84 uint16_t value;
85 uint32_t status;
86 int rc;
87
88 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
89 addr, &value, &status);
90 if (rc)
91 return rc;
92 if (status != MC_CMD_MDIO_STATUS_GOOD)
93 return -EIO;
94
95 return (int)value;
96}
97
98
99static int siena_probe_port(struct efx_nic *efx)
100{
101 int rc;
102
103
104 efx->phy_op = &efx_mcdi_phy_ops;
105
106
107 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
108 efx->mdio.mdio_read = siena_mdio_read;
109 efx->mdio.mdio_write = siena_mdio_write;
110
111
112 rc = efx->phy_op->probe(efx);
113 if (rc != 0)
114 return rc;
115
116
117 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
118 MC_CMD_MAC_NSTATS * sizeof(u64));
119 if (rc)
120 return rc;
121 netif_dbg(efx, probe, efx->net_dev,
122 "stats buffer at %llx (virt %p phys %llx)\n",
123 (u64)efx->stats_buffer.dma_addr,
124 efx->stats_buffer.addr,
125 (u64)virt_to_phys(efx->stats_buffer.addr));
126
127 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
128
129 return 0;
130}
131
132static void siena_remove_port(struct efx_nic *efx)
133{
134 efx->phy_op->remove(efx);
135 efx_nic_free_buffer(efx, &efx->stats_buffer);
136}
137
138static const struct efx_nic_register_test siena_register_tests[] = {
139 { FR_AZ_ADR_REGION,
140 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
141 { FR_CZ_USR_EV_CFG,
142 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
143 { FR_AZ_RX_CFG,
144 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
145 { FR_AZ_TX_CFG,
146 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
147 { FR_AZ_TX_RESERVED,
148 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
149 { FR_AZ_SRM_TX_DC_CFG,
150 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
151 { FR_AZ_RX_DC_CFG,
152 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
153 { FR_AZ_RX_DC_PF_WM,
154 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
155 { FR_BZ_DP_CTRL,
156 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
157 { FR_BZ_RX_RSS_TKEY,
158 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
159 { FR_CZ_RX_RSS_IPV6_REG1,
160 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
161 { FR_CZ_RX_RSS_IPV6_REG2,
162 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
163 { FR_CZ_RX_RSS_IPV6_REG3,
164 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
165};
166
167static int siena_test_registers(struct efx_nic *efx)
168{
169 return efx_nic_test_registers(efx, siena_register_tests,
170 ARRAY_SIZE(siena_register_tests));
171}
172
173
174
175
176
177
178
179
180static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
181{
182 int rc;
183
184
185 rc = efx_mcdi_handle_assertion(efx);
186 if (rc)
187 return rc;
188
189 if (method == RESET_TYPE_WORLD)
190 return efx_mcdi_reset_mc(efx);
191 else
192 return efx_mcdi_reset_port(efx);
193}
194
195static int siena_probe_nvconfig(struct efx_nic *efx)
196{
197 return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
198}
199
200static int siena_probe_nic(struct efx_nic *efx)
201{
202 struct siena_nic_data *nic_data;
203 bool already_attached = 0;
204 efx_oword_t reg;
205 int rc;
206
207
208 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
209 if (!nic_data)
210 return -ENOMEM;
211 efx->nic_data = nic_data;
212
213 if (efx_nic_fpga_ver(efx) != 0) {
214 netif_err(efx, probe, efx->net_dev,
215 "Siena FPGA not supported\n");
216 rc = -ENODEV;
217 goto fail1;
218 }
219
220 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
221 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
222
223
224 nic_data->mcdi_smem = ioremap_nocache(efx->membase_phys +
225 FR_CZ_MC_TREG_SMEM,
226 FR_CZ_MC_TREG_SMEM_STEP *
227 FR_CZ_MC_TREG_SMEM_ROWS);
228 if (!nic_data->mcdi_smem) {
229 netif_err(efx, probe, efx->net_dev,
230 "could not map MCDI at %llx+%x\n",
231 (unsigned long long)efx->membase_phys +
232 FR_CZ_MC_TREG_SMEM,
233 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS);
234 rc = -ENOMEM;
235 goto fail1;
236 }
237 efx_mcdi_init(efx);
238
239
240 rc = efx_mcdi_handle_assertion(efx);
241 if (rc)
242 goto fail2;
243
244
245
246 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
247 if (rc) {
248 netif_err(efx, probe, efx->net_dev,
249 "Unable to register driver with MCPU\n");
250 goto fail2;
251 }
252 if (already_attached)
253
254 netif_err(efx, probe, efx->net_dev,
255 "Host already registered with MCPU\n");
256
257
258 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
259 if (rc) {
260 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
261 goto fail3;
262 }
263
264 siena_init_wol(efx);
265
266
267 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
268 if (rc)
269 goto fail4;
270 BUG_ON(efx->irq_status.dma_addr & 0x0f);
271
272 netif_dbg(efx, probe, efx->net_dev,
273 "INT_KER at %llx (virt %p phys %llx)\n",
274 (unsigned long long)efx->irq_status.dma_addr,
275 efx->irq_status.addr,
276 (unsigned long long)virt_to_phys(efx->irq_status.addr));
277
278
279 rc = siena_probe_nvconfig(efx);
280 if (rc == -EINVAL) {
281 netif_err(efx, probe, efx->net_dev,
282 "NVRAM is invalid therefore using defaults\n");
283 efx->phy_type = PHY_TYPE_NONE;
284 efx->mdio.prtad = MDIO_PRTAD_NONE;
285 } else if (rc) {
286 goto fail5;
287 }
288
289 return 0;
290
291fail5:
292 efx_nic_free_buffer(efx, &efx->irq_status);
293fail4:
294fail3:
295 efx_mcdi_drv_attach(efx, false, NULL);
296fail2:
297 iounmap(nic_data->mcdi_smem);
298fail1:
299 kfree(efx->nic_data);
300 return rc;
301}
302
303
304
305
306
307static int siena_init_nic(struct efx_nic *efx)
308{
309 efx_oword_t temp;
310 int rc;
311
312
313 rc = efx_mcdi_handle_assertion(efx);
314 if (rc)
315 return rc;
316
317
318 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
319 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
320 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
321
322
323
324
325 efx_reado(efx, &temp, FR_AZ_TX_CFG);
326 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
327 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
328 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
329
330 efx_reado(efx, &temp, FR_AZ_RX_CFG);
331 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
332 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
333
334
335
336 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
337 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
338 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
339 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
340
341
342 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
343 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
344
345
346 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
347 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
348 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
349 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
350 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
351 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
352 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
353 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
354 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
355 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
356 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
357 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
358
359
360 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
361 if (rc)
362 return rc;
363
364
365 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
366 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
367
368 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
369 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
370
371 efx_nic_init_common(efx);
372 return 0;
373}
374
375static void siena_remove_nic(struct efx_nic *efx)
376{
377 struct siena_nic_data *nic_data = efx->nic_data;
378
379 efx_nic_free_buffer(efx, &efx->irq_status);
380
381 siena_reset_hw(efx, RESET_TYPE_ALL);
382
383
384 if (efx_nic_has_mc(efx))
385 efx_mcdi_drv_attach(efx, false, NULL);
386
387
388 iounmap(nic_data->mcdi_smem);
389 kfree(nic_data);
390 efx->nic_data = NULL;
391}
392
393#define STATS_GENERATION_INVALID ((u64)(-1))
394
395static int siena_try_update_nic_stats(struct efx_nic *efx)
396{
397 u64 *dma_stats;
398 struct efx_mac_stats *mac_stats;
399 u64 generation_start;
400 u64 generation_end;
401
402 mac_stats = &efx->mac_stats;
403 dma_stats = (u64 *)efx->stats_buffer.addr;
404
405 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
406 if (generation_end == STATS_GENERATION_INVALID)
407 return 0;
408 rmb();
409
410#define MAC_STAT(M, D) \
411 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
412
413 MAC_STAT(tx_bytes, TX_BYTES);
414 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
415 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
416 mac_stats->tx_bad_bytes);
417 MAC_STAT(tx_packets, TX_PKTS);
418 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
419 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
420 MAC_STAT(tx_control, TX_CONTROL_PKTS);
421 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
422 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
423 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
424 MAC_STAT(tx_lt64, TX_LT64_PKTS);
425 MAC_STAT(tx_64, TX_64_PKTS);
426 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
427 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
428 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
429 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
430 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
431 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
432 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
433 mac_stats->tx_collision = 0;
434 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
435 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
436 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
437 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
438 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
439 mac_stats->tx_collision = (mac_stats->tx_single_collision +
440 mac_stats->tx_multiple_collision +
441 mac_stats->tx_excessive_collision +
442 mac_stats->tx_late_collision);
443 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
444 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
445 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
446 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
447 MAC_STAT(rx_bytes, RX_BYTES);
448 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
449 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
450 mac_stats->rx_bad_bytes);
451 MAC_STAT(rx_packets, RX_PKTS);
452 MAC_STAT(rx_good, RX_GOOD_PKTS);
453 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
454 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
455 MAC_STAT(rx_control, RX_CONTROL_PKTS);
456 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
457 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
458 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
459 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
460 MAC_STAT(rx_64, RX_64_PKTS);
461 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
462 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
463 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
464 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
465 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
466 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
467 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
468 mac_stats->rx_bad_lt64 = 0;
469 mac_stats->rx_bad_64_to_15xx = 0;
470 mac_stats->rx_bad_15xx_to_jumbo = 0;
471 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
472 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
473 mac_stats->rx_missed = 0;
474 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
475 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
476 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
477 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
478 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
479 mac_stats->rx_good_lt64 = 0;
480
481 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
482
483#undef MAC_STAT
484
485 rmb();
486 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
487 if (generation_end != generation_start)
488 return -EAGAIN;
489
490 return 0;
491}
492
493static void siena_update_nic_stats(struct efx_nic *efx)
494{
495 int retry;
496
497
498
499 for (retry = 0; retry < 100; ++retry) {
500 if (siena_try_update_nic_stats(efx) == 0)
501 return;
502 udelay(100);
503 }
504
505
506}
507
508static void siena_start_nic_stats(struct efx_nic *efx)
509{
510 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
511
512 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
513
514 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
515 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
516}
517
518static void siena_stop_nic_stats(struct efx_nic *efx)
519{
520 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
521}
522
523
524
525
526
527
528
529
530static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
531{
532 struct siena_nic_data *nic_data = efx->nic_data;
533
534 wol->supported = WAKE_MAGIC;
535 if (nic_data->wol_filter_id != -1)
536 wol->wolopts = WAKE_MAGIC;
537 else
538 wol->wolopts = 0;
539 memset(&wol->sopass, 0, sizeof(wol->sopass));
540}
541
542
543static int siena_set_wol(struct efx_nic *efx, u32 type)
544{
545 struct siena_nic_data *nic_data = efx->nic_data;
546 int rc;
547
548 if (type & ~WAKE_MAGIC)
549 return -EINVAL;
550
551 if (type & WAKE_MAGIC) {
552 if (nic_data->wol_filter_id != -1)
553 efx_mcdi_wol_filter_remove(efx,
554 nic_data->wol_filter_id);
555 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
556 &nic_data->wol_filter_id);
557 if (rc)
558 goto fail;
559
560 pci_wake_from_d3(efx->pci_dev, true);
561 } else {
562 rc = efx_mcdi_wol_filter_reset(efx);
563 nic_data->wol_filter_id = -1;
564 pci_wake_from_d3(efx->pci_dev, false);
565 if (rc)
566 goto fail;
567 }
568
569 return 0;
570 fail:
571 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
572 __func__, type, rc);
573 return rc;
574}
575
576
577static void siena_init_wol(struct efx_nic *efx)
578{
579 struct siena_nic_data *nic_data = efx->nic_data;
580 int rc;
581
582 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
583
584 if (rc != 0) {
585
586
587 efx_mcdi_wol_filter_reset(efx);
588 nic_data->wol_filter_id = -1;
589 } else if (nic_data->wol_filter_id != -1) {
590 pci_wake_from_d3(efx->pci_dev, true);
591 }
592}
593
594
595
596
597
598
599
600
601
602const struct efx_nic_type siena_a0_nic_type = {
603 .probe = siena_probe_nic,
604 .remove = siena_remove_nic,
605 .init = siena_init_nic,
606 .fini = efx_port_dummy_op_void,
607 .monitor = NULL,
608 .reset = siena_reset_hw,
609 .probe_port = siena_probe_port,
610 .remove_port = siena_remove_port,
611 .prepare_flush = efx_port_dummy_op_void,
612 .update_stats = siena_update_nic_stats,
613 .start_stats = siena_start_nic_stats,
614 .stop_stats = siena_stop_nic_stats,
615 .set_id_led = efx_mcdi_set_id_led,
616 .push_irq_moderation = siena_push_irq_moderation,
617 .push_multicast_hash = siena_push_multicast_hash,
618 .reconfigure_port = efx_mcdi_phy_reconfigure,
619 .get_wol = siena_get_wol,
620 .set_wol = siena_set_wol,
621 .resume_wol = siena_init_wol,
622 .test_registers = siena_test_registers,
623 .test_nvram = efx_mcdi_nvram_test_all,
624 .default_mac_ops = &efx_mcdi_mac_operations,
625
626 .revision = EFX_REV_SIENA_A0,
627 .mem_map_size = FR_CZ_MC_TREG_SMEM,
628 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
629 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
630 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
631 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
632 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
633 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
634 .rx_buffer_hash_size = 0x10,
635 .rx_buffer_padding = 0,
636 .max_interrupt_mode = EFX_INT_MODE_MSIX,
637 .phys_addr_channels = 32,
638
639
640 .tx_dc_base = 0x88000,
641 .rx_dc_base = 0x68000,
642 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
643 NETIF_F_RXHASH | NETIF_F_NTUPLE),
644 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
645};
646
