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52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/kernel.h>
55#include <linux/sched.h>
56#include <linux/string.h>
57#include <linux/timer.h>
58#include <linux/errno.h>
59#include <linux/ioport.h>
60#include <linux/slab.h>
61#include <linux/interrupt.h>
62#include <linux/pci.h>
63#include <linux/netdevice.h>
64#include <linux/init.h>
65#include <linux/mii.h>
66#include <linux/etherdevice.h>
67#include <linux/skbuff.h>
68#include <linux/delay.h>
69#include <linux/ethtool.h>
70#include <linux/crc32.h>
71#include <linux/bitops.h>
72#include <linux/dma-mapping.h>
73
74#include <asm/processor.h>
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/uaccess.h>
78
79#include "sis900.h"
80
81#define SIS900_MODULE_NAME "sis900"
82#define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
83
84static const char version[] __devinitconst =
85 KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
86
87static int max_interrupt_work = 40;
88static int multicast_filter_limit = 128;
89
90static int sis900_debug = -1;
91
92#define SIS900_DEF_MSG \
93 (NETIF_MSG_DRV | \
94 NETIF_MSG_LINK | \
95 NETIF_MSG_RX_ERR | \
96 NETIF_MSG_TX_ERR)
97
98
99#define TX_TIMEOUT (4*HZ)
100
101enum {
102 SIS_900 = 0,
103 SIS_7016
104};
105static const char * card_names[] = {
106 "SiS 900 PCI Fast Ethernet",
107 "SiS 7016 PCI Fast Ethernet"
108};
109static DEFINE_PCI_DEVICE_TABLE(sis900_pci_tbl) = {
110 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_900,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_900},
112 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7016,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_7016},
114 {0,}
115};
116MODULE_DEVICE_TABLE (pci, sis900_pci_tbl);
117
118static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex);
119
120static const struct mii_chip_info {
121 const char * name;
122 u16 phy_id0;
123 u16 phy_id1;
124 u8 phy_types;
125#define HOME 0x0001
126#define LAN 0x0002
127#define MIX 0x0003
128#define UNKNOWN 0x0
129} mii_chip_table[] = {
130 { "SiS 900 Internal MII PHY", 0x001d, 0x8000, LAN },
131 { "SiS 7014 Physical Layer Solution", 0x0016, 0xf830, LAN },
132 { "SiS 900 on Foxconn 661 7MI", 0x0143, 0xBC70, LAN },
133 { "Altimata AC101LF PHY", 0x0022, 0x5520, LAN },
134 { "ADM 7001 LAN PHY", 0x002e, 0xcc60, LAN },
135 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
136 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME},
137 { "ICS LAN PHY", 0x0015, 0xF440, LAN },
138 { "ICS LAN PHY", 0x0143, 0xBC70, LAN },
139 { "NS 83851 PHY", 0x2000, 0x5C20, MIX },
140 { "NS 83847 PHY", 0x2000, 0x5C30, MIX },
141 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN },
142 { "VIA 6103 PHY", 0x0101, 0x8f20, LAN },
143 {NULL,},
144};
145
146struct mii_phy {
147 struct mii_phy * next;
148 int phy_addr;
149 u16 phy_id0;
150 u16 phy_id1;
151 u16 status;
152 u8 phy_types;
153};
154
155typedef struct _BufferDesc {
156 u32 link;
157 u32 cmdsts;
158 u32 bufptr;
159} BufferDesc;
160
161struct sis900_private {
162 struct pci_dev * pci_dev;
163
164 spinlock_t lock;
165
166 struct mii_phy * mii;
167 struct mii_phy * first_mii;
168 unsigned int cur_phy;
169 struct mii_if_info mii_info;
170
171 struct timer_list timer;
172 u8 autong_complete;
173
174 u32 msg_enable;
175
176 unsigned int cur_rx, dirty_rx;
177 unsigned int cur_tx, dirty_tx;
178
179
180 struct sk_buff *tx_skbuff[NUM_TX_DESC];
181 struct sk_buff *rx_skbuff[NUM_RX_DESC];
182 BufferDesc *tx_ring;
183 BufferDesc *rx_ring;
184
185 dma_addr_t tx_ring_dma;
186 dma_addr_t rx_ring_dma;
187
188 unsigned int tx_full;
189 u8 host_bridge_rev;
190 u8 chipset_rev;
191};
192
193MODULE_AUTHOR("Jim Huang <cmhuang@sis.com.tw>, Ollie Lho <ollie@sis.com.tw>");
194MODULE_DESCRIPTION("SiS 900 PCI Fast Ethernet driver");
195MODULE_LICENSE("GPL");
196
197module_param(multicast_filter_limit, int, 0444);
198module_param(max_interrupt_work, int, 0444);
199module_param(sis900_debug, int, 0444);
200MODULE_PARM_DESC(multicast_filter_limit, "SiS 900/7016 maximum number of filtered multicast addresses");
201MODULE_PARM_DESC(max_interrupt_work, "SiS 900/7016 maximum events handled per interrupt");
202MODULE_PARM_DESC(sis900_debug, "SiS 900/7016 bitmapped debugging message level");
203
204#ifdef CONFIG_NET_POLL_CONTROLLER
205static void sis900_poll(struct net_device *dev);
206#endif
207static int sis900_open(struct net_device *net_dev);
208static int sis900_mii_probe (struct net_device * net_dev);
209static void sis900_init_rxfilter (struct net_device * net_dev);
210static u16 read_eeprom(long ioaddr, int location);
211static int mdio_read(struct net_device *net_dev, int phy_id, int location);
212static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val);
213static void sis900_timer(unsigned long data);
214static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy);
215static void sis900_tx_timeout(struct net_device *net_dev);
216static void sis900_init_tx_ring(struct net_device *net_dev);
217static void sis900_init_rx_ring(struct net_device *net_dev);
218static netdev_tx_t sis900_start_xmit(struct sk_buff *skb,
219 struct net_device *net_dev);
220static int sis900_rx(struct net_device *net_dev);
221static void sis900_finish_xmit (struct net_device *net_dev);
222static irqreturn_t sis900_interrupt(int irq, void *dev_instance);
223static int sis900_close(struct net_device *net_dev);
224static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd);
225static u16 sis900_mcast_bitnr(u8 *addr, u8 revision);
226static void set_rx_mode(struct net_device *net_dev);
227static void sis900_reset(struct net_device *net_dev);
228static void sis630_set_eq(struct net_device *net_dev, u8 revision);
229static int sis900_set_config(struct net_device *dev, struct ifmap *map);
230static u16 sis900_default_phy(struct net_device * net_dev);
231static void sis900_set_capability( struct net_device *net_dev ,struct mii_phy *phy);
232static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr);
233static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr);
234static void sis900_set_mode (long ioaddr, int speed, int duplex);
235static const struct ethtool_ops sis900_ethtool_ops;
236
237
238
239
240
241
242
243
244
245
246
247static int __devinit sis900_get_mac_addr(struct pci_dev * pci_dev, struct net_device *net_dev)
248{
249 long ioaddr = pci_resource_start(pci_dev, 0);
250 u16 signature;
251 int i;
252
253
254 signature = (u16) read_eeprom(ioaddr, EEPROMSignature);
255 if (signature == 0xffff || signature == 0x0000) {
256 printk (KERN_WARNING "%s: Error EERPOM read %x\n",
257 pci_name(pci_dev), signature);
258 return 0;
259 }
260
261
262 for (i = 0; i < 3; i++)
263 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
264
265
266 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
267
268 return 1;
269}
270
271
272
273
274
275
276
277
278
279
280
281
282static int __devinit sis630e_get_mac_addr(struct pci_dev * pci_dev,
283 struct net_device *net_dev)
284{
285 struct pci_dev *isa_bridge = NULL;
286 u8 reg;
287 int i;
288
289 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, isa_bridge);
290 if (!isa_bridge)
291 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0018, isa_bridge);
292 if (!isa_bridge) {
293 printk(KERN_WARNING "%s: Can not find ISA bridge\n",
294 pci_name(pci_dev));
295 return 0;
296 }
297 pci_read_config_byte(isa_bridge, 0x48, ®);
298 pci_write_config_byte(isa_bridge, 0x48, reg | 0x40);
299
300 for (i = 0; i < 6; i++) {
301 outb(0x09 + i, 0x70);
302 ((u8 *)(net_dev->dev_addr))[i] = inb(0x71);
303 }
304
305
306 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
307
308 pci_write_config_byte(isa_bridge, 0x48, reg & ~0x40);
309 pci_dev_put(isa_bridge);
310
311 return 1;
312}
313
314
315
316
317
318
319
320
321
322
323
324
325static int __devinit sis635_get_mac_addr(struct pci_dev * pci_dev,
326 struct net_device *net_dev)
327{
328 long ioaddr = net_dev->base_addr;
329 u32 rfcrSave;
330 u32 i;
331
332 rfcrSave = inl(rfcr + ioaddr);
333
334 outl(rfcrSave | RELOAD, ioaddr + cr);
335 outl(0, ioaddr + cr);
336
337
338 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
339
340
341 for (i = 0 ; i < 3 ; i++) {
342 outl((i << RFADDR_shift), ioaddr + rfcr);
343 *( ((u16 *)net_dev->dev_addr) + i) = inw(ioaddr + rfdr);
344 }
345
346
347 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
348
349
350 outl(rfcrSave | RFEN, rfcr + ioaddr);
351
352 return 1;
353}
354
355
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358
359
360
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363
364
365
366
367
368
369
370
371static int __devinit sis96x_get_mac_addr(struct pci_dev * pci_dev,
372 struct net_device *net_dev)
373{
374 long ioaddr = net_dev->base_addr;
375 long ee_addr = ioaddr + mear;
376 u32 waittime = 0;
377 int i;
378
379 outl(EEREQ, ee_addr);
380 while(waittime < 2000) {
381 if(inl(ee_addr) & EEGNT) {
382
383
384 for (i = 0; i < 3; i++)
385 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
386
387
388 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
389
390 outl(EEDONE, ee_addr);
391 return 1;
392 } else {
393 udelay(1);
394 waittime ++;
395 }
396 }
397 outl(EEDONE, ee_addr);
398 return 0;
399}
400
401static const struct net_device_ops sis900_netdev_ops = {
402 .ndo_open = sis900_open,
403 .ndo_stop = sis900_close,
404 .ndo_start_xmit = sis900_start_xmit,
405 .ndo_set_config = sis900_set_config,
406 .ndo_set_multicast_list = set_rx_mode,
407 .ndo_change_mtu = eth_change_mtu,
408 .ndo_validate_addr = eth_validate_addr,
409 .ndo_set_mac_address = eth_mac_addr,
410 .ndo_do_ioctl = mii_ioctl,
411 .ndo_tx_timeout = sis900_tx_timeout,
412#ifdef CONFIG_NET_POLL_CONTROLLER
413 .ndo_poll_controller = sis900_poll,
414#endif
415};
416
417
418
419
420
421
422
423
424
425
426
427
428static int __devinit sis900_probe(struct pci_dev *pci_dev,
429 const struct pci_device_id *pci_id)
430{
431 struct sis900_private *sis_priv;
432 struct net_device *net_dev;
433 struct pci_dev *dev;
434 dma_addr_t ring_dma;
435 void *ring_space;
436 long ioaddr;
437 int i, ret;
438 const char *card_name = card_names[pci_id->driver_data];
439 const char *dev_name = pci_name(pci_dev);
440
441
442#ifndef MODULE
443 static int printed_version;
444 if (!printed_version++)
445 printk(version);
446#endif
447
448
449 ret = pci_enable_device(pci_dev);
450 if(ret) return ret;
451
452 i = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
453 if(i){
454 printk(KERN_ERR "sis900.c: architecture does not support "
455 "32bit PCI busmaster DMA\n");
456 return i;
457 }
458
459 pci_set_master(pci_dev);
460
461 net_dev = alloc_etherdev(sizeof(struct sis900_private));
462 if (!net_dev)
463 return -ENOMEM;
464 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
465
466
467 ioaddr = pci_resource_start(pci_dev, 0);
468 ret = pci_request_regions(pci_dev, "sis900");
469 if (ret)
470 goto err_out;
471
472 sis_priv = netdev_priv(net_dev);
473 net_dev->base_addr = ioaddr;
474 net_dev->irq = pci_dev->irq;
475 sis_priv->pci_dev = pci_dev;
476 spin_lock_init(&sis_priv->lock);
477
478 pci_set_drvdata(pci_dev, net_dev);
479
480 ring_space = pci_alloc_consistent(pci_dev, TX_TOTAL_SIZE, &ring_dma);
481 if (!ring_space) {
482 ret = -ENOMEM;
483 goto err_out_cleardev;
484 }
485 sis_priv->tx_ring = (BufferDesc *)ring_space;
486 sis_priv->tx_ring_dma = ring_dma;
487
488 ring_space = pci_alloc_consistent(pci_dev, RX_TOTAL_SIZE, &ring_dma);
489 if (!ring_space) {
490 ret = -ENOMEM;
491 goto err_unmap_tx;
492 }
493 sis_priv->rx_ring = (BufferDesc *)ring_space;
494 sis_priv->rx_ring_dma = ring_dma;
495
496
497 net_dev->netdev_ops = &sis900_netdev_ops;
498 net_dev->watchdog_timeo = TX_TIMEOUT;
499 net_dev->ethtool_ops = &sis900_ethtool_ops;
500
501 if (sis900_debug > 0)
502 sis_priv->msg_enable = sis900_debug;
503 else
504 sis_priv->msg_enable = SIS900_DEF_MSG;
505
506 sis_priv->mii_info.dev = net_dev;
507 sis_priv->mii_info.mdio_read = mdio_read;
508 sis_priv->mii_info.mdio_write = mdio_write;
509 sis_priv->mii_info.phy_id_mask = 0x1f;
510 sis_priv->mii_info.reg_num_mask = 0x1f;
511
512
513 sis_priv->chipset_rev = pci_dev->revision;
514 if(netif_msg_probe(sis_priv))
515 printk(KERN_DEBUG "%s: detected revision %2.2x, "
516 "trying to get MAC address...\n",
517 dev_name, sis_priv->chipset_rev);
518
519 ret = 0;
520 if (sis_priv->chipset_rev == SIS630E_900_REV)
521 ret = sis630e_get_mac_addr(pci_dev, net_dev);
522 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
523 ret = sis635_get_mac_addr(pci_dev, net_dev);
524 else if (sis_priv->chipset_rev == SIS96x_900_REV)
525 ret = sis96x_get_mac_addr(pci_dev, net_dev);
526 else
527 ret = sis900_get_mac_addr(pci_dev, net_dev);
528
529 if (!ret || !is_valid_ether_addr(net_dev->dev_addr)) {
530 random_ether_addr(net_dev->dev_addr);
531 printk(KERN_WARNING "%s: Unreadable or invalid MAC address,"
532 "using random generated one\n", dev_name);
533 }
534
535
536 if (sis_priv->chipset_rev == SIS630ET_900_REV)
537 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr);
538
539
540 if (sis900_mii_probe(net_dev) == 0) {
541 printk(KERN_WARNING "%s: Error probing MII device.\n",
542 dev_name);
543 ret = -ENODEV;
544 goto err_unmap_rx;
545 }
546
547
548 dev = pci_get_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630, NULL);
549 if (dev) {
550 sis_priv->host_bridge_rev = dev->revision;
551 pci_dev_put(dev);
552 }
553
554 ret = register_netdev(net_dev);
555 if (ret)
556 goto err_unmap_rx;
557
558
559 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %pM\n",
560 net_dev->name, card_name, ioaddr, net_dev->irq,
561 net_dev->dev_addr);
562
563
564 ret = (inl(net_dev->base_addr + CFGPMC) & PMESP) >> 27;
565 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
566 printk(KERN_INFO "%s: Wake on LAN only available from suspend to RAM.", net_dev->name);
567
568 return 0;
569
570 err_unmap_rx:
571 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
572 sis_priv->rx_ring_dma);
573 err_unmap_tx:
574 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
575 sis_priv->tx_ring_dma);
576 err_out_cleardev:
577 pci_set_drvdata(pci_dev, NULL);
578 pci_release_regions(pci_dev);
579 err_out:
580 free_netdev(net_dev);
581 return ret;
582}
583
584
585
586
587
588
589
590
591
592
593static int __devinit sis900_mii_probe(struct net_device * net_dev)
594{
595 struct sis900_private *sis_priv = netdev_priv(net_dev);
596 const char *dev_name = pci_name(sis_priv->pci_dev);
597 u16 poll_bit = MII_STAT_LINK, status = 0;
598 unsigned long timeout = jiffies + 5 * HZ;
599 int phy_addr;
600
601 sis_priv->mii = NULL;
602
603
604 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
605 struct mii_phy * mii_phy = NULL;
606 u16 mii_status;
607 int i;
608
609 mii_phy = NULL;
610 for(i = 0; i < 2; i++)
611 mii_status = mdio_read(net_dev, phy_addr, MII_STATUS);
612
613 if (mii_status == 0xffff || mii_status == 0x0000) {
614 if (netif_msg_probe(sis_priv))
615 printk(KERN_DEBUG "%s: MII at address %d"
616 " not accessible\n",
617 dev_name, phy_addr);
618 continue;
619 }
620
621 if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) == NULL) {
622 printk(KERN_WARNING "Cannot allocate mem for struct mii_phy\n");
623 mii_phy = sis_priv->first_mii;
624 while (mii_phy) {
625 struct mii_phy *phy;
626 phy = mii_phy;
627 mii_phy = mii_phy->next;
628 kfree(phy);
629 }
630 return 0;
631 }
632
633 mii_phy->phy_id0 = mdio_read(net_dev, phy_addr, MII_PHY_ID0);
634 mii_phy->phy_id1 = mdio_read(net_dev, phy_addr, MII_PHY_ID1);
635 mii_phy->phy_addr = phy_addr;
636 mii_phy->status = mii_status;
637 mii_phy->next = sis_priv->mii;
638 sis_priv->mii = mii_phy;
639 sis_priv->first_mii = mii_phy;
640
641 for (i = 0; mii_chip_table[i].phy_id1; i++)
642 if ((mii_phy->phy_id0 == mii_chip_table[i].phy_id0 ) &&
643 ((mii_phy->phy_id1 & 0xFFF0) == mii_chip_table[i].phy_id1)){
644 mii_phy->phy_types = mii_chip_table[i].phy_types;
645 if (mii_chip_table[i].phy_types == MIX)
646 mii_phy->phy_types =
647 (mii_status & (MII_STAT_CAN_TX_FDX | MII_STAT_CAN_TX)) ? LAN : HOME;
648 printk(KERN_INFO "%s: %s transceiver found "
649 "at address %d.\n",
650 dev_name,
651 mii_chip_table[i].name,
652 phy_addr);
653 break;
654 }
655
656 if( !mii_chip_table[i].phy_id1 ) {
657 printk(KERN_INFO "%s: Unknown PHY transceiver found at address %d.\n",
658 dev_name, phy_addr);
659 mii_phy->phy_types = UNKNOWN;
660 }
661 }
662
663 if (sis_priv->mii == NULL) {
664 printk(KERN_INFO "%s: No MII transceivers found!\n", dev_name);
665 return 0;
666 }
667
668
669 sis_priv->mii = NULL;
670 sis900_default_phy( net_dev );
671
672
673 if ((sis_priv->mii->phy_id0 == 0x001D) &&
674 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
675 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
676
677
678 if ((sis_priv->mii->phy_id0 == 0x0015) &&
679 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
680 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
681
682 if(status & MII_STAT_LINK){
683 while (poll_bit) {
684 yield();
685
686 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
687 if (time_after_eq(jiffies, timeout)) {
688 printk(KERN_WARNING "%s: reset phy and link down now\n",
689 dev_name);
690 return -ETIME;
691 }
692 }
693 }
694
695 if (sis_priv->chipset_rev == SIS630E_900_REV) {
696
697 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
698 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
699 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
700 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
701
702 }
703
704 if (sis_priv->mii->status & MII_STAT_LINK)
705 netif_carrier_on(net_dev);
706 else
707 netif_carrier_off(net_dev);
708
709 return 1;
710}
711
712
713
714
715
716
717
718
719
720
721static u16 sis900_default_phy(struct net_device * net_dev)
722{
723 struct sis900_private *sis_priv = netdev_priv(net_dev);
724 struct mii_phy *phy = NULL, *phy_home = NULL,
725 *default_phy = NULL, *phy_lan = NULL;
726 u16 status;
727
728 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
729 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
730 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
731
732
733 if ((status & MII_STAT_LINK) && !default_phy &&
734 (phy->phy_types != UNKNOWN))
735 default_phy = phy;
736 else {
737 status = mdio_read(net_dev, phy->phy_addr, MII_CONTROL);
738 mdio_write(net_dev, phy->phy_addr, MII_CONTROL,
739 status | MII_CNTL_AUTO | MII_CNTL_ISOLATE);
740 if (phy->phy_types == HOME)
741 phy_home = phy;
742 else if(phy->phy_types == LAN)
743 phy_lan = phy;
744 }
745 }
746
747 if (!default_phy && phy_home)
748 default_phy = phy_home;
749 else if (!default_phy && phy_lan)
750 default_phy = phy_lan;
751 else if (!default_phy)
752 default_phy = sis_priv->first_mii;
753
754 if (sis_priv->mii != default_phy) {
755 sis_priv->mii = default_phy;
756 sis_priv->cur_phy = default_phy->phy_addr;
757 printk(KERN_INFO "%s: Using transceiver found at address %d as default\n",
758 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
759 }
760
761 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
762
763 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
764 status &= (~MII_CNTL_ISOLATE);
765
766 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
767 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
768 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
769
770 return status;
771}
772
773
774
775
776
777
778
779
780
781
782
783static void sis900_set_capability(struct net_device *net_dev, struct mii_phy *phy)
784{
785 u16 cap;
786 u16 status;
787
788 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
789 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
790
791 cap = MII_NWAY_CSMA_CD |
792 ((phy->status & MII_STAT_CAN_TX_FDX)? MII_NWAY_TX_FDX:0) |
793 ((phy->status & MII_STAT_CAN_TX) ? MII_NWAY_TX:0) |
794 ((phy->status & MII_STAT_CAN_T_FDX) ? MII_NWAY_T_FDX:0)|
795 ((phy->status & MII_STAT_CAN_T) ? MII_NWAY_T:0);
796
797 mdio_write(net_dev, phy->phy_addr, MII_ANADV, cap);
798}
799
800
801
802#define eeprom_delay() inl(ee_addr)
803
804
805
806
807
808
809
810
811
812
813static u16 __devinit read_eeprom(long ioaddr, int location)
814{
815 int i;
816 u16 retval = 0;
817 long ee_addr = ioaddr + mear;
818 u32 read_cmd = location | EEread;
819
820 outl(0, ee_addr);
821 eeprom_delay();
822 outl(EECS, ee_addr);
823 eeprom_delay();
824
825
826 for (i = 8; i >= 0; i--) {
827 u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
828 outl(dataval, ee_addr);
829 eeprom_delay();
830 outl(dataval | EECLK, ee_addr);
831 eeprom_delay();
832 }
833 outl(EECS, ee_addr);
834 eeprom_delay();
835
836
837 for (i = 16; i > 0; i--) {
838 outl(EECS, ee_addr);
839 eeprom_delay();
840 outl(EECS | EECLK, ee_addr);
841 eeprom_delay();
842 retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
843 eeprom_delay();
844 }
845
846
847 outl(0, ee_addr);
848 eeprom_delay();
849
850 return retval;
851}
852
853
854
855
856#define mdio_delay() inl(mdio_addr)
857
858static void mdio_idle(long mdio_addr)
859{
860 outl(MDIO | MDDIR, mdio_addr);
861 mdio_delay();
862 outl(MDIO | MDDIR | MDC, mdio_addr);
863}
864
865
866static void mdio_reset(long mdio_addr)
867{
868 int i;
869
870 for (i = 31; i >= 0; i--) {
871 outl(MDDIR | MDIO, mdio_addr);
872 mdio_delay();
873 outl(MDDIR | MDIO | MDC, mdio_addr);
874 mdio_delay();
875 }
876}
877
878
879
880
881
882
883
884
885
886
887
888
889static int mdio_read(struct net_device *net_dev, int phy_id, int location)
890{
891 long mdio_addr = net_dev->base_addr + mear;
892 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
893 u16 retval = 0;
894 int i;
895
896 mdio_reset(mdio_addr);
897 mdio_idle(mdio_addr);
898
899 for (i = 15; i >= 0; i--) {
900 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
901 outl(dataval, mdio_addr);
902 mdio_delay();
903 outl(dataval | MDC, mdio_addr);
904 mdio_delay();
905 }
906
907
908 for (i = 16; i > 0; i--) {
909 outl(0, mdio_addr);
910 mdio_delay();
911 retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0);
912 outl(MDC, mdio_addr);
913 mdio_delay();
914 }
915 outl(0x00, mdio_addr);
916
917 return retval;
918}
919
920
921
922
923
924
925
926
927
928
929
930
931
932static void mdio_write(struct net_device *net_dev, int phy_id, int location,
933 int value)
934{
935 long mdio_addr = net_dev->base_addr + mear;
936 int mii_cmd = MIIwrite|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
937 int i;
938
939 mdio_reset(mdio_addr);
940 mdio_idle(mdio_addr);
941
942
943 for (i = 15; i >= 0; i--) {
944 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
945 outb(dataval, mdio_addr);
946 mdio_delay();
947 outb(dataval | MDC, mdio_addr);
948 mdio_delay();
949 }
950 mdio_delay();
951
952
953 for (i = 15; i >= 0; i--) {
954 int dataval = (value & (1 << i)) ? MDDIR | MDIO : MDDIR;
955 outl(dataval, mdio_addr);
956 mdio_delay();
957 outl(dataval | MDC, mdio_addr);
958 mdio_delay();
959 }
960 mdio_delay();
961
962
963 for (i = 2; i > 0; i--) {
964 outb(0, mdio_addr);
965 mdio_delay();
966 outb(MDC, mdio_addr);
967 mdio_delay();
968 }
969 outl(0x00, mdio_addr);
970}
971
972
973
974
975
976
977
978
979
980
981
982
983static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr)
984{
985 int i;
986 u16 status;
987
988 for (i = 0; i < 2; i++)
989 status = mdio_read(net_dev, phy_addr, MII_STATUS);
990
991 mdio_write( net_dev, phy_addr, MII_CONTROL, MII_CNTL_RESET );
992
993 return status;
994}
995
996#ifdef CONFIG_NET_POLL_CONTROLLER
997
998
999
1000
1001
1002static void sis900_poll(struct net_device *dev)
1003{
1004 disable_irq(dev->irq);
1005 sis900_interrupt(dev->irq, dev);
1006 enable_irq(dev->irq);
1007}
1008#endif
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018static int
1019sis900_open(struct net_device *net_dev)
1020{
1021 struct sis900_private *sis_priv = netdev_priv(net_dev);
1022 long ioaddr = net_dev->base_addr;
1023 int ret;
1024
1025
1026 sis900_reset(net_dev);
1027
1028
1029 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1030
1031 ret = request_irq(net_dev->irq, sis900_interrupt, IRQF_SHARED,
1032 net_dev->name, net_dev);
1033 if (ret)
1034 return ret;
1035
1036 sis900_init_rxfilter(net_dev);
1037
1038 sis900_init_tx_ring(net_dev);
1039 sis900_init_rx_ring(net_dev);
1040
1041 set_rx_mode(net_dev);
1042
1043 netif_start_queue(net_dev);
1044
1045
1046 sis900_set_mode(ioaddr, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1047
1048
1049 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1050 outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
1051 outl(IE, ioaddr + ier);
1052
1053 sis900_check_mode(net_dev, sis_priv->mii);
1054
1055
1056
1057 init_timer(&sis_priv->timer);
1058 sis_priv->timer.expires = jiffies + HZ;
1059 sis_priv->timer.data = (unsigned long)net_dev;
1060 sis_priv->timer.function = sis900_timer;
1061 add_timer(&sis_priv->timer);
1062
1063 return 0;
1064}
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074static void
1075sis900_init_rxfilter (struct net_device * net_dev)
1076{
1077 struct sis900_private *sis_priv = netdev_priv(net_dev);
1078 long ioaddr = net_dev->base_addr;
1079 u32 rfcrSave;
1080 u32 i;
1081
1082 rfcrSave = inl(rfcr + ioaddr);
1083
1084
1085 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
1086
1087
1088 for (i = 0 ; i < 3 ; i++) {
1089 u32 w;
1090
1091 w = (u32) *((u16 *)(net_dev->dev_addr)+i);
1092 outl((i << RFADDR_shift), ioaddr + rfcr);
1093 outl(w, ioaddr + rfdr);
1094
1095 if (netif_msg_hw(sis_priv)) {
1096 printk(KERN_DEBUG "%s: Receive Filter Addrss[%d]=%x\n",
1097 net_dev->name, i, inl(ioaddr + rfdr));
1098 }
1099 }
1100
1101
1102 outl(rfcrSave | RFEN, rfcr + ioaddr);
1103}
1104
1105
1106
1107
1108
1109
1110
1111
1112static void
1113sis900_init_tx_ring(struct net_device *net_dev)
1114{
1115 struct sis900_private *sis_priv = netdev_priv(net_dev);
1116 long ioaddr = net_dev->base_addr;
1117 int i;
1118
1119 sis_priv->tx_full = 0;
1120 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1121
1122 for (i = 0; i < NUM_TX_DESC; i++) {
1123 sis_priv->tx_skbuff[i] = NULL;
1124
1125 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1126 ((i+1)%NUM_TX_DESC)*sizeof(BufferDesc);
1127 sis_priv->tx_ring[i].cmdsts = 0;
1128 sis_priv->tx_ring[i].bufptr = 0;
1129 }
1130
1131
1132 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1133 if (netif_msg_hw(sis_priv))
1134 printk(KERN_DEBUG "%s: TX descriptor register loaded with: %8.8x\n",
1135 net_dev->name, inl(ioaddr + txdp));
1136}
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146static void
1147sis900_init_rx_ring(struct net_device *net_dev)
1148{
1149 struct sis900_private *sis_priv = netdev_priv(net_dev);
1150 long ioaddr = net_dev->base_addr;
1151 int i;
1152
1153 sis_priv->cur_rx = 0;
1154 sis_priv->dirty_rx = 0;
1155
1156
1157 for (i = 0; i < NUM_RX_DESC; i++) {
1158 sis_priv->rx_skbuff[i] = NULL;
1159
1160 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1161 ((i+1)%NUM_RX_DESC)*sizeof(BufferDesc);
1162 sis_priv->rx_ring[i].cmdsts = 0;
1163 sis_priv->rx_ring[i].bufptr = 0;
1164 }
1165
1166
1167 for (i = 0; i < NUM_RX_DESC; i++) {
1168 struct sk_buff *skb;
1169
1170 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1171
1172
1173
1174
1175 break;
1176 }
1177 sis_priv->rx_skbuff[i] = skb;
1178 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1179 sis_priv->rx_ring[i].bufptr = pci_map_single(sis_priv->pci_dev,
1180 skb->data, RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1181 }
1182 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1183
1184
1185 outl(sis_priv->rx_ring_dma, ioaddr + rxdp);
1186 if (netif_msg_hw(sis_priv))
1187 printk(KERN_DEBUG "%s: RX descriptor register loaded with: %8.8x\n",
1188 net_dev->name, inl(ioaddr + rxdp));
1189}
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218static void sis630_set_eq(struct net_device *net_dev, u8 revision)
1219{
1220 struct sis900_private *sis_priv = netdev_priv(net_dev);
1221 u16 reg14h, eq_value=0, max_value=0, min_value=0;
1222 int i, maxcount=10;
1223
1224 if ( !(revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1225 revision == SIS630A_900_REV || revision == SIS630ET_900_REV) )
1226 return;
1227
1228 if (netif_carrier_ok(net_dev)) {
1229 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1230 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1231 (0x2200 | reg14h) & 0xBFFF);
1232 for (i=0; i < maxcount; i++) {
1233 eq_value = (0x00F8 & mdio_read(net_dev,
1234 sis_priv->cur_phy, MII_RESV)) >> 3;
1235 if (i == 0)
1236 max_value=min_value=eq_value;
1237 max_value = (eq_value > max_value) ?
1238 eq_value : max_value;
1239 min_value = (eq_value < min_value) ?
1240 eq_value : min_value;
1241 }
1242
1243 if (revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1244 revision == SIS630ET_900_REV) {
1245 if (max_value < 5)
1246 eq_value = max_value;
1247 else if (max_value >= 5 && max_value < 15)
1248 eq_value = (max_value == min_value) ?
1249 max_value+2 : max_value+1;
1250 else if (max_value >= 15)
1251 eq_value=(max_value == min_value) ?
1252 max_value+6 : max_value+5;
1253 }
1254
1255 if (revision == SIS630A_900_REV &&
1256 (sis_priv->host_bridge_rev == SIS630B0 ||
1257 sis_priv->host_bridge_rev == SIS630B1)) {
1258 if (max_value == 0)
1259 eq_value = 3;
1260 else
1261 eq_value = (max_value + min_value + 1)/2;
1262 }
1263
1264 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1265 reg14h = (reg14h & 0xFF07) | ((eq_value << 3) & 0x00F8);
1266 reg14h = (reg14h | 0x6000) & 0xFDFF;
1267 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1268 } else {
1269 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1270 if (revision == SIS630A_900_REV &&
1271 (sis_priv->host_bridge_rev == SIS630B0 ||
1272 sis_priv->host_bridge_rev == SIS630B1))
1273 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1274 (reg14h | 0x2200) & 0xBFFF);
1275 else
1276 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1277 (reg14h | 0x2000) & 0xBFFF);
1278 }
1279}
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289static void sis900_timer(unsigned long data)
1290{
1291 struct net_device *net_dev = (struct net_device *)data;
1292 struct sis900_private *sis_priv = netdev_priv(net_dev);
1293 struct mii_phy *mii_phy = sis_priv->mii;
1294 static const int next_tick = 5*HZ;
1295 u16 status;
1296
1297 if (!sis_priv->autong_complete){
1298 int uninitialized_var(speed), duplex = 0;
1299
1300 sis900_read_mode(net_dev, &speed, &duplex);
1301 if (duplex){
1302 sis900_set_mode(net_dev->base_addr, speed, duplex);
1303 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1304 netif_start_queue(net_dev);
1305 }
1306
1307 sis_priv->timer.expires = jiffies + HZ;
1308 add_timer(&sis_priv->timer);
1309 return;
1310 }
1311
1312 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1313 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1314
1315
1316 if (!netif_carrier_ok(net_dev)) {
1317 LookForLink:
1318
1319 status = sis900_default_phy(net_dev);
1320 mii_phy = sis_priv->mii;
1321
1322 if (status & MII_STAT_LINK){
1323 sis900_check_mode(net_dev, mii_phy);
1324 netif_carrier_on(net_dev);
1325 }
1326 } else {
1327
1328 if (!(status & MII_STAT_LINK)){
1329 netif_carrier_off(net_dev);
1330 if(netif_msg_link(sis_priv))
1331 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1332
1333
1334 if ((mii_phy->phy_id0 == 0x001D) &&
1335 ((mii_phy->phy_id1 & 0xFFF0) == 0x8000))
1336 sis900_reset_phy(net_dev, sis_priv->cur_phy);
1337
1338 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1339
1340 goto LookForLink;
1341 }
1342 }
1343
1344 sis_priv->timer.expires = jiffies + next_tick;
1345 add_timer(&sis_priv->timer);
1346}
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360static void sis900_check_mode(struct net_device *net_dev, struct mii_phy *mii_phy)
1361{
1362 struct sis900_private *sis_priv = netdev_priv(net_dev);
1363 long ioaddr = net_dev->base_addr;
1364 int speed, duplex;
1365
1366 if (mii_phy->phy_types == LAN) {
1367 outl(~EXD & inl(ioaddr + cfg), ioaddr + cfg);
1368 sis900_set_capability(net_dev , mii_phy);
1369 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1370 } else {
1371 outl(EXD | inl(ioaddr + cfg), ioaddr + cfg);
1372 speed = HW_SPEED_HOME;
1373 duplex = FDX_CAPABLE_HALF_SELECTED;
1374 sis900_set_mode(ioaddr, speed, duplex);
1375 sis_priv->autong_complete = 1;
1376 }
1377}
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392static void sis900_set_mode (long ioaddr, int speed, int duplex)
1393{
1394 u32 tx_flags = 0, rx_flags = 0;
1395
1396 if (inl(ioaddr + cfg) & EDB_MASTER_EN) {
1397 tx_flags = TxATP | (DMA_BURST_64 << TxMXDMA_shift) |
1398 (TX_FILL_THRESH << TxFILLT_shift);
1399 rx_flags = DMA_BURST_64 << RxMXDMA_shift;
1400 } else {
1401 tx_flags = TxATP | (DMA_BURST_512 << TxMXDMA_shift) |
1402 (TX_FILL_THRESH << TxFILLT_shift);
1403 rx_flags = DMA_BURST_512 << RxMXDMA_shift;
1404 }
1405
1406 if (speed == HW_SPEED_HOME || speed == HW_SPEED_10_MBPS) {
1407 rx_flags |= (RxDRNT_10 << RxDRNT_shift);
1408 tx_flags |= (TxDRNT_10 << TxDRNT_shift);
1409 } else {
1410 rx_flags |= (RxDRNT_100 << RxDRNT_shift);
1411 tx_flags |= (TxDRNT_100 << TxDRNT_shift);
1412 }
1413
1414 if (duplex == FDX_CAPABLE_FULL_SELECTED) {
1415 tx_flags |= (TxCSI | TxHBI);
1416 rx_flags |= RxATX;
1417 }
1418
1419#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1420
1421 rx_flags |= RxAJAB;
1422#endif
1423
1424 outl (tx_flags, ioaddr + txcfg);
1425 outl (rx_flags, ioaddr + rxcfg);
1426}
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr)
1440{
1441 struct sis900_private *sis_priv = netdev_priv(net_dev);
1442 int i = 0;
1443 u32 status;
1444
1445 for (i = 0; i < 2; i++)
1446 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1447
1448 if (!(status & MII_STAT_LINK)){
1449 if(netif_msg_link(sis_priv))
1450 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1451 sis_priv->autong_complete = 1;
1452 netif_carrier_off(net_dev);
1453 return;
1454 }
1455
1456
1457 mdio_write(net_dev, phy_addr, MII_CONTROL,
1458 MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
1459 sis_priv->autong_complete = 0;
1460}
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex)
1475{
1476 struct sis900_private *sis_priv = netdev_priv(net_dev);
1477 struct mii_phy *phy = sis_priv->mii;
1478 int phy_addr = sis_priv->cur_phy;
1479 u32 status;
1480 u16 autoadv, autorec;
1481 int i;
1482
1483 for (i = 0; i < 2; i++)
1484 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1485
1486 if (!(status & MII_STAT_LINK))
1487 return;
1488
1489
1490 autoadv = mdio_read(net_dev, phy_addr, MII_ANADV);
1491 autorec = mdio_read(net_dev, phy_addr, MII_ANLPAR);
1492 status = autoadv & autorec;
1493
1494 *speed = HW_SPEED_10_MBPS;
1495 *duplex = FDX_CAPABLE_HALF_SELECTED;
1496
1497 if (status & (MII_NWAY_TX | MII_NWAY_TX_FDX))
1498 *speed = HW_SPEED_100_MBPS;
1499 if (status & ( MII_NWAY_TX_FDX | MII_NWAY_T_FDX))
1500 *duplex = FDX_CAPABLE_FULL_SELECTED;
1501
1502 sis_priv->autong_complete = 1;
1503
1504
1505 if ((phy->phy_id0 == 0x0000) && ((phy->phy_id1 & 0xFFF0) == 0x8200)) {
1506 if (mdio_read(net_dev, phy_addr, MII_CONTROL) & MII_CNTL_FDX)
1507 *duplex = FDX_CAPABLE_FULL_SELECTED;
1508 if (mdio_read(net_dev, phy_addr, 0x0019) & 0x01)
1509 *speed = HW_SPEED_100_MBPS;
1510 }
1511
1512 if(netif_msg_link(sis_priv))
1513 printk(KERN_INFO "%s: Media Link On %s %s-duplex\n",
1514 net_dev->name,
1515 *speed == HW_SPEED_100_MBPS ?
1516 "100mbps" : "10mbps",
1517 *duplex == FDX_CAPABLE_FULL_SELECTED ?
1518 "full" : "half");
1519}
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529static void sis900_tx_timeout(struct net_device *net_dev)
1530{
1531 struct sis900_private *sis_priv = netdev_priv(net_dev);
1532 long ioaddr = net_dev->base_addr;
1533 unsigned long flags;
1534 int i;
1535
1536 if(netif_msg_tx_err(sis_priv))
1537 printk(KERN_INFO "%s: Transmit timeout, status %8.8x %8.8x\n",
1538 net_dev->name, inl(ioaddr + cr), inl(ioaddr + isr));
1539
1540
1541 outl(0x0000, ioaddr + imr);
1542
1543
1544 spin_lock_irqsave(&sis_priv->lock, flags);
1545
1546
1547 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1548 for (i = 0; i < NUM_TX_DESC; i++) {
1549 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1550
1551 if (skb) {
1552 pci_unmap_single(sis_priv->pci_dev,
1553 sis_priv->tx_ring[i].bufptr, skb->len,
1554 PCI_DMA_TODEVICE);
1555 dev_kfree_skb_irq(skb);
1556 sis_priv->tx_skbuff[i] = NULL;
1557 sis_priv->tx_ring[i].cmdsts = 0;
1558 sis_priv->tx_ring[i].bufptr = 0;
1559 net_dev->stats.tx_dropped++;
1560 }
1561 }
1562 sis_priv->tx_full = 0;
1563 netif_wake_queue(net_dev);
1564
1565 spin_unlock_irqrestore(&sis_priv->lock, flags);
1566
1567 net_dev->trans_start = jiffies;
1568
1569
1570 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1571
1572
1573 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1574}
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586static netdev_tx_t
1587sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
1588{
1589 struct sis900_private *sis_priv = netdev_priv(net_dev);
1590 long ioaddr = net_dev->base_addr;
1591 unsigned int entry;
1592 unsigned long flags;
1593 unsigned int index_cur_tx, index_dirty_tx;
1594 unsigned int count_dirty_tx;
1595
1596
1597 if(!sis_priv->autong_complete){
1598 netif_stop_queue(net_dev);
1599 return NETDEV_TX_BUSY;
1600 }
1601
1602 spin_lock_irqsave(&sis_priv->lock, flags);
1603
1604
1605 entry = sis_priv->cur_tx % NUM_TX_DESC;
1606 sis_priv->tx_skbuff[entry] = skb;
1607
1608
1609 sis_priv->tx_ring[entry].bufptr = pci_map_single(sis_priv->pci_dev,
1610 skb->data, skb->len, PCI_DMA_TODEVICE);
1611 sis_priv->tx_ring[entry].cmdsts = (OWN | skb->len);
1612 outl(TxENA | inl(ioaddr + cr), ioaddr + cr);
1613
1614 sis_priv->cur_tx ++;
1615 index_cur_tx = sis_priv->cur_tx;
1616 index_dirty_tx = sis_priv->dirty_tx;
1617
1618 for (count_dirty_tx = 0; index_cur_tx != index_dirty_tx; index_dirty_tx++)
1619 count_dirty_tx ++;
1620
1621 if (index_cur_tx == index_dirty_tx) {
1622
1623 sis_priv->tx_full = 1;
1624 netif_stop_queue(net_dev);
1625 } else if (count_dirty_tx < NUM_TX_DESC) {
1626
1627 netif_start_queue(net_dev);
1628 } else {
1629
1630 sis_priv->tx_full = 1;
1631 netif_stop_queue(net_dev);
1632 }
1633
1634 spin_unlock_irqrestore(&sis_priv->lock, flags);
1635
1636 if (netif_msg_tx_queued(sis_priv))
1637 printk(KERN_DEBUG "%s: Queued Tx packet at %p size %d "
1638 "to slot %d.\n",
1639 net_dev->name, skb->data, (int)skb->len, entry);
1640
1641 return NETDEV_TX_OK;
1642}
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653static irqreturn_t sis900_interrupt(int irq, void *dev_instance)
1654{
1655 struct net_device *net_dev = dev_instance;
1656 struct sis900_private *sis_priv = netdev_priv(net_dev);
1657 int boguscnt = max_interrupt_work;
1658 long ioaddr = net_dev->base_addr;
1659 u32 status;
1660 unsigned int handled = 0;
1661
1662 spin_lock (&sis_priv->lock);
1663
1664 do {
1665 status = inl(ioaddr + isr);
1666
1667 if ((status & (HIBERR|TxURN|TxERR|TxIDLE|RxORN|RxERR|RxOK)) == 0)
1668
1669 break;
1670 handled = 1;
1671
1672
1673 if (status & (RxORN | RxERR | RxOK))
1674
1675 sis900_rx(net_dev);
1676
1677 if (status & (TxURN | TxERR | TxIDLE))
1678
1679 sis900_finish_xmit(net_dev);
1680
1681
1682 if (status & HIBERR) {
1683 if(netif_msg_intr(sis_priv))
1684 printk(KERN_INFO "%s: Abnormal interrupt, "
1685 "status %#8.8x.\n", net_dev->name, status);
1686 break;
1687 }
1688 if (--boguscnt < 0) {
1689 if(netif_msg_intr(sis_priv))
1690 printk(KERN_INFO "%s: Too much work at interrupt, "
1691 "interrupt status = %#8.8x.\n",
1692 net_dev->name, status);
1693 break;
1694 }
1695 } while (1);
1696
1697 if(netif_msg_intr(sis_priv))
1698 printk(KERN_DEBUG "%s: exiting interrupt, "
1699 "interrupt status = 0x%#8.8x.\n",
1700 net_dev->name, inl(ioaddr + isr));
1701
1702 spin_unlock (&sis_priv->lock);
1703 return IRQ_RETVAL(handled);
1704}
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716static int sis900_rx(struct net_device *net_dev)
1717{
1718 struct sis900_private *sis_priv = netdev_priv(net_dev);
1719 long ioaddr = net_dev->base_addr;
1720 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1721 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
1722 int rx_work_limit;
1723
1724 if (netif_msg_rx_status(sis_priv))
1725 printk(KERN_DEBUG "sis900_rx, cur_rx:%4.4d, dirty_rx:%4.4d "
1726 "status:0x%8.8x\n",
1727 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
1728 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1729
1730 while (rx_status & OWN) {
1731 unsigned int rx_size;
1732 unsigned int data_size;
1733
1734 if (--rx_work_limit < 0)
1735 break;
1736
1737 data_size = rx_status & DSIZE;
1738 rx_size = data_size - CRC_SIZE;
1739
1740#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1741
1742 if ((rx_status & TOOLONG) && data_size <= MAX_FRAME_SIZE)
1743 rx_status &= (~ ((unsigned int)TOOLONG));
1744#endif
1745
1746 if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) {
1747
1748 if (netif_msg_rx_err(sis_priv))
1749 printk(KERN_DEBUG "%s: Corrupted packet "
1750 "received, buffer status = 0x%8.8x/%d.\n",
1751 net_dev->name, rx_status, data_size);
1752 net_dev->stats.rx_errors++;
1753 if (rx_status & OVERRUN)
1754 net_dev->stats.rx_over_errors++;
1755 if (rx_status & (TOOLONG|RUNT))
1756 net_dev->stats.rx_length_errors++;
1757 if (rx_status & (RXISERR | FAERR))
1758 net_dev->stats.rx_frame_errors++;
1759 if (rx_status & CRCERR)
1760 net_dev->stats.rx_crc_errors++;
1761
1762 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1763 } else {
1764 struct sk_buff * skb;
1765 struct sk_buff * rx_skb;
1766
1767 pci_unmap_single(sis_priv->pci_dev,
1768 sis_priv->rx_ring[entry].bufptr, RX_BUF_SIZE,
1769 PCI_DMA_FROMDEVICE);
1770
1771
1772
1773 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1774
1775
1776
1777
1778
1779
1780 skb = sis_priv->rx_skbuff[entry];
1781 net_dev->stats.rx_dropped++;
1782 goto refill_rx_ring;
1783 }
1784
1785
1786
1787
1788 if (sis_priv->rx_skbuff[entry] == NULL) {
1789 if (netif_msg_rx_err(sis_priv))
1790 printk(KERN_WARNING "%s: NULL pointer "
1791 "encountered in Rx ring\n"
1792 "cur_rx:%4.4d, dirty_rx:%4.4d\n",
1793 net_dev->name, sis_priv->cur_rx,
1794 sis_priv->dirty_rx);
1795 dev_kfree_skb(skb);
1796 break;
1797 }
1798
1799
1800 rx_skb = sis_priv->rx_skbuff[entry];
1801 skb_put(rx_skb, rx_size);
1802 rx_skb->protocol = eth_type_trans(rx_skb, net_dev);
1803 netif_rx(rx_skb);
1804
1805
1806 if ((rx_status & BCAST) == MCAST)
1807 net_dev->stats.multicast++;
1808 net_dev->stats.rx_bytes += rx_size;
1809 net_dev->stats.rx_packets++;
1810 sis_priv->dirty_rx++;
1811refill_rx_ring:
1812 sis_priv->rx_skbuff[entry] = skb;
1813 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1814 sis_priv->rx_ring[entry].bufptr =
1815 pci_map_single(sis_priv->pci_dev, skb->data,
1816 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1817 }
1818 sis_priv->cur_rx++;
1819 entry = sis_priv->cur_rx % NUM_RX_DESC;
1820 rx_status = sis_priv->rx_ring[entry].cmdsts;
1821 }
1822
1823
1824
1825 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1826 struct sk_buff *skb;
1827
1828 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1829
1830 if (sis_priv->rx_skbuff[entry] == NULL) {
1831 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1832
1833
1834
1835
1836 if (netif_msg_rx_err(sis_priv))
1837 printk(KERN_INFO "%s: Memory squeeze, "
1838 "deferring packet.\n",
1839 net_dev->name);
1840 net_dev->stats.rx_dropped++;
1841 break;
1842 }
1843 sis_priv->rx_skbuff[entry] = skb;
1844 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1845 sis_priv->rx_ring[entry].bufptr =
1846 pci_map_single(sis_priv->pci_dev, skb->data,
1847 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1848 }
1849 }
1850
1851 outl(RxENA | inl(ioaddr + cr), ioaddr + cr );
1852
1853 return 0;
1854}
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866static void sis900_finish_xmit (struct net_device *net_dev)
1867{
1868 struct sis900_private *sis_priv = netdev_priv(net_dev);
1869
1870 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1871 struct sk_buff *skb;
1872 unsigned int entry;
1873 u32 tx_status;
1874
1875 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1876 tx_status = sis_priv->tx_ring[entry].cmdsts;
1877
1878 if (tx_status & OWN) {
1879
1880
1881
1882 break;
1883 }
1884
1885 if (tx_status & (ABORT | UNDERRUN | OWCOLL)) {
1886
1887 if (netif_msg_tx_err(sis_priv))
1888 printk(KERN_DEBUG "%s: Transmit "
1889 "error, Tx status %8.8x.\n",
1890 net_dev->name, tx_status);
1891 net_dev->stats.tx_errors++;
1892 if (tx_status & UNDERRUN)
1893 net_dev->stats.tx_fifo_errors++;
1894 if (tx_status & ABORT)
1895 net_dev->stats.tx_aborted_errors++;
1896 if (tx_status & NOCARRIER)
1897 net_dev->stats.tx_carrier_errors++;
1898 if (tx_status & OWCOLL)
1899 net_dev->stats.tx_window_errors++;
1900 } else {
1901
1902 net_dev->stats.collisions += (tx_status & COLCNT) >> 16;
1903 net_dev->stats.tx_bytes += tx_status & DSIZE;
1904 net_dev->stats.tx_packets++;
1905 }
1906
1907 skb = sis_priv->tx_skbuff[entry];
1908 pci_unmap_single(sis_priv->pci_dev,
1909 sis_priv->tx_ring[entry].bufptr, skb->len,
1910 PCI_DMA_TODEVICE);
1911 dev_kfree_skb_irq(skb);
1912 sis_priv->tx_skbuff[entry] = NULL;
1913 sis_priv->tx_ring[entry].bufptr = 0;
1914 sis_priv->tx_ring[entry].cmdsts = 0;
1915 }
1916
1917 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1918 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1919
1920
1921 sis_priv->tx_full = 0;
1922 netif_wake_queue (net_dev);
1923 }
1924}
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934static int sis900_close(struct net_device *net_dev)
1935{
1936 long ioaddr = net_dev->base_addr;
1937 struct sis900_private *sis_priv = netdev_priv(net_dev);
1938 struct sk_buff *skb;
1939 int i;
1940
1941 netif_stop_queue(net_dev);
1942
1943
1944 outl(0x0000, ioaddr + imr);
1945 outl(0x0000, ioaddr + ier);
1946
1947
1948 outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr);
1949
1950 del_timer(&sis_priv->timer);
1951
1952 free_irq(net_dev->irq, net_dev);
1953
1954
1955 for (i = 0; i < NUM_RX_DESC; i++) {
1956 skb = sis_priv->rx_skbuff[i];
1957 if (skb) {
1958 pci_unmap_single(sis_priv->pci_dev,
1959 sis_priv->rx_ring[i].bufptr,
1960 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1961 dev_kfree_skb(skb);
1962 sis_priv->rx_skbuff[i] = NULL;
1963 }
1964 }
1965 for (i = 0; i < NUM_TX_DESC; i++) {
1966 skb = sis_priv->tx_skbuff[i];
1967 if (skb) {
1968 pci_unmap_single(sis_priv->pci_dev,
1969 sis_priv->tx_ring[i].bufptr, skb->len,
1970 PCI_DMA_TODEVICE);
1971 dev_kfree_skb(skb);
1972 sis_priv->tx_skbuff[i] = NULL;
1973 }
1974 }
1975
1976
1977
1978 return 0;
1979}
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989static void sis900_get_drvinfo(struct net_device *net_dev,
1990 struct ethtool_drvinfo *info)
1991{
1992 struct sis900_private *sis_priv = netdev_priv(net_dev);
1993
1994 strcpy (info->driver, SIS900_MODULE_NAME);
1995 strcpy (info->version, SIS900_DRV_VERSION);
1996 strcpy (info->bus_info, pci_name(sis_priv->pci_dev));
1997}
1998
1999static u32 sis900_get_msglevel(struct net_device *net_dev)
2000{
2001 struct sis900_private *sis_priv = netdev_priv(net_dev);
2002 return sis_priv->msg_enable;
2003}
2004
2005static void sis900_set_msglevel(struct net_device *net_dev, u32 value)
2006{
2007 struct sis900_private *sis_priv = netdev_priv(net_dev);
2008 sis_priv->msg_enable = value;
2009}
2010
2011static u32 sis900_get_link(struct net_device *net_dev)
2012{
2013 struct sis900_private *sis_priv = netdev_priv(net_dev);
2014 return mii_link_ok(&sis_priv->mii_info);
2015}
2016
2017static int sis900_get_settings(struct net_device *net_dev,
2018 struct ethtool_cmd *cmd)
2019{
2020 struct sis900_private *sis_priv = netdev_priv(net_dev);
2021 spin_lock_irq(&sis_priv->lock);
2022 mii_ethtool_gset(&sis_priv->mii_info, cmd);
2023 spin_unlock_irq(&sis_priv->lock);
2024 return 0;
2025}
2026
2027static int sis900_set_settings(struct net_device *net_dev,
2028 struct ethtool_cmd *cmd)
2029{
2030 struct sis900_private *sis_priv = netdev_priv(net_dev);
2031 int rt;
2032 spin_lock_irq(&sis_priv->lock);
2033 rt = mii_ethtool_sset(&sis_priv->mii_info, cmd);
2034 spin_unlock_irq(&sis_priv->lock);
2035 return rt;
2036}
2037
2038static int sis900_nway_reset(struct net_device *net_dev)
2039{
2040 struct sis900_private *sis_priv = netdev_priv(net_dev);
2041 return mii_nway_restart(&sis_priv->mii_info);
2042}
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055static int sis900_set_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2056{
2057 struct sis900_private *sis_priv = netdev_priv(net_dev);
2058 long pmctrl_addr = net_dev->base_addr + pmctrl;
2059 u32 cfgpmcsr = 0, pmctrl_bits = 0;
2060
2061 if (wol->wolopts == 0) {
2062 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2063 cfgpmcsr &= ~PME_EN;
2064 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2065 outl(pmctrl_bits, pmctrl_addr);
2066 if (netif_msg_wol(sis_priv))
2067 printk(KERN_DEBUG "%s: Wake on LAN disabled\n", net_dev->name);
2068 return 0;
2069 }
2070
2071 if (wol->wolopts & (WAKE_MAGICSECURE | WAKE_UCAST | WAKE_MCAST
2072 | WAKE_BCAST | WAKE_ARP))
2073 return -EINVAL;
2074
2075 if (wol->wolopts & WAKE_MAGIC)
2076 pmctrl_bits |= MAGICPKT;
2077 if (wol->wolopts & WAKE_PHY)
2078 pmctrl_bits |= LINKON;
2079
2080 outl(pmctrl_bits, pmctrl_addr);
2081
2082 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2083 cfgpmcsr |= PME_EN;
2084 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2085 if (netif_msg_wol(sis_priv))
2086 printk(KERN_DEBUG "%s: Wake on LAN enabled\n", net_dev->name);
2087
2088 return 0;
2089}
2090
2091static void sis900_get_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2092{
2093 long pmctrl_addr = net_dev->base_addr + pmctrl;
2094 u32 pmctrl_bits;
2095
2096 pmctrl_bits = inl(pmctrl_addr);
2097 if (pmctrl_bits & MAGICPKT)
2098 wol->wolopts |= WAKE_MAGIC;
2099 if (pmctrl_bits & LINKON)
2100 wol->wolopts |= WAKE_PHY;
2101
2102 wol->supported = (WAKE_PHY | WAKE_MAGIC);
2103}
2104
2105static const struct ethtool_ops sis900_ethtool_ops = {
2106 .get_drvinfo = sis900_get_drvinfo,
2107 .get_msglevel = sis900_get_msglevel,
2108 .set_msglevel = sis900_set_msglevel,
2109 .get_link = sis900_get_link,
2110 .get_settings = sis900_get_settings,
2111 .set_settings = sis900_set_settings,
2112 .nway_reset = sis900_nway_reset,
2113 .get_wol = sis900_get_wol,
2114 .set_wol = sis900_set_wol
2115};
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2127{
2128 struct sis900_private *sis_priv = netdev_priv(net_dev);
2129 struct mii_ioctl_data *data = if_mii(rq);
2130
2131 switch(cmd) {
2132 case SIOCGMIIPHY:
2133 data->phy_id = sis_priv->mii->phy_addr;
2134
2135
2136 case SIOCGMIIREG:
2137 data->val_out = mdio_read(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
2138 return 0;
2139
2140 case SIOCSMIIREG:
2141 mdio_write(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2142 return 0;
2143 default:
2144 return -EOPNOTSUPP;
2145 }
2146}
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158static int sis900_set_config(struct net_device *dev, struct ifmap *map)
2159{
2160 struct sis900_private *sis_priv = netdev_priv(dev);
2161 struct mii_phy *mii_phy = sis_priv->mii;
2162
2163 u16 status;
2164
2165 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
2166
2167
2168
2169
2170
2171
2172 switch(map->port){
2173 case IF_PORT_UNKNOWN:
2174 dev->if_port = map->port;
2175
2176
2177
2178
2179
2180 netif_carrier_off(dev);
2181
2182
2183 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2184
2185
2186
2187
2188
2189 mdio_write(dev, mii_phy->phy_addr,
2190 MII_CONTROL, status | MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
2191
2192 break;
2193
2194 case IF_PORT_10BASET:
2195 dev->if_port = map->port;
2196
2197
2198
2199
2200
2201
2202 netif_carrier_off(dev);
2203
2204
2205
2206 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2207
2208
2209 mdio_write(dev, mii_phy->phy_addr,
2210 MII_CONTROL, status & ~(MII_CNTL_SPEED |
2211 MII_CNTL_AUTO));
2212 break;
2213
2214 case IF_PORT_100BASET:
2215 case IF_PORT_100BASETX:
2216 dev->if_port = map->port;
2217
2218
2219
2220
2221
2222
2223 netif_carrier_off(dev);
2224
2225
2226
2227 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2228 mdio_write(dev, mii_phy->phy_addr,
2229 MII_CONTROL, (status & ~MII_CNTL_SPEED) |
2230 MII_CNTL_SPEED);
2231
2232 break;
2233
2234 case IF_PORT_10BASE2:
2235 case IF_PORT_AUI:
2236 case IF_PORT_100BASEFX:
2237
2238 return -EOPNOTSUPP;
2239 break;
2240
2241 default:
2242 return -EINVAL;
2243 }
2244 }
2245 return 0;
2246}
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259static inline u16 sis900_mcast_bitnr(u8 *addr, u8 revision)
2260{
2261
2262 u32 crc = ether_crc(6, addr);
2263
2264
2265 if ((revision >= SIS635A_900_REV) || (revision == SIS900B_900_REV))
2266 return (int)(crc >> 24);
2267 else
2268 return (int)(crc >> 25);
2269}
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280static void set_rx_mode(struct net_device *net_dev)
2281{
2282 long ioaddr = net_dev->base_addr;
2283 struct sis900_private *sis_priv = netdev_priv(net_dev);
2284 u16 mc_filter[16] = {0};
2285 int i, table_entries;
2286 u32 rx_mode;
2287
2288
2289 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2290 (sis_priv->chipset_rev == SIS900B_900_REV))
2291 table_entries = 16;
2292 else
2293 table_entries = 8;
2294
2295 if (net_dev->flags & IFF_PROMISC) {
2296
2297 rx_mode = RFPromiscuous;
2298 for (i = 0; i < table_entries; i++)
2299 mc_filter[i] = 0xffff;
2300 } else if ((netdev_mc_count(net_dev) > multicast_filter_limit) ||
2301 (net_dev->flags & IFF_ALLMULTI)) {
2302
2303 rx_mode = RFAAB | RFAAM;
2304 for (i = 0; i < table_entries; i++)
2305 mc_filter[i] = 0xffff;
2306 } else {
2307
2308
2309
2310 struct netdev_hw_addr *ha;
2311 rx_mode = RFAAB;
2312
2313 netdev_for_each_mc_addr(ha, net_dev) {
2314 unsigned int bit_nr;
2315
2316 bit_nr = sis900_mcast_bitnr(ha->addr,
2317 sis_priv->chipset_rev);
2318 mc_filter[bit_nr >> 4] |= (1 << (bit_nr & 0xf));
2319 }
2320 }
2321
2322
2323 for (i = 0; i < table_entries; i++) {
2324
2325 outl((u32)(0x00000004+i) << RFADDR_shift, ioaddr + rfcr);
2326 outl(mc_filter[i], ioaddr + rfdr);
2327 }
2328
2329 outl(RFEN | rx_mode, ioaddr + rfcr);
2330
2331
2332
2333 if (net_dev->flags & IFF_LOOPBACK) {
2334 u32 cr_saved;
2335
2336 cr_saved = inl(ioaddr + cr);
2337 outl(cr_saved | TxDIS | RxDIS, ioaddr + cr);
2338
2339 outl(inl(ioaddr + txcfg) | TxMLB, ioaddr + txcfg);
2340 outl(inl(ioaddr + rxcfg) | RxATX, ioaddr + rxcfg);
2341
2342 outl(cr_saved, ioaddr + cr);
2343 }
2344}
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355static void sis900_reset(struct net_device *net_dev)
2356{
2357 struct sis900_private *sis_priv = netdev_priv(net_dev);
2358 long ioaddr = net_dev->base_addr;
2359 int i = 0;
2360 u32 status = TxRCMP | RxRCMP;
2361
2362 outl(0, ioaddr + ier);
2363 outl(0, ioaddr + imr);
2364 outl(0, ioaddr + rfcr);
2365
2366 outl(RxRESET | TxRESET | RESET | inl(ioaddr + cr), ioaddr + cr);
2367
2368
2369 while (status && (i++ < 1000)) {
2370 status ^= (inl(isr + ioaddr) & status);
2371 }
2372
2373 if( (sis_priv->chipset_rev >= SIS635A_900_REV) ||
2374 (sis_priv->chipset_rev == SIS900B_900_REV) )
2375 outl(PESEL | RND_CNT, ioaddr + cfg);
2376 else
2377 outl(PESEL, ioaddr + cfg);
2378}
2379
2380
2381
2382
2383
2384
2385
2386
2387static void __devexit sis900_remove(struct pci_dev *pci_dev)
2388{
2389 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2390 struct sis900_private *sis_priv = netdev_priv(net_dev);
2391 struct mii_phy *phy = NULL;
2392
2393 while (sis_priv->first_mii) {
2394 phy = sis_priv->first_mii;
2395 sis_priv->first_mii = phy->next;
2396 kfree(phy);
2397 }
2398
2399 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2400 sis_priv->rx_ring_dma);
2401 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2402 sis_priv->tx_ring_dma);
2403 unregister_netdev(net_dev);
2404 free_netdev(net_dev);
2405 pci_release_regions(pci_dev);
2406 pci_set_drvdata(pci_dev, NULL);
2407}
2408
2409#ifdef CONFIG_PM
2410
2411static int sis900_suspend(struct pci_dev *pci_dev, pm_message_t state)
2412{
2413 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2414 long ioaddr = net_dev->base_addr;
2415
2416 if(!netif_running(net_dev))
2417 return 0;
2418
2419 netif_stop_queue(net_dev);
2420 netif_device_detach(net_dev);
2421
2422
2423 outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr);
2424
2425 pci_set_power_state(pci_dev, PCI_D3hot);
2426 pci_save_state(pci_dev);
2427
2428 return 0;
2429}
2430
2431static int sis900_resume(struct pci_dev *pci_dev)
2432{
2433 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2434 struct sis900_private *sis_priv = netdev_priv(net_dev);
2435 long ioaddr = net_dev->base_addr;
2436
2437 if(!netif_running(net_dev))
2438 return 0;
2439 pci_restore_state(pci_dev);
2440 pci_set_power_state(pci_dev, PCI_D0);
2441
2442 sis900_init_rxfilter(net_dev);
2443
2444 sis900_init_tx_ring(net_dev);
2445 sis900_init_rx_ring(net_dev);
2446
2447 set_rx_mode(net_dev);
2448
2449 netif_device_attach(net_dev);
2450 netif_start_queue(net_dev);
2451
2452
2453 sis900_set_mode(ioaddr, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
2454
2455
2456 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
2457 outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
2458 outl(IE, ioaddr + ier);
2459
2460 sis900_check_mode(net_dev, sis_priv->mii);
2461
2462 return 0;
2463}
2464#endif
2465
2466static struct pci_driver sis900_pci_driver = {
2467 .name = SIS900_MODULE_NAME,
2468 .id_table = sis900_pci_tbl,
2469 .probe = sis900_probe,
2470 .remove = __devexit_p(sis900_remove),
2471#ifdef CONFIG_PM
2472 .suspend = sis900_suspend,
2473 .resume = sis900_resume,
2474#endif
2475};
2476
2477static int __init sis900_init_module(void)
2478{
2479
2480#ifdef MODULE
2481 printk(version);
2482#endif
2483
2484 return pci_register_driver(&sis900_pci_driver);
2485}
2486
2487static void __exit sis900_cleanup_module(void)
2488{
2489 pci_unregister_driver(&sis900_pci_driver);
2490}
2491
2492module_init(sis900_init_module);
2493module_exit(sis900_cleanup_module);
2494
2495