linux/drivers/net/wireless/b43/phy_n.c
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   1/*
   2
   3  Broadcom B43 wireless driver
   4  IEEE 802.11n PHY support
   5
   6  Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8  This program is free software; you can redistribute it and/or modify
   9  it under the terms of the GNU General Public License as published by
  10  the Free Software Foundation; either version 2 of the License, or
  11  (at your option) any later version.
  12
  13  This program is distributed in the hope that it will be useful,
  14  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  GNU General Public License for more details.
  17
  18  You should have received a copy of the GNU General Public License
  19  along with this program; see the file COPYING.  If not, write to
  20  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21  Boston, MA 02110-1301, USA.
  22
  23*/
  24
  25#include <linux/delay.h>
  26#include <linux/slab.h>
  27#include <linux/types.h>
  28
  29#include "b43.h"
  30#include "phy_n.h"
  31#include "tables_nphy.h"
  32#include "radio_2055.h"
  33#include "radio_2056.h"
  34#include "main.h"
  35
  36struct nphy_txgains {
  37        u16 txgm[2];
  38        u16 pga[2];
  39        u16 pad[2];
  40        u16 ipa[2];
  41};
  42
  43struct nphy_iqcal_params {
  44        u16 txgm;
  45        u16 pga;
  46        u16 pad;
  47        u16 ipa;
  48        u16 cal_gain;
  49        u16 ncorr[5];
  50};
  51
  52struct nphy_iq_est {
  53        s32 iq0_prod;
  54        u32 i0_pwr;
  55        u32 q0_pwr;
  56        s32 iq1_prod;
  57        u32 i1_pwr;
  58        u32 q1_pwr;
  59};
  60
  61enum b43_nphy_rf_sequence {
  62        B43_RFSEQ_RX2TX,
  63        B43_RFSEQ_TX2RX,
  64        B43_RFSEQ_RESET2RX,
  65        B43_RFSEQ_UPDATE_GAINH,
  66        B43_RFSEQ_UPDATE_GAINL,
  67        B43_RFSEQ_UPDATE_GAINU,
  68};
  69
  70enum b43_nphy_rssi_type {
  71        B43_NPHY_RSSI_X = 0,
  72        B43_NPHY_RSSI_Y,
  73        B43_NPHY_RSSI_Z,
  74        B43_NPHY_RSSI_PWRDET,
  75        B43_NPHY_RSSI_TSSI_I,
  76        B43_NPHY_RSSI_TSSI_Q,
  77        B43_NPHY_RSSI_TBD,
  78};
  79
  80static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  81                                                bool enable);
  82static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  83                                        u8 *events, u8 *delays, u8 length);
  84static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  85                                       enum b43_nphy_rf_sequence seq);
  86static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  87                                                u16 value, u8 core, bool off);
  88static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  89                                                u16 value, u8 core);
  90
  91void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  92{//TODO
  93}
  94
  95static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  96{//TODO
  97}
  98
  99static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 100                                                        bool ignore_tssi)
 101{//TODO
 102        return B43_TXPWR_RES_DONE;
 103}
 104
 105static void b43_chantab_radio_upload(struct b43_wldev *dev,
 106                                const struct b43_nphy_channeltab_entry_rev2 *e)
 107{
 108        b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 109        b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 110        b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 111        b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 112        b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 113
 114        b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 115        b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 116        b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 117        b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 118        b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 119
 120        b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 121        b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 122        b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 123        b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 124        b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 125
 126        b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 127        b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 128        b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 129        b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 130        b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 131
 132        b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 133        b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 134        b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 135        b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 136        b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 137
 138        b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 139        b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 140}
 141
 142static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 143                                const struct b43_nphy_channeltab_entry_rev3 *e)
 144{
 145        b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 146        b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 147        b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 148        b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 149        b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 150        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 151                                        e->radio_syn_pll_loopfilter1);
 152        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 153                                        e->radio_syn_pll_loopfilter2);
 154        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 155                                        e->radio_syn_pll_loopfilter3);
 156        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 157                                        e->radio_syn_pll_loopfilter4);
 158        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 159                                        e->radio_syn_pll_loopfilter5);
 160        b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 161                                        e->radio_syn_reserved_addr27);
 162        b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 163                                        e->radio_syn_reserved_addr28);
 164        b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 165                                        e->radio_syn_reserved_addr29);
 166        b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 167                                        e->radio_syn_logen_vcobuf1);
 168        b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 169        b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 170        b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 171
 172        b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 173                                        e->radio_rx0_lnaa_tune);
 174        b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 175                                        e->radio_rx0_lnag_tune);
 176
 177        b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 178                                        e->radio_tx0_intpaa_boost_tune);
 179        b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 180                                        e->radio_tx0_intpag_boost_tune);
 181        b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 182                                        e->radio_tx0_pada_boost_tune);
 183        b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 184                                        e->radio_tx0_padg_boost_tune);
 185        b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 186                                        e->radio_tx0_pgaa_boost_tune);
 187        b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 188                                        e->radio_tx0_pgag_boost_tune);
 189        b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 190                                        e->radio_tx0_mixa_boost_tune);
 191        b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 192                                        e->radio_tx0_mixg_boost_tune);
 193
 194        b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 195                                        e->radio_rx1_lnaa_tune);
 196        b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 197                                        e->radio_rx1_lnag_tune);
 198
 199        b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 200                                        e->radio_tx1_intpaa_boost_tune);
 201        b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 202                                        e->radio_tx1_intpag_boost_tune);
 203        b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 204                                        e->radio_tx1_pada_boost_tune);
 205        b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 206                                        e->radio_tx1_padg_boost_tune);
 207        b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 208                                        e->radio_tx1_pgaa_boost_tune);
 209        b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 210                                        e->radio_tx1_pgag_boost_tune);
 211        b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 212                                        e->radio_tx1_mixa_boost_tune);
 213        b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 214                                        e->radio_tx1_mixg_boost_tune);
 215}
 216
 217/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 218static void b43_radio_2056_setup(struct b43_wldev *dev,
 219                                const struct b43_nphy_channeltab_entry_rev3 *e)
 220{
 221        B43_WARN_ON(dev->phy.rev < 3);
 222
 223        b43_chantab_radio_2056_upload(dev, e);
 224        /* TODO */
 225        udelay(50);
 226        /* VCO calibration */
 227        b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 228        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 229        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 230        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 231        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 232        udelay(300);
 233}
 234
 235static void b43_chantab_phy_upload(struct b43_wldev *dev,
 236                                   const struct b43_phy_n_sfo_cfg *e)
 237{
 238        b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 239        b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 240        b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 241        b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 242        b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 243        b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 244}
 245
 246/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
 247static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
 248{
 249        struct b43_phy_n *nphy = dev->phy.n;
 250        u8 i;
 251        u16 tmp;
 252
 253        if (nphy->hang_avoid)
 254                b43_nphy_stay_in_carrier_search(dev, 1);
 255
 256        nphy->txpwrctrl = enable;
 257        if (!enable) {
 258                if (dev->phy.rev >= 3)
 259                        ; /* TODO */
 260
 261                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
 262                for (i = 0; i < 84; i++)
 263                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 264
 265                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
 266                for (i = 0; i < 84; i++)
 267                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 268
 269                tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 270                if (dev->phy.rev >= 3)
 271                        tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 272                b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
 273
 274                if (dev->phy.rev >= 3) {
 275                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 276                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 277                } else {
 278                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 279                }
 280
 281                if (dev->phy.rev == 2)
 282                        b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 283                                ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
 284                else if (dev->phy.rev < 2)
 285                        b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 286                                ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
 287
 288                if (dev->phy.rev < 2 && 0)
 289                        ; /* TODO */
 290        } else {
 291                b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
 292        }
 293
 294        if (nphy->hang_avoid)
 295                b43_nphy_stay_in_carrier_search(dev, 0);
 296}
 297
 298/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 299static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 300{
 301        struct b43_phy_n *nphy = dev->phy.n;
 302        struct ssb_sprom *sprom = &(dev->sdev->bus->sprom);
 303
 304        u8 txpi[2], bbmult, i;
 305        u16 tmp, radio_gain, dac_gain;
 306        u16 freq = dev->phy.channel_freq;
 307        u32 txgain;
 308        /* u32 gaintbl; rev3+ */
 309
 310        if (nphy->hang_avoid)
 311                b43_nphy_stay_in_carrier_search(dev, 1);
 312
 313        if (dev->phy.rev >= 3) {
 314                txpi[0] = 40;
 315                txpi[1] = 40;
 316        } else if (sprom->revision < 4) {
 317                txpi[0] = 72;
 318                txpi[1] = 72;
 319        } else {
 320                if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 321                        txpi[0] = sprom->txpid2g[0];
 322                        txpi[1] = sprom->txpid2g[1];
 323                } else if (freq >= 4900 && freq < 5100) {
 324                        txpi[0] = sprom->txpid5gl[0];
 325                        txpi[1] = sprom->txpid5gl[1];
 326                } else if (freq >= 5100 && freq < 5500) {
 327                        txpi[0] = sprom->txpid5g[0];
 328                        txpi[1] = sprom->txpid5g[1];
 329                } else if (freq >= 5500) {
 330                        txpi[0] = sprom->txpid5gh[0];
 331                        txpi[1] = sprom->txpid5gh[1];
 332                } else {
 333                        txpi[0] = 91;
 334                        txpi[1] = 91;
 335                }
 336        }
 337
 338        /*
 339        for (i = 0; i < 2; i++) {
 340                nphy->txpwrindex[i].index_internal = txpi[i];
 341                nphy->txpwrindex[i].index_internal_save = txpi[i];
 342        }
 343        */
 344
 345        for (i = 0; i < 2; i++) {
 346                if (dev->phy.rev >= 3) {
 347                        /* FIXME: support 5GHz */
 348                        txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 349                        radio_gain = (txgain >> 16) & 0x1FFFF;
 350                } else {
 351                        txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
 352                        radio_gain = (txgain >> 16) & 0x1FFF;
 353                }
 354
 355                dac_gain = (txgain >> 8) & 0x3F;
 356                bbmult = txgain & 0xFF;
 357
 358                if (dev->phy.rev >= 3) {
 359                        if (i == 0)
 360                                b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 361                        else
 362                                b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 363                } else {
 364                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 365                }
 366
 367                if (i == 0)
 368                        b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
 369                else
 370                        b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
 371
 372                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
 373                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
 374
 375                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 376                tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 377
 378                if (i == 0)
 379                        tmp = (tmp & 0x00FF) | (bbmult << 8);
 380                else
 381                        tmp = (tmp & 0xFF00) | bbmult;
 382
 383                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 384                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
 385
 386                if (0)
 387                        ; /* TODO */
 388        }
 389
 390        b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
 391
 392        if (nphy->hang_avoid)
 393                b43_nphy_stay_in_carrier_search(dev, 0);
 394}
 395
 396
 397/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 398static void b43_radio_2055_setup(struct b43_wldev *dev,
 399                                const struct b43_nphy_channeltab_entry_rev2 *e)
 400{
 401        B43_WARN_ON(dev->phy.rev >= 3);
 402
 403        b43_chantab_radio_upload(dev, e);
 404        udelay(50);
 405        b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 406        b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 407        b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 408        b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 409        udelay(300);
 410}
 411
 412static void b43_radio_init2055_pre(struct b43_wldev *dev)
 413{
 414        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 415                     ~B43_NPHY_RFCTL_CMD_PORFORCE);
 416        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 417                    B43_NPHY_RFCTL_CMD_CHIP0PU |
 418                    B43_NPHY_RFCTL_CMD_OEPORFORCE);
 419        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 420                    B43_NPHY_RFCTL_CMD_PORFORCE);
 421}
 422
 423static void b43_radio_init2055_post(struct b43_wldev *dev)
 424{
 425        struct b43_phy_n *nphy = dev->phy.n;
 426        struct ssb_sprom *sprom = &(dev->sdev->bus->sprom);
 427        struct ssb_boardinfo *binfo = &(dev->sdev->bus->boardinfo);
 428        int i;
 429        u16 val;
 430        bool workaround = false;
 431
 432        if (sprom->revision < 4)
 433                workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM &&
 434                                binfo->type == 0x46D &&
 435                                binfo->rev >= 0x41);
 436        else
 437                workaround =
 438                        !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 439
 440        b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 441        if (workaround) {
 442                b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 443                b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 444        }
 445        b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 446        b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 447        b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 448        b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 449        b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 450        msleep(1);
 451        b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 452        for (i = 0; i < 200; i++) {
 453                val = b43_radio_read(dev, B2055_CAL_COUT2);
 454                if (val & 0x80) {
 455                        i = 0;
 456                        break;
 457                }
 458                udelay(10);
 459        }
 460        if (i)
 461                b43err(dev->wl, "radio post init timeout\n");
 462        b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 463        b43_switch_channel(dev, dev->phy.channel);
 464        b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 465        b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 466        b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 467        b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 468        b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 469        b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 470        if (!nphy->gain_boost) {
 471                b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 472                b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 473        } else {
 474                b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 475                b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 476        }
 477        udelay(2);
 478}
 479
 480/*
 481 * Initialize a Broadcom 2055 N-radio
 482 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 483 */
 484static void b43_radio_init2055(struct b43_wldev *dev)
 485{
 486        b43_radio_init2055_pre(dev);
 487        if (b43_status(dev) < B43_STAT_INITIALIZED) {
 488                /* Follow wl, not specs. Do not force uploading all regs */
 489                b2055_upload_inittab(dev, 0, 0);
 490        } else {
 491                bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 492                b2055_upload_inittab(dev, ghz5, 0);
 493        }
 494        b43_radio_init2055_post(dev);
 495}
 496
 497static void b43_radio_init2056_pre(struct b43_wldev *dev)
 498{
 499        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 500                     ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 501        /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 502        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 503                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 504        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 505                    ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 506        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 507                    B43_NPHY_RFCTL_CMD_CHIP0PU);
 508}
 509
 510static void b43_radio_init2056_post(struct b43_wldev *dev)
 511{
 512        b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 513        b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 514        b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 515        msleep(1);
 516        b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 517        b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 518        b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 519        /*
 520        if (nphy->init_por)
 521                Call Radio 2056 Recalibrate
 522        */
 523}
 524
 525/*
 526 * Initialize a Broadcom 2056 N-radio
 527 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 528 */
 529static void b43_radio_init2056(struct b43_wldev *dev)
 530{
 531        b43_radio_init2056_pre(dev);
 532        b2056_upload_inittabs(dev, 0, 0);
 533        b43_radio_init2056_post(dev);
 534}
 535
 536/*
 537 * Upload the N-PHY tables.
 538 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 539 */
 540static void b43_nphy_tables_init(struct b43_wldev *dev)
 541{
 542        if (dev->phy.rev < 3)
 543                b43_nphy_rev0_1_2_tables_init(dev);
 544        else
 545                b43_nphy_rev3plus_tables_init(dev);
 546}
 547
 548/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 549static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 550{
 551        struct b43_phy_n *nphy = dev->phy.n;
 552        enum ieee80211_band band;
 553        u16 tmp;
 554
 555        if (!enable) {
 556                nphy->rfctrl_intc1_save = b43_phy_read(dev,
 557                                                       B43_NPHY_RFCTL_INTC1);
 558                nphy->rfctrl_intc2_save = b43_phy_read(dev,
 559                                                       B43_NPHY_RFCTL_INTC2);
 560                band = b43_current_band(dev->wl);
 561                if (dev->phy.rev >= 3) {
 562                        if (band == IEEE80211_BAND_5GHZ)
 563                                tmp = 0x600;
 564                        else
 565                                tmp = 0x480;
 566                } else {
 567                        if (band == IEEE80211_BAND_5GHZ)
 568                                tmp = 0x180;
 569                        else
 570                                tmp = 0x120;
 571                }
 572                b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 573                b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 574        } else {
 575                b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 576                                nphy->rfctrl_intc1_save);
 577                b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 578                                nphy->rfctrl_intc2_save);
 579        }
 580}
 581
 582/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 583static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 584{
 585        struct b43_phy_n *nphy = dev->phy.n;
 586        u16 tmp;
 587        enum ieee80211_band band = b43_current_band(dev->wl);
 588        bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 589                        (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 590
 591        if (dev->phy.rev >= 3) {
 592                if (ipa) {
 593                        tmp = 4;
 594                        b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 595                              (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 596                }
 597
 598                tmp = 1;
 599                b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 600                              (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 601        }
 602}
 603
 604/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 605static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 606{
 607        u32 tmslow;
 608
 609        if (dev->phy.type != B43_PHYTYPE_N)
 610                return;
 611
 612        tmslow = ssb_read32(dev->sdev, SSB_TMSLOW);
 613        if (force)
 614                tmslow |= SSB_TMSLOW_FGC;
 615        else
 616                tmslow &= ~SSB_TMSLOW_FGC;
 617        ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
 618}
 619
 620/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 621static void b43_nphy_reset_cca(struct b43_wldev *dev)
 622{
 623        u16 bbcfg;
 624
 625        b43_nphy_bmac_clock_fgc(dev, 1);
 626        bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 627        b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 628        udelay(1);
 629        b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 630        b43_nphy_bmac_clock_fgc(dev, 0);
 631        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 632}
 633
 634/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 635static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 636{
 637        u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 638
 639        mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 640        if (preamble == 1)
 641                mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 642        else
 643                mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 644
 645        b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 646}
 647
 648/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 649static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 650{
 651        struct b43_phy_n *nphy = dev->phy.n;
 652
 653        bool override = false;
 654        u16 chain = 0x33;
 655
 656        if (nphy->txrx_chain == 0) {
 657                chain = 0x11;
 658                override = true;
 659        } else if (nphy->txrx_chain == 1) {
 660                chain = 0x22;
 661                override = true;
 662        }
 663
 664        b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 665                        ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 666                        chain);
 667
 668        if (override)
 669                b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 670                                B43_NPHY_RFSEQMODE_CAOVER);
 671        else
 672                b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 673                                ~B43_NPHY_RFSEQMODE_CAOVER);
 674}
 675
 676/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 677static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 678                                u16 samps, u8 time, bool wait)
 679{
 680        int i;
 681        u16 tmp;
 682
 683        b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 684        b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 685        if (wait)
 686                b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 687        else
 688                b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 689
 690        b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 691
 692        for (i = 1000; i; i--) {
 693                tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 694                if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 695                        est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 696                                        b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 697                        est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 698                                        b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 699                        est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 700                                        b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 701
 702                        est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 703                                        b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 704                        est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 705                                        b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 706                        est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 707                                        b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 708                        return;
 709                }
 710                udelay(10);
 711        }
 712        memset(est, 0, sizeof(*est));
 713}
 714
 715/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 716static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 717                                        struct b43_phy_n_iq_comp *pcomp)
 718{
 719        if (write) {
 720                b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 721                b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 722                b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 723                b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 724        } else {
 725                pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 726                pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 727                pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 728                pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 729        }
 730}
 731
 732#if 0
 733/* Ready but not used anywhere */
 734/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 735static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 736{
 737        u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 738
 739        b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 740        if (core == 0) {
 741                b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 742                b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 743        } else {
 744                b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 745                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 746        }
 747        b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 748        b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 749        b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 750        b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 751        b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 752        b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 753        b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 754        b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 755}
 756
 757/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 758static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 759{
 760        u8 rxval, txval;
 761        u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 762
 763        regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 764        if (core == 0) {
 765                regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 766                regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 767        } else {
 768                regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 769                regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 770        }
 771        regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 772        regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 773        regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 774        regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 775        regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 776        regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 777        regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 778        regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 779
 780        b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 781        b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 782
 783        b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 784                        ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 785                        ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 786        b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 787                        ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 788        b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 789                        (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 790        b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 791                        (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 792
 793        if (core == 0) {
 794                b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 795                b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 796        } else {
 797                b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 798                b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 799        }
 800
 801        b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 802        b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 803        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 804
 805        if (core == 0) {
 806                rxval = 1;
 807                txval = 8;
 808        } else {
 809                rxval = 4;
 810                txval = 2;
 811        }
 812        b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 813        b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 814}
 815#endif
 816
 817/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 818static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 819{
 820        int i;
 821        s32 iq;
 822        u32 ii;
 823        u32 qq;
 824        int iq_nbits, qq_nbits;
 825        int arsh, brsh;
 826        u16 tmp, a, b;
 827
 828        struct nphy_iq_est est;
 829        struct b43_phy_n_iq_comp old;
 830        struct b43_phy_n_iq_comp new = { };
 831        bool error = false;
 832
 833        if (mask == 0)
 834                return;
 835
 836        b43_nphy_rx_iq_coeffs(dev, false, &old);
 837        b43_nphy_rx_iq_coeffs(dev, true, &new);
 838        b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 839        new = old;
 840
 841        for (i = 0; i < 2; i++) {
 842                if (i == 0 && (mask & 1)) {
 843                        iq = est.iq0_prod;
 844                        ii = est.i0_pwr;
 845                        qq = est.q0_pwr;
 846                } else if (i == 1 && (mask & 2)) {
 847                        iq = est.iq1_prod;
 848                        ii = est.i1_pwr;
 849                        qq = est.q1_pwr;
 850                } else {
 851                        continue;
 852                }
 853
 854                if (ii + qq < 2) {
 855                        error = true;
 856                        break;
 857                }
 858
 859                iq_nbits = fls(abs(iq));
 860                qq_nbits = fls(qq);
 861
 862                arsh = iq_nbits - 20;
 863                if (arsh >= 0) {
 864                        a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 865                        tmp = ii >> arsh;
 866                } else {
 867                        a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 868                        tmp = ii << -arsh;
 869                }
 870                if (tmp == 0) {
 871                        error = true;
 872                        break;
 873                }
 874                a /= tmp;
 875
 876                brsh = qq_nbits - 11;
 877                if (brsh >= 0) {
 878                        b = (qq << (31 - qq_nbits));
 879                        tmp = ii >> brsh;
 880                } else {
 881                        b = (qq << (31 - qq_nbits));
 882                        tmp = ii << -brsh;
 883                }
 884                if (tmp == 0) {
 885                        error = true;
 886                        break;
 887                }
 888                b = int_sqrt(b / tmp - a * a) - (1 << 10);
 889
 890                if (i == 0 && (mask & 0x1)) {
 891                        if (dev->phy.rev >= 3) {
 892                                new.a0 = a & 0x3FF;
 893                                new.b0 = b & 0x3FF;
 894                        } else {
 895                                new.a0 = b & 0x3FF;
 896                                new.b0 = a & 0x3FF;
 897                        }
 898                } else if (i == 1 && (mask & 0x2)) {
 899                        if (dev->phy.rev >= 3) {
 900                                new.a1 = a & 0x3FF;
 901                                new.b1 = b & 0x3FF;
 902                        } else {
 903                                new.a1 = b & 0x3FF;
 904                                new.b1 = a & 0x3FF;
 905                        }
 906                }
 907        }
 908
 909        if (error)
 910                new = old;
 911
 912        b43_nphy_rx_iq_coeffs(dev, true, &new);
 913}
 914
 915/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 916static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 917{
 918        u16 array[4];
 919        int i;
 920
 921        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 922        for (i = 0; i < 4; i++)
 923                array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 924
 925        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 926        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 927        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 928        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 929}
 930
 931/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 932static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 933                                          const u16 *clip_st)
 934{
 935        b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 936        b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 937}
 938
 939/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 940static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 941{
 942        clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 943        clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 944}
 945
 946/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 947static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 948{
 949        if (dev->phy.rev >= 3) {
 950                if (!init)
 951                        return;
 952                if (0 /* FIXME */) {
 953                        b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 954                        b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 955                        b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 956                        b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 957                }
 958        } else {
 959                b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 960                b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 961
 962                ssb_chipco_gpio_control(&dev->sdev->bus->chipco, 0xFC00,
 963                                        0xFC00);
 964                b43_write32(dev, B43_MMIO_MACCTL,
 965                        b43_read32(dev, B43_MMIO_MACCTL) &
 966                        ~B43_MACCTL_GPOUTSMSK);
 967                b43_write16(dev, B43_MMIO_GPIO_MASK,
 968                        b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 969                b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 970                        b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 971
 972                if (init) {
 973                        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 974                        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 975                        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 976                        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 977                }
 978        }
 979}
 980
 981/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 982static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 983{
 984        u16 tmp;
 985
 986        if (dev->sdev->id.revision == 16)
 987                b43_mac_suspend(dev);
 988
 989        tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 990        tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 991                B43_NPHY_CLASSCTL_WAITEDEN);
 992        tmp &= ~mask;
 993        tmp |= (val & mask);
 994        b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 995
 996        if (dev->sdev->id.revision == 16)
 997                b43_mac_enable(dev);
 998
 999        return tmp;
1000}
1001
1002/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1003static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1004{
1005        struct b43_phy *phy = &dev->phy;
1006        struct b43_phy_n *nphy = phy->n;
1007
1008        if (enable) {
1009                static const u16 clip[] = { 0xFFFF, 0xFFFF };
1010                if (nphy->deaf_count++ == 0) {
1011                        nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1012                        b43_nphy_classifier(dev, 0x7, 0);
1013                        b43_nphy_read_clip_detection(dev, nphy->clip_state);
1014                        b43_nphy_write_clip_detection(dev, clip);
1015                }
1016                b43_nphy_reset_cca(dev);
1017        } else {
1018                if (--nphy->deaf_count == 0) {
1019                        b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1020                        b43_nphy_write_clip_detection(dev, nphy->clip_state);
1021                }
1022        }
1023}
1024
1025/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1026static void b43_nphy_stop_playback(struct b43_wldev *dev)
1027{
1028        struct b43_phy_n *nphy = dev->phy.n;
1029        u16 tmp;
1030
1031        if (nphy->hang_avoid)
1032                b43_nphy_stay_in_carrier_search(dev, 1);
1033
1034        tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1035        if (tmp & 0x1)
1036                b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1037        else if (tmp & 0x2)
1038                b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1039
1040        b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1041
1042        if (nphy->bb_mult_save & 0x80000000) {
1043                tmp = nphy->bb_mult_save & 0xFFFF;
1044                b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1045                nphy->bb_mult_save = 0;
1046        }
1047
1048        if (nphy->hang_avoid)
1049                b43_nphy_stay_in_carrier_search(dev, 0);
1050}
1051
1052/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1053static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1054{
1055        struct b43_phy_n *nphy = dev->phy.n;
1056
1057        u8 channel = dev->phy.channel;
1058        int tone[2] = { 57, 58 };
1059        u32 noise[2] = { 0x3FF, 0x3FF };
1060
1061        B43_WARN_ON(dev->phy.rev < 3);
1062
1063        if (nphy->hang_avoid)
1064                b43_nphy_stay_in_carrier_search(dev, 1);
1065
1066        if (nphy->gband_spurwar_en) {
1067                /* TODO: N PHY Adjust Analog Pfbw (7) */
1068                if (channel == 11 && dev->phy.is_40mhz)
1069                        ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1070                else
1071                        ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1072                /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1073        }
1074
1075        if (nphy->aband_spurwar_en) {
1076                if (channel == 54) {
1077                        tone[0] = 0x20;
1078                        noise[0] = 0x25F;
1079                } else if (channel == 38 || channel == 102 || channel == 118) {
1080                        if (0 /* FIXME */) {
1081                                tone[0] = 0x20;
1082                                noise[0] = 0x21F;
1083                        } else {
1084                                tone[0] = 0;
1085                                noise[0] = 0;
1086                        }
1087                } else if (channel == 134) {
1088                        tone[0] = 0x20;
1089                        noise[0] = 0x21F;
1090                } else if (channel == 151) {
1091                        tone[0] = 0x10;
1092                        noise[0] = 0x23F;
1093                } else if (channel == 153 || channel == 161) {
1094                        tone[0] = 0x30;
1095                        noise[0] = 0x23F;
1096                } else {
1097                        tone[0] = 0;
1098                        noise[0] = 0;
1099                }
1100
1101                if (!tone[0] && !noise[0])
1102                        ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1103                else
1104                        ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1105        }
1106
1107        if (nphy->hang_avoid)
1108                b43_nphy_stay_in_carrier_search(dev, 0);
1109}
1110
1111/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1112static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1113{
1114        struct b43_phy_n *nphy = dev->phy.n;
1115
1116        u8 i;
1117        s16 tmp;
1118        u16 data[4];
1119        s16 gain[2];
1120        u16 minmax[2];
1121        static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1122
1123        if (nphy->hang_avoid)
1124                b43_nphy_stay_in_carrier_search(dev, 1);
1125
1126        if (nphy->gain_boost) {
1127                if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1128                        gain[0] = 6;
1129                        gain[1] = 6;
1130                } else {
1131                        tmp = 40370 - 315 * dev->phy.channel;
1132                        gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1133                        tmp = 23242 - 224 * dev->phy.channel;
1134                        gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1135                }
1136        } else {
1137                gain[0] = 0;
1138                gain[1] = 0;
1139        }
1140
1141        for (i = 0; i < 2; i++) {
1142                if (nphy->elna_gain_config) {
1143                        data[0] = 19 + gain[i];
1144                        data[1] = 25 + gain[i];
1145                        data[2] = 25 + gain[i];
1146                        data[3] = 25 + gain[i];
1147                } else {
1148                        data[0] = lna_gain[0] + gain[i];
1149                        data[1] = lna_gain[1] + gain[i];
1150                        data[2] = lna_gain[2] + gain[i];
1151                        data[3] = lna_gain[3] + gain[i];
1152                }
1153                b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1154
1155                minmax[i] = 23 + gain[i];
1156        }
1157
1158        b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1159                                minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1160        b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1161                                minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1162
1163        if (nphy->hang_avoid)
1164                b43_nphy_stay_in_carrier_search(dev, 0);
1165}
1166
1167/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1168static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1169{
1170        struct b43_phy_n *nphy = dev->phy.n;
1171        struct ssb_sprom *sprom = &(dev->sdev->bus->sprom);
1172
1173        /* PHY rev 0, 1, 2 */
1174        u8 i, j;
1175        u8 code;
1176        u16 tmp;
1177        u8 rfseq_events[3] = { 6, 8, 7 };
1178        u8 rfseq_delays[3] = { 10, 30, 1 };
1179
1180        /* PHY rev >= 3 */
1181        bool ghz5;
1182        bool ext_lna;
1183        u16 rssi_gain;
1184        struct nphy_gain_ctl_workaround_entry *e;
1185        u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1186        u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1187
1188        if (dev->phy.rev >= 3) {
1189                /* Prepare values */
1190                ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1191                        & B43_NPHY_BANDCTL_5GHZ;
1192                ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1193                e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1194                if (ghz5 && dev->phy.rev >= 5)
1195                        rssi_gain = 0x90;
1196                else
1197                        rssi_gain = 0x50;
1198
1199                b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1200
1201                /* Set Clip 2 detect */
1202                b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1203                                B43_NPHY_C1_CGAINI_CL2DETECT);
1204                b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1205                                B43_NPHY_C2_CGAINI_CL2DETECT);
1206
1207                b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1208                                0x17);
1209                b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1210                                0x17);
1211                b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1212                b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1213                b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1214                b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1215                b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1216                                rssi_gain);
1217                b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1218                                rssi_gain);
1219                b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1220                                0x17);
1221                b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1222                                0x17);
1223                b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1224                b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1225
1226                b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1227                b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1228                b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1229                b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1230                b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1231                b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1232                b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1233                b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1234                b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1235                b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1236                b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1237                b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1238
1239                b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1240                b43_phy_write(dev, 0x2A7, e->init_gain);
1241                b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1242                                        e->rfseq_init);
1243                b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1244
1245                /* TODO: check defines. Do not match variables names */
1246                b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1247                b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1248                b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1249                b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1250                b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1251                b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1252
1253                b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1254                b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1255                b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1256                b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1257                b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1258                b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1259                                ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1260                b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1261                                ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1262                b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1263        } else {
1264                /* Set Clip 2 detect */
1265                b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1266                                B43_NPHY_C1_CGAINI_CL2DETECT);
1267                b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1268                                B43_NPHY_C2_CGAINI_CL2DETECT);
1269
1270                /* Set narrowband clip threshold */
1271                b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1272                b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1273
1274                if (!dev->phy.is_40mhz) {
1275                        /* Set dwell lengths */
1276                        b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1277                        b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1278                        b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1279                        b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1280                }
1281
1282                /* Set wideband clip 2 threshold */
1283                b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1284                                ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1285                                21);
1286                b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1287                                ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1288                                21);
1289
1290                if (!dev->phy.is_40mhz) {
1291                        b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1292                                ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1293                        b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1294                                ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1295                        b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1296                                ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1297                        b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1298                                ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1299                }
1300
1301                b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1302
1303                if (nphy->gain_boost) {
1304                        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1305                            dev->phy.is_40mhz)
1306                                code = 4;
1307                        else
1308                                code = 5;
1309                } else {
1310                        code = dev->phy.is_40mhz ? 6 : 7;
1311                }
1312
1313                /* Set HPVGA2 index */
1314                b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1315                                ~B43_NPHY_C1_INITGAIN_HPVGA2,
1316                                code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1317                b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1318                                ~B43_NPHY_C2_INITGAIN_HPVGA2,
1319                                code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1320
1321                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1322                /* specs say about 2 loops, but wl does 4 */
1323                for (i = 0; i < 4; i++)
1324                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1325                                                        (code << 8 | 0x7C));
1326
1327                b43_nphy_adjust_lna_gain_table(dev);
1328
1329                if (nphy->elna_gain_config) {
1330                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1331                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1332                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1333                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1334                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1335
1336                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1337                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1338                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1339                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1340                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1341
1342                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1343                        /* specs say about 2 loops, but wl does 4 */
1344                        for (i = 0; i < 4; i++)
1345                                b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1346                                                        (code << 8 | 0x74));
1347                }
1348
1349                if (dev->phy.rev == 2) {
1350                        for (i = 0; i < 4; i++) {
1351                                b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1352                                                (0x0400 * i) + 0x0020);
1353                                for (j = 0; j < 21; j++) {
1354                                        tmp = j * (i < 2 ? 3 : 1);
1355                                        b43_phy_write(dev,
1356                                                B43_NPHY_TABLE_DATALO, tmp);
1357                                }
1358                        }
1359                }
1360
1361                b43_nphy_set_rf_sequence(dev, 5,
1362                                rfseq_events, rfseq_delays, 3);
1363                b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1364                        ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1365                        0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1366
1367                if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1368                        b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1369                                        0xFF80, 4);
1370        }
1371}
1372
1373/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1374static void b43_nphy_workarounds(struct b43_wldev *dev)
1375{
1376        struct ssb_bus *bus = dev->sdev->bus;
1377        struct b43_phy *phy = &dev->phy;
1378        struct b43_phy_n *nphy = phy->n;
1379
1380        u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1381        u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1382
1383        u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1384        u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1385
1386        u16 tmp16;
1387        u32 tmp32;
1388
1389        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1390                b43_nphy_classifier(dev, 1, 0);
1391        else
1392                b43_nphy_classifier(dev, 1, 1);
1393
1394        if (nphy->hang_avoid)
1395                b43_nphy_stay_in_carrier_search(dev, 1);
1396
1397        b43_phy_set(dev, B43_NPHY_IQFLIP,
1398                    B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1399
1400        if (dev->phy.rev >= 3) {
1401                tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1402                tmp32 &= 0xffffff;
1403                b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1404
1405                b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1406                b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1407                b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1408                b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1409                b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1410                b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1411
1412                b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1413                b43_phy_write(dev, 0x2AE, 0x000C);
1414
1415                /* TODO */
1416
1417                tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1418                        0x2 : 0x9C40;
1419                b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1420
1421                b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1422
1423                b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1424                b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1425
1426                b43_nphy_gain_ctrl_workarounds(dev);
1427
1428                b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1429                b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1430
1431                /* TODO */
1432
1433                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1434                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1435                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1436                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1437                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1438                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1439                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1440                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1441                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1442                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1443
1444                /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1445
1446                if ((bus->sprom.boardflags2_lo & B43_BFL2_APLL_WAR &&
1447                    b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1448                    (bus->sprom.boardflags2_lo & B43_BFL2_GPLL_WAR &&
1449                    b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1450                        tmp32 = 0x00088888;
1451                else
1452                        tmp32 = 0x88888888;
1453                b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1454                b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1455                b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1456
1457                if (dev->phy.rev == 4 &&
1458                    b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1459                        b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1460                                        0x70);
1461                        b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1462                                        0x70);
1463                }
1464
1465                b43_phy_write(dev, 0x224, 0x039C);
1466                b43_phy_write(dev, 0x225, 0x0357);
1467                b43_phy_write(dev, 0x226, 0x0317);
1468                b43_phy_write(dev, 0x227, 0x02D7);
1469                b43_phy_write(dev, 0x228, 0x039C);
1470                b43_phy_write(dev, 0x229, 0x0357);
1471                b43_phy_write(dev, 0x22A, 0x0317);
1472                b43_phy_write(dev, 0x22B, 0x02D7);
1473                b43_phy_write(dev, 0x22C, 0x039C);
1474                b43_phy_write(dev, 0x22D, 0x0357);
1475                b43_phy_write(dev, 0x22E, 0x0317);
1476                b43_phy_write(dev, 0x22F, 0x02D7);
1477        } else {
1478                if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1479                    nphy->band5g_pwrgain) {
1480                        b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1481                        b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1482                } else {
1483                        b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1484                        b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1485                }
1486
1487                b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1488                b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1489                b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1490                b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1491
1492                if (dev->phy.rev < 2) {
1493                        b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1494                        b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1495                        b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1496                        b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1497                        b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1498                        b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1499                }
1500
1501                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1502                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1503                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1504                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1505
1506                if (bus->sprom.boardflags2_lo & 0x100 &&
1507                    bus->boardinfo.type == 0x8B) {
1508                        delays1[0] = 0x1;
1509                        delays1[5] = 0x14;
1510                }
1511                b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1512                b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1513
1514                b43_nphy_gain_ctrl_workarounds(dev);
1515
1516                if (dev->phy.rev < 2) {
1517                        if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1518                                b43_hf_write(dev, b43_hf_read(dev) |
1519                                                B43_HF_MLADVW);
1520                } else if (dev->phy.rev == 2) {
1521                        b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1522                        b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1523                }
1524
1525                if (dev->phy.rev < 2)
1526                        b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1527                                        ~B43_NPHY_SCRAM_SIGCTL_SCM);
1528
1529                /* Set phase track alpha and beta */
1530                b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1531                b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1532                b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1533                b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1534                b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1535                b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1536
1537                b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1538                                ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1539                b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1540                b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1541                b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1542
1543                if (dev->phy.rev == 2)
1544                        b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1545                                        B43_NPHY_FINERX2_CGC_DECGC);
1546        }
1547
1548        if (nphy->hang_avoid)
1549                b43_nphy_stay_in_carrier_search(dev, 0);
1550}
1551
1552/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1553static int b43_nphy_load_samples(struct b43_wldev *dev,
1554                                        struct b43_c32 *samples, u16 len) {
1555        struct b43_phy_n *nphy = dev->phy.n;
1556        u16 i;
1557        u32 *data;
1558
1559        data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1560        if (!data) {
1561                b43err(dev->wl, "allocation for samples loading failed\n");
1562                return -ENOMEM;
1563        }
1564        if (nphy->hang_avoid)
1565                b43_nphy_stay_in_carrier_search(dev, 1);
1566
1567        for (i = 0; i < len; i++) {
1568                data[i] = (samples[i].i & 0x3FF << 10);
1569                data[i] |= samples[i].q & 0x3FF;
1570        }
1571        b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1572
1573        kfree(data);
1574        if (nphy->hang_avoid)
1575                b43_nphy_stay_in_carrier_search(dev, 0);
1576        return 0;
1577}
1578
1579/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1580static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1581                                        bool test)
1582{
1583        int i;
1584        u16 bw, len, rot, angle;
1585        struct b43_c32 *samples;
1586
1587
1588        bw = (dev->phy.is_40mhz) ? 40 : 20;
1589        len = bw << 3;
1590
1591        if (test) {
1592                if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1593                        bw = 82;
1594                else
1595                        bw = 80;
1596
1597                if (dev->phy.is_40mhz)
1598                        bw <<= 1;
1599
1600                len = bw << 1;
1601        }
1602
1603        samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1604        if (!samples) {
1605                b43err(dev->wl, "allocation for samples generation failed\n");
1606                return 0;
1607        }
1608        rot = (((freq * 36) / bw) << 16) / 100;
1609        angle = 0;
1610
1611        for (i = 0; i < len; i++) {
1612                samples[i] = b43_cordic(angle);
1613                angle += rot;
1614                samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1615                samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1616        }
1617
1618        i = b43_nphy_load_samples(dev, samples, len);
1619        kfree(samples);
1620        return (i < 0) ? 0 : len;
1621}
1622
1623/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1624static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1625                                        u16 wait, bool iqmode, bool dac_test)
1626{
1627        struct b43_phy_n *nphy = dev->phy.n;
1628        int i;
1629        u16 seq_mode;
1630        u32 tmp;
1631
1632        if (nphy->hang_avoid)
1633                b43_nphy_stay_in_carrier_search(dev, true);
1634
1635        if ((nphy->bb_mult_save & 0x80000000) == 0) {
1636                tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1637                nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1638        }
1639
1640        if (!dev->phy.is_40mhz)
1641                tmp = 0x6464;
1642        else
1643                tmp = 0x4747;
1644        b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1645
1646        if (nphy->hang_avoid)
1647                b43_nphy_stay_in_carrier_search(dev, false);
1648
1649        b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1650
1651        if (loops != 0xFFFF)
1652                b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1653        else
1654                b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1655
1656        b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1657
1658        seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1659
1660        b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1661        if (iqmode) {
1662                b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1663                b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1664        } else {
1665                if (dac_test)
1666                        b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1667                else
1668                        b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1669        }
1670        for (i = 0; i < 100; i++) {
1671                if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1672                        i = 0;
1673                        break;
1674                }
1675                udelay(10);
1676        }
1677        if (i)
1678                b43err(dev->wl, "run samples timeout\n");
1679
1680        b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1681}
1682
1683/*
1684 * Transmits a known value for LO calibration
1685 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1686 */
1687static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1688                                bool iqmode, bool dac_test)
1689{
1690        u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1691        if (samp == 0)
1692                return -1;
1693        b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1694        return 0;
1695}
1696
1697/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1698static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1699{
1700        struct b43_phy_n *nphy = dev->phy.n;
1701        int i, j;
1702        u32 tmp;
1703        u32 cur_real, cur_imag, real_part, imag_part;
1704
1705        u16 buffer[7];
1706
1707        if (nphy->hang_avoid)
1708                b43_nphy_stay_in_carrier_search(dev, true);
1709
1710        b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1711
1712        for (i = 0; i < 2; i++) {
1713                tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1714                        (buffer[i * 2 + 1] & 0x3FF);
1715                b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1716                                (((i + 26) << 10) | 320));
1717                for (j = 0; j < 128; j++) {
1718                        b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1719                                        ((tmp >> 16) & 0xFFFF));
1720                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1721                                        (tmp & 0xFFFF));
1722                }
1723        }
1724
1725        for (i = 0; i < 2; i++) {
1726                tmp = buffer[5 + i];
1727                real_part = (tmp >> 8) & 0xFF;
1728                imag_part = (tmp & 0xFF);
1729                b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1730                                (((i + 26) << 10) | 448));
1731
1732                if (dev->phy.rev >= 3) {
1733                        cur_real = real_part;
1734                        cur_imag = imag_part;
1735                        tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1736                }
1737
1738                for (j = 0; j < 128; j++) {
1739                        if (dev->phy.rev < 3) {
1740                                cur_real = (real_part * loscale[j] + 128) >> 8;
1741                                cur_imag = (imag_part * loscale[j] + 128) >> 8;
1742                                tmp = ((cur_real & 0xFF) << 8) |
1743                                        (cur_imag & 0xFF);
1744                        }
1745                        b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1746                                        ((tmp >> 16) & 0xFFFF));
1747                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1748                                        (tmp & 0xFFFF));
1749                }
1750        }
1751
1752        if (dev->phy.rev >= 3) {
1753                b43_shm_write16(dev, B43_SHM_SHARED,
1754                                B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1755                b43_shm_write16(dev, B43_SHM_SHARED,
1756                                B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1757        }
1758
1759        if (nphy->hang_avoid)
1760                b43_nphy_stay_in_carrier_search(dev, false);
1761}
1762
1763/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1764static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1765                                        u8 *events, u8 *delays, u8 length)
1766{
1767        struct b43_phy_n *nphy = dev->phy.n;
1768        u8 i;
1769        u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1770        u16 offset1 = cmd << 4;
1771        u16 offset2 = offset1 + 0x80;
1772
1773        if (nphy->hang_avoid)
1774                b43_nphy_stay_in_carrier_search(dev, true);
1775
1776        b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1777        b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1778
1779        for (i = length; i < 16; i++) {
1780                b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1781                b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1782        }
1783
1784        if (nphy->hang_avoid)
1785                b43_nphy_stay_in_carrier_search(dev, false);
1786}
1787
1788/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1789static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1790                                       enum b43_nphy_rf_sequence seq)
1791{
1792        static const u16 trigger[] = {
1793                [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1794                [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1795                [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1796                [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1797                [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1798                [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1799        };
1800        int i;
1801        u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1802
1803        B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1804
1805        b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1806                    B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1807        b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1808        for (i = 0; i < 200; i++) {
1809                if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1810                        goto ok;
1811                msleep(1);
1812        }
1813        b43err(dev->wl, "RF sequence status timeout\n");
1814ok:
1815        b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1816}
1817
1818/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1819static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1820                                                u16 value, u8 core, bool off)
1821{
1822        int i;
1823        u8 index = fls(field);
1824        u8 addr, en_addr, val_addr;
1825        /* we expect only one bit set */
1826        B43_WARN_ON(field & (~(1 << (index - 1))));
1827
1828        if (dev->phy.rev >= 3) {
1829                const struct nphy_rf_control_override_rev3 *rf_ctrl;
1830                for (i = 0; i < 2; i++) {
1831                        if (index == 0 || index == 16) {
1832                                b43err(dev->wl,
1833                                        "Unsupported RF Ctrl Override call\n");
1834                                return;
1835                        }
1836
1837                        rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1838                        en_addr = B43_PHY_N((i == 0) ?
1839                                rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1840                        val_addr = B43_PHY_N((i == 0) ?
1841                                rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1842
1843                        if (off) {
1844                                b43_phy_mask(dev, en_addr, ~(field));
1845                                b43_phy_mask(dev, val_addr,
1846                                                ~(rf_ctrl->val_mask));
1847                        } else {
1848                                if (core == 0 || ((1 << core) & i) != 0) {
1849                                        b43_phy_set(dev, en_addr, field);
1850                                        b43_phy_maskset(dev, val_addr,
1851                                                ~(rf_ctrl->val_mask),
1852                                                (value << rf_ctrl->val_shift));
1853                                }
1854                        }
1855                }
1856        } else {
1857                const struct nphy_rf_control_override_rev2 *rf_ctrl;
1858                if (off) {
1859                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1860                        value = 0;
1861                } else {
1862                        b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1863                }
1864
1865                for (i = 0; i < 2; i++) {
1866                        if (index <= 1 || index == 16) {
1867                                b43err(dev->wl,
1868                                        "Unsupported RF Ctrl Override call\n");
1869                                return;
1870                        }
1871
1872                        if (index == 2 || index == 10 ||
1873                            (index >= 13 && index <= 15)) {
1874                                core = 1;
1875                        }
1876
1877                        rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1878                        addr = B43_PHY_N((i == 0) ?
1879                                rf_ctrl->addr0 : rf_ctrl->addr1);
1880
1881                        if ((core & (1 << i)) != 0)
1882                                b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1883                                                (value << rf_ctrl->shift));
1884
1885                        b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1886                        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1887                                        B43_NPHY_RFCTL_CMD_START);
1888                        udelay(1);
1889                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1890                }
1891        }
1892}
1893
1894/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1895static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1896                                                u16 value, u8 core)
1897{
1898        u8 i, j;
1899        u16 reg, tmp, val;
1900
1901        B43_WARN_ON(dev->phy.rev < 3);
1902        B43_WARN_ON(field > 4);
1903
1904        for (i = 0; i < 2; i++) {
1905                if ((core == 1 && i == 1) || (core == 2 && !i))
1906                        continue;
1907
1908                reg = (i == 0) ?
1909                        B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1910                b43_phy_mask(dev, reg, 0xFBFF);
1911
1912                switch (field) {
1913                case 0:
1914                        b43_phy_write(dev, reg, 0);
1915                        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1916                        break;
1917                case 1:
1918                        if (!i) {
1919                                b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1920                                                0xFC3F, (value << 6));
1921                                b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1922                                                0xFFFE, 1);
1923                                b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1924                                                B43_NPHY_RFCTL_CMD_START);
1925                                for (j = 0; j < 100; j++) {
1926                                        if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1927                                                j = 0;
1928                                                break;
1929                                        }
1930                                        udelay(10);
1931                                }
1932                                if (j)
1933                                        b43err(dev->wl,
1934                                                "intc override timeout\n");
1935                                b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1936                                                0xFFFE);
1937                        } else {
1938                                b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1939                                                0xFC3F, (value << 6));
1940                                b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1941                                                0xFFFE, 1);
1942                                b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1943                                                B43_NPHY_RFCTL_CMD_RXTX);
1944                                for (j = 0; j < 100; j++) {
1945                                        if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1946                                                j = 0;
1947                                                break;
1948                                        }
1949                                        udelay(10);
1950                                }
1951                                if (j)
1952                                        b43err(dev->wl,
1953                                                "intc override timeout\n");
1954                                b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1955                                                0xFFFE);
1956                        }
1957                        break;
1958                case 2:
1959                        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1960                                tmp = 0x0020;
1961                                val = value << 5;
1962                        } else {
1963                                tmp = 0x0010;
1964                                val = value << 4;
1965                        }
1966                        b43_phy_maskset(dev, reg, ~tmp, val);
1967                        break;
1968                case 3:
1969                        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1970                                tmp = 0x0001;
1971                                val = value;
1972                        } else {
1973                                tmp = 0x0004;
1974                                val = value << 2;
1975                        }
1976                        b43_phy_maskset(dev, reg, ~tmp, val);
1977                        break;
1978                case 4:
1979                        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1980                                tmp = 0x0002;
1981                                val = value << 1;
1982                        } else {
1983                                tmp = 0x0008;
1984                                val = value << 3;
1985                        }
1986                        b43_phy_maskset(dev, reg, ~tmp, val);
1987                        break;
1988                }
1989        }
1990}
1991
1992/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
1993static void b43_nphy_bphy_init(struct b43_wldev *dev)
1994{
1995        unsigned int i;
1996        u16 val;
1997
1998        val = 0x1E1F;
1999        for (i = 0; i < 16; i++) {
2000                b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2001                val -= 0x202;
2002        }
2003        val = 0x3E3F;
2004        for (i = 0; i < 16; i++) {
2005                b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2006                val -= 0x202;
2007        }
2008        b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2009}
2010
2011/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2012static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2013                                        s8 offset, u8 core, u8 rail,
2014                                        enum b43_nphy_rssi_type type)
2015{
2016        u16 tmp;
2017        bool core1or5 = (core == 1) || (core == 5);
2018        bool core2or5 = (core == 2) || (core == 5);
2019
2020        offset = clamp_val(offset, -32, 31);
2021        tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2022
2023        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2024                b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2025        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2026                b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2027        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2028                b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2029        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2030                b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2031
2032        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2033                b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2034        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2035                b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2036        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2037                b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2038        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2039                b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2040
2041        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2042                b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2043        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2044                b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2045        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2046                b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2047        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2048                b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2049
2050        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2051                b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2052        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2053                b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2054        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2055                b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2056        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2057                b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2058
2059        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2060                b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2061        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2062                b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2063        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2064                b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2065        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2066                b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2067
2068        if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2069                b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2070        if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2071                b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2072
2073        if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2074                b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2075        if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2076                b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2077}
2078
2079static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2080{
2081        u16 val;
2082
2083        if (type < 3)
2084                val = 0;
2085        else if (type == 6)
2086                val = 1;
2087        else if (type == 3)
2088                val = 2;
2089        else
2090                val = 3;
2091
2092        val = (val << 12) | (val << 14);
2093        b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2094        b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2095
2096        if (type < 3) {
2097                b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2098                                (type + 1) << 4);
2099                b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2100                                (type + 1) << 4);
2101        }
2102
2103        if (code == 0) {
2104                b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2105                if (type < 3) {
2106                        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2107                                ~(B43_NPHY_RFCTL_CMD_RXEN |
2108                                  B43_NPHY_RFCTL_CMD_CORESEL));
2109                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2110                                ~(0x1 << 12 |
2111                                  0x1 << 5 |
2112                                  0x1 << 1 |
2113                                  0x1));
2114                        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2115                                ~B43_NPHY_RFCTL_CMD_START);
2116                        udelay(20);
2117                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2118                }
2119        } else {
2120                b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2121                if (type < 3) {
2122                        b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2123                                ~(B43_NPHY_RFCTL_CMD_RXEN |
2124                                  B43_NPHY_RFCTL_CMD_CORESEL),
2125                                (B43_NPHY_RFCTL_CMD_RXEN |
2126                                 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2127                        b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2128                                (0x1 << 12 |
2129                                  0x1 << 5 |
2130                                  0x1 << 1 |
2131                                  0x1));
2132                        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2133                                B43_NPHY_RFCTL_CMD_START);
2134                        udelay(20);
2135                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2136                }
2137        }
2138}
2139
2140static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2141{
2142        struct b43_phy_n *nphy = dev->phy.n;
2143        u8 i;
2144        u16 reg, val;
2145
2146        if (code == 0) {
2147                b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2148                b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2149                b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2150                b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2151                b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2152                b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2153                b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2154                b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2155        } else {
2156                for (i = 0; i < 2; i++) {
2157                        if ((code == 1 && i == 1) || (code == 2 && !i))
2158                                continue;
2159
2160                        reg = (i == 0) ?
2161                                B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2162                        b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2163
2164                        if (type < 3) {
2165                                reg = (i == 0) ?
2166                                        B43_NPHY_AFECTL_C1 :
2167                                        B43_NPHY_AFECTL_C2;
2168                                b43_phy_maskset(dev, reg, 0xFCFF, 0);
2169
2170                                reg = (i == 0) ?
2171                                        B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2172                                        B43_NPHY_RFCTL_LUT_TRSW_UP2;
2173                                b43_phy_maskset(dev, reg, 0xFFC3, 0);
2174
2175                                if (type == 0)
2176                                        val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2177                                else if (type == 1)
2178                                        val = 16;
2179                                else
2180                                        val = 32;
2181                                b43_phy_set(dev, reg, val);
2182
2183                                reg = (i == 0) ?
2184                                        B43_NPHY_TXF_40CO_B1S0 :
2185                                        B43_NPHY_TXF_40CO_B32S1;
2186                                b43_phy_set(dev, reg, 0x0020);
2187                        } else {
2188                                if (type == 6)
2189                                        val = 0x0100;
2190                                else if (type == 3)
2191                                        val = 0x0200;
2192                                else
2193                                        val = 0x0300;
2194
2195                                reg = (i == 0) ?
2196                                        B43_NPHY_AFECTL_C1 :
2197                                        B43_NPHY_AFECTL_C2;
2198
2199                                b43_phy_maskset(dev, reg, 0xFCFF, val);
2200                                b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2201
2202                                if (type != 3 && type != 6) {
2203                                        enum ieee80211_band band =
2204                                                b43_current_band(dev->wl);
2205
2206                                        if ((nphy->ipa2g_on &&
2207                                                band == IEEE80211_BAND_2GHZ) ||
2208                                                (nphy->ipa5g_on &&
2209                                                band == IEEE80211_BAND_5GHZ))
2210                                                val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2211                                        else
2212                                                val = 0x11;
2213                                        reg = (i == 0) ? 0x2000 : 0x3000;
2214                                        reg |= B2055_PADDRV;
2215                                        b43_radio_write16(dev, reg, val);
2216
2217                                        reg = (i == 0) ?
2218                                                B43_NPHY_AFECTL_OVER1 :
2219                                                B43_NPHY_AFECTL_OVER;
2220                                        b43_phy_set(dev, reg, 0x0200);
2221                                }
2222                        }
2223                }
2224        }
2225}
2226
2227/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2228static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2229{
2230        if (dev->phy.rev >= 3)
2231                b43_nphy_rev3_rssi_select(dev, code, type);
2232        else
2233                b43_nphy_rev2_rssi_select(dev, code, type);
2234}
2235
2236/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2237static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2238{
2239        int i;
2240        for (i = 0; i < 2; i++) {
2241                if (type == 2) {
2242                        if (i == 0) {
2243                                b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2244                                                  0xFC, buf[0]);
2245                                b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2246                                                  0xFC, buf[1]);
2247                        } else {
2248                                b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2249                                                  0xFC, buf[2 * i]);
2250                                b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2251                                                  0xFC, buf[2 * i + 1]);
2252                        }
2253                } else {
2254                        if (i == 0)
2255                                b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2256                                                  0xF3, buf[0] << 2);
2257                        else
2258                                b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2259                                                  0xF3, buf[2 * i + 1] << 2);
2260                }
2261        }
2262}
2263
2264/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2265static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2266                                u8 nsamp)
2267{
2268        int i;
2269        int out;
2270        u16 save_regs_phy[9];
2271        u16 s[2];
2272
2273        if (dev->phy.rev >= 3) {
2274                save_regs_phy[0] = b43_phy_read(dev,
2275                                                B43_NPHY_RFCTL_LUT_TRSW_UP1);
2276                save_regs_phy[1] = b43_phy_read(dev,
2277                                                B43_NPHY_RFCTL_LUT_TRSW_UP2);
2278                save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2279                save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2280                save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2281                save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2282                save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2283                save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2284                save_regs_phy[8] = 0;
2285        } else {
2286                save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2287                save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2288                save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2289                save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2290                save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2291                save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2292                save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2293                save_regs_phy[7] = 0;
2294                save_regs_phy[8] = 0;
2295        }
2296
2297        b43_nphy_rssi_select(dev, 5, type);
2298
2299        if (dev->phy.rev < 2) {
2300                save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2301                b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2302        }
2303
2304        for (i = 0; i < 4; i++)
2305                buf[i] = 0;
2306
2307        for (i = 0; i < nsamp; i++) {
2308                if (dev->phy.rev < 2) {
2309                        s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2310                        s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2311                } else {
2312                        s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2313                        s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2314                }
2315
2316                buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2317                buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2318                buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2319                buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2320        }
2321        out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2322                (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2323
2324        if (dev->phy.rev < 2)
2325                b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2326
2327        if (dev->phy.rev >= 3) {
2328                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2329                                save_regs_phy[0]);
2330                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2331                                save_regs_phy[1]);
2332                b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2333                b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2334                b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2335                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2336                b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2337                b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2338        } else {
2339                b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2340                b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2341                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2342                b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2343                b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2344                b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2345                b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2346        }
2347
2348        return out;
2349}
2350
2351/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2352static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2353{
2354        int i, j;
2355        u8 state[4];
2356        u8 code, val;
2357        u16 class, override;
2358        u8 regs_save_radio[2];
2359        u16 regs_save_phy[2];
2360
2361        s8 offset[4];
2362        u8 core;
2363        u8 rail;
2364
2365        u16 clip_state[2];
2366        u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2367        s32 results_min[4] = { };
2368        u8 vcm_final[4] = { };
2369        s32 results[4][4] = { };
2370        s32 miniq[4][2] = { };
2371
2372        if (type == 2) {
2373                code = 0;
2374                val = 6;
2375        } else if (type < 2) {
2376                code = 25;
2377                val = 4;
2378        } else {
2379                B43_WARN_ON(1);
2380                return;
2381        }
2382
2383        class = b43_nphy_classifier(dev, 0, 0);
2384        b43_nphy_classifier(dev, 7, 4);
2385        b43_nphy_read_clip_detection(dev, clip_state);
2386        b43_nphy_write_clip_detection(dev, clip_off);
2387
2388        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2389                override = 0x140;
2390        else
2391                override = 0x110;
2392
2393        regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2394        regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2395        b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2396        b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2397
2398        regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2399        regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2400        b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2401        b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2402
2403        state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2404        state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2405        b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2406        b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2407        state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2408        state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2409
2410        b43_nphy_rssi_select(dev, 5, type);
2411        b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2412        b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2413
2414        for (i = 0; i < 4; i++) {
2415                u8 tmp[4];
2416                for (j = 0; j < 4; j++)
2417                        tmp[j] = i;
2418                if (type != 1)
2419                        b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2420                b43_nphy_poll_rssi(dev, type, results[i], 8);
2421                if (type < 2)
2422                        for (j = 0; j < 2; j++)
2423                                miniq[i][j] = min(results[i][2 * j],
2424                                                results[i][2 * j + 1]);
2425        }
2426
2427        for (i = 0; i < 4; i++) {
2428                s32 mind = 40;
2429                u8 minvcm = 0;
2430                s32 minpoll = 249;
2431                s32 curr;
2432                for (j = 0; j < 4; j++) {
2433                        if (type == 2)
2434                                curr = abs(results[j][i]);
2435                        else
2436                                curr = abs(miniq[j][i / 2] - code * 8);
2437
2438                        if (curr < mind) {
2439                                mind = curr;
2440                                minvcm = j;
2441                        }
2442
2443                        if (results[j][i] < minpoll)
2444                                minpoll = results[j][i];
2445                }
2446                results_min[i] = minpoll;
2447                vcm_final[i] = minvcm;
2448        }
2449
2450        if (type != 1)
2451                b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2452
2453        for (i = 0; i < 4; i++) {
2454                offset[i] = (code * 8) - results[vcm_final[i]][i];
2455
2456                if (offset[i] < 0)
2457                        offset[i] = -((abs(offset[i]) + 4) / 8);
2458                else
2459                        offset[i] = (offset[i] + 4) / 8;
2460
2461                if (results_min[i] == 248)
2462                        offset[i] = code - 32;
2463
2464                core = (i / 2) ? 2 : 1;
2465                rail = (i % 2) ? 1 : 0;
2466
2467                b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2468                                                type);
2469        }
2470
2471        b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2472        b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2473
2474        switch (state[2]) {
2475        case 1:
2476                b43_nphy_rssi_select(dev, 1, 2);
2477                break;
2478        case 4:
2479                b43_nphy_rssi_select(dev, 1, 0);
2480                break;
2481        case 2:
2482                b43_nphy_rssi_select(dev, 1, 1);
2483                break;
2484        default:
2485                b43_nphy_rssi_select(dev, 1, 1);
2486                break;
2487        }
2488
2489        switch (state[3]) {
2490        case 1:
2491                b43_nphy_rssi_select(dev, 2, 2);
2492                break;
2493        case 4:
2494                b43_nphy_rssi_select(dev, 2, 0);
2495                break;
2496        default:
2497                b43_nphy_rssi_select(dev, 2, 1);
2498                break;
2499        }
2500
2501        b43_nphy_rssi_select(dev, 0, type);
2502
2503        b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2504        b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2505        b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2506        b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2507
2508        b43_nphy_classifier(dev, 7, class);
2509        b43_nphy_write_clip_detection(dev, clip_state);
2510        /* Specs don't say about reset here, but it makes wl and b43 dumps
2511           identical, it really seems wl performs this */
2512        b43_nphy_reset_cca(dev);
2513}
2514
2515/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2516static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2517{
2518        /* TODO */
2519}
2520
2521/*
2522 * RSSI Calibration
2523 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2524 */
2525static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2526{
2527        if (dev->phy.rev >= 3) {
2528                b43_nphy_rev3_rssi_cal(dev);
2529        } else {
2530                b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2531                b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2532                b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2533        }
2534}
2535
2536/*
2537 * Restore RSSI Calibration
2538 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2539 */
2540static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2541{
2542        struct b43_phy_n *nphy = dev->phy.n;
2543
2544        u16 *rssical_radio_regs = NULL;
2545        u16 *rssical_phy_regs = NULL;
2546
2547        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2548                if (!nphy->rssical_chanspec_2G.center_freq)
2549                        return;
2550                rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2551                rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2552        } else {
2553                if (!nphy->rssical_chanspec_5G.center_freq)
2554                        return;
2555                rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2556                rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2557        }
2558
2559        /* TODO use some definitions */
2560        b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2561        b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2562
2563        b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2564        b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2565        b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2566        b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2567
2568        b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2569        b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2570        b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2571        b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2572
2573        b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2574        b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2575        b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2576        b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2577}
2578
2579/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2580static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2581{
2582        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2583                if (dev->phy.rev >= 6) {
2584                        /* TODO If the chip is 47162
2585                                return txpwrctrl_tx_gain_ipa_rev5 */
2586                        return txpwrctrl_tx_gain_ipa_rev6;
2587                } else if (dev->phy.rev >= 5) {
2588                        return txpwrctrl_tx_gain_ipa_rev5;
2589                } else {
2590                        return txpwrctrl_tx_gain_ipa;
2591                }
2592        } else {
2593                return txpwrctrl_tx_gain_ipa_5g;
2594        }
2595}
2596
2597/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2598static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2599{
2600        struct b43_phy_n *nphy = dev->phy.n;
2601        u16 *save = nphy->tx_rx_cal_radio_saveregs;
2602        u16 tmp;
2603        u8 offset, i;
2604
2605        if (dev->phy.rev >= 3) {
2606            for (i = 0; i < 2; i++) {
2607                tmp = (i == 0) ? 0x2000 : 0x3000;
2608                offset = i * 11;
2609
2610                save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2611                save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2612                save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2613                save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2614                save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2615                save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2616                save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2617                save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2618                save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2619                save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2620                save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2621
2622                if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2623                        b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2624                        b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2625                        b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2626                        b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2627                        b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2628                        if (nphy->ipa5g_on) {
2629                                b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2630                                b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2631                        } else {
2632                                b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2633                                b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2634                        }
2635                        b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2636                } else {
2637                        b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2638                        b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2639                        b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2640                        b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2641                        b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2642                        b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2643                        if (nphy->ipa2g_on) {
2644                                b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2645                                b43_radio_write16(dev, tmp | B2055_XOCTL2,
2646                                        (dev->phy.rev < 5) ? 0x11 : 0x01);
2647                        } else {
2648                                b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2649                                b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2650                        }
2651                }
2652                b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2653                b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2654                b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2655            }
2656        } else {
2657                save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2658                b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2659
2660                save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2661                b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2662
2663                save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2664                b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2665
2666                save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2667                b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2668
2669                save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2670                save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2671
2672                if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2673                    B43_NPHY_BANDCTL_5GHZ)) {
2674                        b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2675                        b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2676                } else {
2677                        b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2678                        b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2679                }
2680
2681                if (dev->phy.rev < 2) {
2682                        b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2683                        b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2684                } else {
2685                        b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2686                        b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2687                }
2688        }
2689}
2690
2691/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2692static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2693                                        struct nphy_txgains target,
2694                                        struct nphy_iqcal_params *params)
2695{
2696        int i, j, indx;
2697        u16 gain;
2698
2699        if (dev->phy.rev >= 3) {
2700                params->txgm = target.txgm[core];
2701                params->pga = target.pga[core];
2702                params->pad = target.pad[core];
2703                params->ipa = target.ipa[core];
2704                params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2705                                        (params->pad << 4) | (params->ipa);
2706                for (j = 0; j < 5; j++)
2707                        params->ncorr[j] = 0x79;
2708        } else {
2709                gain = (target.pad[core]) | (target.pga[core] << 4) |
2710                        (target.txgm[core] << 8);
2711
2712                indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2713                        1 : 0;
2714                for (i = 0; i < 9; i++)
2715                        if (tbl_iqcal_gainparams[indx][i][0] == gain)
2716                                break;
2717                i = min(i, 8);
2718
2719                params->txgm = tbl_iqcal_gainparams[indx][i][1];
2720                params->pga = tbl_iqcal_gainparams[indx][i][2];
2721                params->pad = tbl_iqcal_gainparams[indx][i][3];
2722                params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2723                                        (params->pad << 2);
2724                for (j = 0; j < 4; j++)
2725                        params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2726        }
2727}
2728
2729/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2730static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2731{
2732        struct b43_phy_n *nphy = dev->phy.n;
2733        int i;
2734        u16 scale, entry;
2735
2736        u16 tmp = nphy->txcal_bbmult;
2737        if (core == 0)
2738                tmp >>= 8;
2739        tmp &= 0xff;
2740
2741        for (i = 0; i < 18; i++) {
2742                scale = (ladder_lo[i].percent * tmp) / 100;
2743                entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2744                b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2745
2746                scale = (ladder_iq[i].percent * tmp) / 100;
2747                entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2748                b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2749        }
2750}
2751
2752/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2753static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2754{
2755        int i;
2756        for (i = 0; i < 15; i++)
2757                b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2758                                tbl_tx_filter_coef_rev4[2][i]);
2759}
2760
2761/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2762static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2763{
2764        int i, j;
2765        /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2766        static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2767
2768        for (i = 0; i < 3; i++)
2769                for (j = 0; j < 15; j++)
2770                        b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2771                                        tbl_tx_filter_coef_rev4[i][j]);
2772
2773        if (dev->phy.is_40mhz) {
2774                for (j = 0; j < 15; j++)
2775                        b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2776                                        tbl_tx_filter_coef_rev4[3][j]);
2777        } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2778                for (j = 0; j < 15; j++)
2779                        b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2780                                        tbl_tx_filter_coef_rev4[5][j]);
2781        }
2782
2783        if (dev->phy.channel == 14)
2784                for (j = 0; j < 15; j++)
2785                        b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2786                                        tbl_tx_filter_coef_rev4[6][j]);
2787}
2788
2789/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2790static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2791{
2792        struct b43_phy_n *nphy = dev->phy.n;
2793
2794        u16 curr_gain[2];
2795        struct nphy_txgains target;
2796        const u32 *table = NULL;
2797
2798        if (!nphy->txpwrctrl) {
2799                int i;
2800
2801                if (nphy->hang_avoid)
2802                        b43_nphy_stay_in_carrier_search(dev, true);
2803                b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2804                if (nphy->hang_avoid)
2805                        b43_nphy_stay_in_carrier_search(dev, false);
2806
2807                for (i = 0; i < 2; ++i) {
2808                        if (dev->phy.rev >= 3) {
2809                                target.ipa[i] = curr_gain[i] & 0x000F;
2810                                target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2811                                target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2812                                target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2813                        } else {
2814                                target.ipa[i] = curr_gain[i] & 0x0003;
2815                                target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2816                                target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2817                                target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2818                        }
2819                }
2820        } else {
2821                int i;
2822                u16 index[2];
2823                index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2824                        B43_NPHY_TXPCTL_STAT_BIDX) >>
2825                        B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2826                index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2827                        B43_NPHY_TXPCTL_STAT_BIDX) >>
2828                        B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2829
2830                for (i = 0; i < 2; ++i) {
2831                        if (dev->phy.rev >= 3) {
2832                                enum ieee80211_band band =
2833                                        b43_current_band(dev->wl);
2834
2835                                if ((nphy->ipa2g_on &&
2836                                     band == IEEE80211_BAND_2GHZ) ||
2837                                    (nphy->ipa5g_on &&
2838                                     band == IEEE80211_BAND_5GHZ)) {
2839                                        table = b43_nphy_get_ipa_gain_table(dev);
2840                                } else {
2841                                        if (band == IEEE80211_BAND_5GHZ) {
2842                                                if (dev->phy.rev == 3)
2843                                                        table = b43_ntab_tx_gain_rev3_5ghz;
2844                                                else if (dev->phy.rev == 4)
2845                                                        table = b43_ntab_tx_gain_rev4_5ghz;
2846                                                else
2847                                                        table = b43_ntab_tx_gain_rev5plus_5ghz;
2848                                        } else {
2849                                                table = b43_ntab_tx_gain_rev3plus_2ghz;
2850                                        }
2851                                }
2852
2853                                target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2854                                target.pad[i] = (table[index[i]] >> 20) & 0xF;
2855                                target.pga[i] = (table[index[i]] >> 24) & 0xF;
2856                                target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2857                        } else {
2858                                table = b43_ntab_tx_gain_rev0_1_2;
2859
2860                                target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2861                                target.pad[i] = (table[index[i]] >> 18) & 0x3;
2862                                target.pga[i] = (table[index[i]] >> 20) & 0x7;
2863                                target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2864                        }
2865                }
2866        }
2867
2868        return target;
2869}
2870
2871/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2872static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2873{
2874        u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2875
2876        if (dev->phy.rev >= 3) {
2877                b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2878                b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2879                b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2880                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2881                b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2882                b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2883                b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2884                b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2885                b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2886                b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2887                b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2888                b43_nphy_reset_cca(dev);
2889        } else {
2890                b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2891                b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2892                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2893                b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2894                b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2895                b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2896                b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2897        }
2898}
2899
2900/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2901static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2902{
2903        u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2904        u16 tmp;
2905
2906        regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2907        regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2908        if (dev->phy.rev >= 3) {
2909                b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2910                b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2911
2912                tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2913                regs[2] = tmp;
2914                b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2915
2916                tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2917                regs[3] = tmp;
2918                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2919
2920                regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2921                b43_phy_mask(dev, B43_NPHY_BBCFG,
2922                             ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2923
2924                tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2925                regs[5] = tmp;
2926                b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2927
2928                tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2929                regs[6] = tmp;
2930                b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2931                regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2932                regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2933
2934                b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2935                b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2936                b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2937
2938                regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2939                regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2940                b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2941                b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2942        } else {
2943                b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2944                b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2945                tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2946                regs[2] = tmp;
2947                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2948                tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2949                regs[3] = tmp;
2950                tmp |= 0x2000;
2951                b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2952                tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2953                regs[4] = tmp;
2954                tmp |= 0x2000;
2955                b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2956                regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2957                regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2958                if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2959                        tmp = 0x0180;
2960                else
2961                        tmp = 0x0120;
2962                b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2963                b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2964        }
2965}
2966
2967/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2968static void b43_nphy_save_cal(struct b43_wldev *dev)
2969{
2970        struct b43_phy_n *nphy = dev->phy.n;
2971
2972        struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2973        u16 *txcal_radio_regs = NULL;
2974        struct b43_chanspec *iqcal_chanspec;
2975        u16 *table = NULL;
2976
2977        if (nphy->hang_avoid)
2978                b43_nphy_stay_in_carrier_search(dev, 1);
2979
2980        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2981                rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2982                txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2983                iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2984                table = nphy->cal_cache.txcal_coeffs_2G;
2985        } else {
2986                rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2987                txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2988                iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2989                table = nphy->cal_cache.txcal_coeffs_5G;
2990        }
2991
2992        b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2993        /* TODO use some definitions */
2994        if (dev->phy.rev >= 3) {
2995                txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2996                txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2997                txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2998                txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2999                txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3000                txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3001                txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3002                txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3003        } else {
3004                txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3005                txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3006                txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3007                txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3008        }
3009        iqcal_chanspec->center_freq = dev->phy.channel_freq;
3010        iqcal_chanspec->channel_type = dev->phy.channel_type;
3011        b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3012
3013        if (nphy->hang_avoid)
3014                b43_nphy_stay_in_carrier_search(dev, 0);
3015}
3016
3017/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3018static void b43_nphy_restore_cal(struct b43_wldev *dev)
3019{
3020        struct b43_phy_n *nphy = dev->phy.n;
3021
3022        u16 coef[4];
3023        u16 *loft = NULL;
3024        u16 *table = NULL;
3025
3026        int i;
3027        u16 *txcal_radio_regs = NULL;
3028        struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3029
3030        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3031                if (!nphy->iqcal_chanspec_2G.center_freq)
3032                        return;
3033                table = nphy->cal_cache.txcal_coeffs_2G;
3034                loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3035        } else {
3036                if (!nphy->iqcal_chanspec_5G.center_freq)
3037                        return;
3038                table = nphy->cal_cache.txcal_coeffs_5G;
3039                loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3040        }
3041
3042        b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3043
3044        for (i = 0; i < 4; i++) {
3045                if (dev->phy.rev >= 3)
3046                        table[i] = coef[i];
3047                else
3048                        coef[i] = 0;
3049        }
3050
3051        b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3052        b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3053        b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3054
3055        if (dev->phy.rev < 2)
3056                b43_nphy_tx_iq_workaround(dev);
3057
3058        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3059                txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3060                rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3061        } else {
3062                txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3063                rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3064        }
3065
3066        /* TODO use some definitions */
3067        if (dev->phy.rev >= 3) {
3068                b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3069                b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3070                b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3071                b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3072                b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3073                b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3074                b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3075                b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3076        } else {
3077                b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3078                b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3079                b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3080                b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3081        }
3082        b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3083}
3084
3085/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3086static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3087                                struct nphy_txgains target,
3088                                bool full, bool mphase)
3089{
3090        struct b43_phy_n *nphy = dev->phy.n;
3091        int i;
3092        int error = 0;
3093        int freq;
3094        bool avoid = false;
3095        u8 length;
3096        u16 tmp, core, type, count, max, numb, last = 0, cmd;
3097        const u16 *table;
3098        bool phy6or5x;
3099
3100        u16 buffer[11];
3101        u16 diq_start = 0;
3102        u16 save[2];
3103        u16 gain[2];
3104        struct nphy_iqcal_params params[2];
3105        bool updated[2] = { };
3106
3107        b43_nphy_stay_in_carrier_search(dev, true);
3108
3109        if (dev->phy.rev >= 4) {
3110                avoid = nphy->hang_avoid;
3111                nphy->hang_avoid = 0;
3112        }
3113
3114        b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3115
3116        for (i = 0; i < 2; i++) {
3117                b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3118                gain[i] = params[i].cal_gain;
3119        }
3120
3121        b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3122
3123        b43_nphy_tx_cal_radio_setup(dev);
3124        b43_nphy_tx_cal_phy_setup(dev);
3125
3126        phy6or5x = dev->phy.rev >= 6 ||
3127                (dev->phy.rev == 5 && nphy->ipa2g_on &&
3128                b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3129        if (phy6or5x) {
3130                if (dev->phy.is_40mhz) {
3131                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3132                                        tbl_tx_iqlo_cal_loft_ladder_40);
3133                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3134                                        tbl_tx_iqlo_cal_iqimb_ladder_40);
3135                } else {
3136                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3137                                        tbl_tx_iqlo_cal_loft_ladder_20);
3138                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3139                                        tbl_tx_iqlo_cal_iqimb_ladder_20);
3140                }
3141        }
3142
3143        b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3144
3145        if (!dev->phy.is_40mhz)
3146                freq = 2500;
3147        else
3148                freq = 5000;
3149
3150        if (nphy->mphase_cal_phase_id > 2)
3151                b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3152                                        0xFFFF, 0, true, false);
3153        else
3154                error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3155
3156        if (error == 0) {
3157                if (nphy->mphase_cal_phase_id > 2) {
3158                        table = nphy->mphase_txcal_bestcoeffs;
3159                        length = 11;
3160                        if (dev->phy.rev < 3)
3161                                length -= 2;
3162                } else {
3163                        if (!full && nphy->txiqlocal_coeffsvalid) {
3164                                table = nphy->txiqlocal_bestc;
3165                                length = 11;
3166                                if (dev->phy.rev < 3)
3167                                        length -= 2;
3168                        } else {
3169                                full = true;
3170                                if (dev->phy.rev >= 3) {
3171                                        table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3172                                        length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3173                                } else {
3174                                        table = tbl_tx_iqlo_cal_startcoefs;
3175                                        length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3176                                }
3177                        }
3178                }
3179
3180                b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3181
3182                if (full) {
3183                        if (dev->phy.rev >= 3)
3184                                max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3185                        else
3186                                max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3187                } else {
3188                        if (dev->phy.rev >= 3)
3189                                max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3190                        else
3191                                max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3192                }
3193
3194                if (mphase) {
3195                        count = nphy->mphase_txcal_cmdidx;
3196                        numb = min(max,
3197                                (u16)(count + nphy->mphase_txcal_numcmds));
3198                } else {
3199                        count = 0;
3200                        numb = max;
3201                }
3202
3203                for (; count < numb; count++) {
3204                        if (full) {
3205                                if (dev->phy.rev >= 3)
3206                                        cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3207                                else
3208                                        cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3209                        } else {
3210                                if (dev->phy.rev >= 3)
3211                                        cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3212                                else
3213                                        cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3214                        }
3215
3216                        core = (cmd & 0x3000) >> 12;
3217                        type = (cmd & 0x0F00) >> 8;
3218
3219                        if (phy6or5x && updated[core] == 0) {
3220                                b43_nphy_update_tx_cal_ladder(dev, core);
3221                                updated[core] = 1;
3222                        }
3223
3224                        tmp = (params[core].ncorr[type] << 8) | 0x66;
3225                        b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3226
3227                        if (type == 1 || type == 3 || type == 4) {
3228                                buffer[0] = b43_ntab_read(dev,
3229                                                B43_NTAB16(15, 69 + core));
3230                                diq_start = buffer[0];
3231                                buffer[0] = 0;
3232                                b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3233                                                0);
3234                        }
3235
3236                        b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3237                        for (i = 0; i < 2000; i++) {
3238                                tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3239                                if (tmp & 0xC000)
3240                                        break;
3241                                udelay(10);
3242                        }
3243
3244                        b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3245                                                buffer);
3246                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3247                                                buffer);
3248
3249                        if (type == 1 || type == 3 || type == 4)
3250                                buffer[0] = diq_start;
3251                }
3252
3253                if (mphase)
3254                        nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3255
3256                last = (dev->phy.rev < 3) ? 6 : 7;
3257
3258                if (!mphase || nphy->mphase_cal_phase_id == last) {
3259                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3260                        b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3261                        if (dev->phy.rev < 3) {
3262                                buffer[0] = 0;
3263                                buffer[1] = 0;
3264                                buffer[2] = 0;
3265                                buffer[3] = 0;
3266                        }
3267                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3268                                                buffer);
3269                        b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3270                                                buffer);
3271                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3272                                                buffer);
3273                        b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3274                                                buffer);
3275                        length = 11;
3276                        if (dev->phy.rev < 3)
3277                                length -= 2;
3278                        b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3279                                                nphy->txiqlocal_bestc);
3280                        nphy->txiqlocal_coeffsvalid = true;
3281                        nphy->txiqlocal_chanspec.center_freq =
3282                                                        dev->phy.channel_freq;
3283                        nphy->txiqlocal_chanspec.channel_type =
3284                                                        dev->phy.channel_type;
3285                } else {
3286                        length = 11;
3287                        if (dev->phy.rev < 3)
3288                                length -= 2;
3289                        b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3290                                                nphy->mphase_txcal_bestcoeffs);
3291                }
3292
3293                b43_nphy_stop_playback(dev);
3294                b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3295        }
3296
3297        b43_nphy_tx_cal_phy_cleanup(dev);
3298        b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3299
3300        if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3301                b43_nphy_tx_iq_workaround(dev);
3302
3303        if (dev->phy.rev >= 4)
3304                nphy->hang_avoid = avoid;
3305
3306        b43_nphy_stay_in_carrier_search(dev, false);
3307
3308        return error;
3309}
3310
3311/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3312static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3313{
3314        struct b43_phy_n *nphy = dev->phy.n;
3315        u8 i;
3316        u16 buffer[7];
3317        bool equal = true;
3318
3319        if (!nphy->txiqlocal_coeffsvalid ||
3320            nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3321            nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3322                return;
3323
3324        b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3325        for (i = 0; i < 4; i++) {
3326                if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3327                        equal = false;
3328                        break;
3329                }
3330        }
3331
3332        if (!equal) {
3333                b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3334                                        nphy->txiqlocal_bestc);
3335                for (i = 0; i < 4; i++)
3336                        buffer[i] = 0;
3337                b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3338                                        buffer);
3339                b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3340                                        &nphy->txiqlocal_bestc[5]);
3341                b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3342                                        &nphy->txiqlocal_bestc[5]);
3343        }
3344}
3345
3346/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3347static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3348                        struct nphy_txgains target, u8 type, bool debug)
3349{
3350        struct b43_phy_n *nphy = dev->phy.n;
3351        int i, j, index;
3352        u8 rfctl[2];
3353        u8 afectl_core;
3354        u16 tmp[6];
3355        u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3356        u32 real, imag;
3357        enum ieee80211_band band;
3358
3359        u8 use;
3360        u16 cur_hpf;
3361        u16 lna[3] = { 3, 3, 1 };
3362        u16 hpf1[3] = { 7, 2, 0 };
3363        u16 hpf2[3] = { 2, 0, 0 };
3364        u32 power[3] = { };
3365        u16 gain_save[2];
3366        u16 cal_gain[2];
3367        struct nphy_iqcal_params cal_params[2];
3368        struct nphy_iq_est est;
3369        int ret = 0;
3370        bool playtone = true;
3371        int desired = 13;
3372
3373        b43_nphy_stay_in_carrier_search(dev, 1);
3374
3375        if (dev->phy.rev < 2)
3376                b43_nphy_reapply_tx_cal_coeffs(dev);
3377        b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3378        for (i = 0; i < 2; i++) {
3379                b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3380                cal_gain[i] = cal_params[i].cal_gain;
3381        }
3382        b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3383
3384        for (i = 0; i < 2; i++) {
3385                if (i == 0) {
3386                        rfctl[0] = B43_NPHY_RFCTL_INTC1;
3387                        rfctl[1] = B43_NPHY_RFCTL_INTC2;
3388                        afectl_core = B43_NPHY_AFECTL_C1;
3389                } else {
3390                        rfctl[0] = B43_NPHY_RFCTL_INTC2;
3391                        rfctl[1] = B43_NPHY_RFCTL_INTC1;
3392                        afectl_core = B43_NPHY_AFECTL_C2;
3393                }
3394
3395                tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3396                tmp[2] = b43_phy_read(dev, afectl_core);
3397                tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3398                tmp[4] = b43_phy_read(dev, rfctl[0]);
3399                tmp[5] = b43_phy_read(dev, rfctl[1]);
3400
3401                b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3402                                ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3403                                ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3404                b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3405                                (1 - i));
3406                b43_phy_set(dev, afectl_core, 0x0006);
3407                b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3408
3409                band = b43_current_band(dev->wl);
3410
3411                if (nphy->rxcalparams & 0xFF000000) {
3412                        if (band == IEEE80211_BAND_5GHZ)
3413                                b43_phy_write(dev, rfctl[0], 0x140);
3414                        else
3415                                b43_phy_write(dev, rfctl[0], 0x110);
3416                } else {
3417                        if (band == IEEE80211_BAND_5GHZ)
3418                                b43_phy_write(dev, rfctl[0], 0x180);
3419                        else
3420                                b43_phy_write(dev, rfctl[0], 0x120);
3421                }
3422
3423                if (band == IEEE80211_BAND_5GHZ)
3424                        b43_phy_write(dev, rfctl[1], 0x148);
3425                else
3426                        b43_phy_write(dev, rfctl[1], 0x114);
3427
3428                if (nphy->rxcalparams & 0x10000) {
3429                        b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3430                                        (i + 1));
3431                        b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3432                                        (2 - i));
3433                }
3434
3435                for (j = 0; j < 4; j++) {
3436                        if (j < 3) {
3437                                cur_lna = lna[j];
3438                                cur_hpf1 = hpf1[j];
3439                                cur_hpf2 = hpf2[j];
3440                        } else {
3441                                if (power[1] > 10000) {
3442                                        use = 1;
3443                                        cur_hpf = cur_hpf1;
3444                                        index = 2;
3445                                } else {
3446                                        if (power[0] > 10000) {
3447                                                use = 1;
3448                                                cur_hpf = cur_hpf1;
3449                                                index = 1;
3450                                        } else {
3451                                                index = 0;
3452                                                use = 2;
3453                                                cur_hpf = cur_hpf2;
3454                                        }
3455                                }
3456                                cur_lna = lna[index];
3457                                cur_hpf1 = hpf1[index];
3458                                cur_hpf2 = hpf2[index];
3459                                cur_hpf += desired - hweight32(power[index]);
3460                                cur_hpf = clamp_val(cur_hpf, 0, 10);
3461                                if (use == 1)
3462                                        cur_hpf1 = cur_hpf;
3463                                else
3464                                        cur_hpf2 = cur_hpf;
3465                        }
3466
3467                        tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3468                                        (cur_lna << 2));
3469                        b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3470                                                                        false);
3471                        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3472                        b43_nphy_stop_playback(dev);
3473
3474                        if (playtone) {
3475                                ret = b43_nphy_tx_tone(dev, 4000,
3476                                                (nphy->rxcalparams & 0xFFFF),
3477                                                false, false);
3478                                playtone = false;
3479                        } else {
3480                                b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3481                                                        false, false);
3482                        }
3483
3484                        if (ret == 0) {
3485                                if (j < 3) {
3486                                        b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3487                                                                        false);
3488                                        if (i == 0) {
3489                                                real = est.i0_pwr;
3490                                                imag = est.q0_pwr;
3491                                        } else {
3492                                                real = est.i1_pwr;
3493                                                imag = est.q1_pwr;
3494                                        }
3495                                        power[i] = ((real + imag) / 1024) + 1;
3496                                } else {
3497                                        b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3498                                }
3499                                b43_nphy_stop_playback(dev);
3500                        }
3501
3502                        if (ret != 0)
3503                                break;
3504                }
3505
3506                b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3507                b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3508                b43_phy_write(dev, rfctl[1], tmp[5]);
3509                b43_phy_write(dev, rfctl[0], tmp[4]);
3510                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3511                b43_phy_write(dev, afectl_core, tmp[2]);
3512                b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3513
3514                if (ret != 0)
3515                        break;
3516        }
3517
3518        b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3519        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3520        b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3521
3522        b43_nphy_stay_in_carrier_search(dev, 0);
3523
3524        return ret;
3525}
3526
3527static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3528                        struct nphy_txgains target, u8 type, bool debug)
3529{
3530        return -1;
3531}
3532
3533/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3534static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3535                        struct nphy_txgains target, u8 type, bool debug)
3536{
3537        if (dev->phy.rev >= 3)
3538                return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3539        else
3540                return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3541}
3542
3543/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3544static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3545{
3546        struct b43_phy *phy = &dev->phy;
3547        struct b43_phy_n *nphy = phy->n;
3548        /* u16 buf[16]; it's rev3+ */
3549
3550        nphy->phyrxchain = mask;
3551
3552        if (0 /* FIXME clk */)
3553                return;
3554
3555        b43_mac_suspend(dev);
3556
3557        if (nphy->hang_avoid)
3558                b43_nphy_stay_in_carrier_search(dev, true);
3559
3560        b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3561                        (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3562
3563        if ((mask & 0x3) != 0x3) {
3564                b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3565                if (dev->phy.rev >= 3) {
3566                        /* TODO */
3567                }
3568        } else {
3569                b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3570                if (dev->phy.rev >= 3) {
3571                        /* TODO */
3572                }
3573        }
3574
3575        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3576
3577        if (nphy->hang_avoid)
3578                b43_nphy_stay_in_carrier_search(dev, false);
3579
3580        b43_mac_enable(dev);
3581}
3582
3583/*
3584 * Init N-PHY
3585 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3586 */
3587int b43_phy_initn(struct b43_wldev *dev)
3588{
3589        struct ssb_bus *bus = dev->sdev->bus;
3590        struct b43_phy *phy = &dev->phy;
3591        struct b43_phy_n *nphy = phy->n;
3592        u8 tx_pwr_state;
3593        struct nphy_txgains target;
3594        u16 tmp;
3595        enum ieee80211_band tmp2;
3596        bool do_rssi_cal;
3597
3598        u16 clip[2];
3599        bool do_cal = false;
3600
3601        if ((dev->phy.rev >= 3) &&
3602           (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3603           (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3604                chipco_set32(&dev->sdev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3605        }
3606        nphy->deaf_count = 0;
3607        b43_nphy_tables_init(dev);
3608        nphy->crsminpwr_adjusted = false;
3609        nphy->noisevars_adjusted = false;
3610
3611        /* Clear all overrides */
3612        if (dev->phy.rev >= 3) {
3613                b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3614                b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3615                b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3616                b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3617        } else {
3618                b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3619        }
3620        b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3621        b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3622        if (dev->phy.rev < 6) {
3623                b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3624                b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3625        }
3626        b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3627                     ~(B43_NPHY_RFSEQMODE_CAOVER |
3628                       B43_NPHY_RFSEQMODE_TROVER));
3629        if (dev->phy.rev >= 3)
3630                b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3631        b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3632
3633        if (dev->phy.rev <= 2) {
3634                tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3635                b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3636                                ~B43_NPHY_BPHY_CTL3_SCALE,
3637                                tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3638        }
3639        b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3640        b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3641
3642        if (bus->sprom.boardflags2_lo & 0x100 ||
3643            (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3644             bus->boardinfo.type == 0x8B))
3645                b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3646        else
3647                b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3648        b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3649        b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3650        b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3651
3652        b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3653        b43_nphy_update_txrx_chain(dev);
3654
3655        if (phy->rev < 2) {
3656                b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3657                b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3658        }
3659
3660        tmp2 = b43_current_band(dev->wl);
3661        if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3662            (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3663                b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3664                b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3665                                nphy->papd_epsilon_offset[0] << 7);
3666                b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3667                b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3668                                nphy->papd_epsilon_offset[1] << 7);
3669                b43_nphy_int_pa_set_tx_dig_filters(dev);
3670        } else if (phy->rev >= 5) {
3671                b43_nphy_ext_pa_set_tx_dig_filters(dev);
3672        }
3673
3674        b43_nphy_workarounds(dev);
3675
3676        /* Reset CCA, in init code it differs a little from standard way */
3677        b43_nphy_bmac_clock_fgc(dev, 1);
3678        tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3679        b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3680        b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3681        b43_nphy_bmac_clock_fgc(dev, 0);
3682
3683        b43_mac_phy_clock_set(dev, true);
3684
3685        b43_nphy_pa_override(dev, false);
3686        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3687        b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3688        b43_nphy_pa_override(dev, true);
3689
3690        b43_nphy_classifier(dev, 0, 0);
3691        b43_nphy_read_clip_detection(dev, clip);
3692        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3693                b43_nphy_bphy_init(dev);
3694
3695        tx_pwr_state = nphy->txpwrctrl;
3696        b43_nphy_tx_power_ctrl(dev, false);
3697        b43_nphy_tx_power_fix(dev);
3698        /* TODO N PHY TX Power Control Idle TSSI */
3699        /* TODO N PHY TX Power Control Setup */
3700
3701        if (phy->rev >= 3) {
3702                /* TODO */
3703        } else {
3704                b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3705                                        b43_ntab_tx_gain_rev0_1_2);
3706                b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3707                                        b43_ntab_tx_gain_rev0_1_2);
3708        }
3709
3710        if (nphy->phyrxchain != 3)
3711                b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3712        if (nphy->mphase_cal_phase_id > 0)
3713                ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3714
3715        do_rssi_cal = false;
3716        if (phy->rev >= 3) {
3717                if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3718                        do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3719                else
3720                        do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3721
3722                if (do_rssi_cal)
3723                        b43_nphy_rssi_cal(dev);
3724                else
3725                        b43_nphy_restore_rssi_cal(dev);
3726        } else {
3727                b43_nphy_rssi_cal(dev);
3728        }
3729
3730        if (!((nphy->measure_hold & 0x6) != 0)) {
3731                if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3732                        do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3733                else
3734                        do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3735
3736                if (nphy->mute)
3737                        do_cal = false;
3738
3739                if (do_cal) {
3740                        target = b43_nphy_get_tx_gains(dev);
3741
3742                        if (nphy->antsel_type == 2)
3743                                b43_nphy_superswitch_init(dev, true);
3744                        if (nphy->perical != 2) {
3745                                b43_nphy_rssi_cal(dev);
3746                                if (phy->rev >= 3) {
3747                                        nphy->cal_orig_pwr_idx[0] =
3748                                            nphy->txpwrindex[0].index_internal;
3749                                        nphy->cal_orig_pwr_idx[1] =
3750                                            nphy->txpwrindex[1].index_internal;
3751                                        /* TODO N PHY Pre Calibrate TX Gain */
3752                                        target = b43_nphy_get_tx_gains(dev);
3753                                }
3754                                if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3755                                        if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3756                                                b43_nphy_save_cal(dev);
3757                        } else if (nphy->mphase_cal_phase_id == 0)
3758                                ;/* N PHY Periodic Calibration with arg 3 */
3759                } else {
3760                        b43_nphy_restore_cal(dev);
3761                }
3762        }
3763
3764        b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3765        b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3766        b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3767        b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3768        if (phy->rev >= 3 && phy->rev <= 6)
3769                b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3770        b43_nphy_tx_lp_fbw(dev);
3771        if (phy->rev >= 3)
3772                b43_nphy_spur_workaround(dev);
3773
3774        return 0;
3775}
3776
3777/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3778static void b43_nphy_channel_setup(struct b43_wldev *dev,
3779                                const struct b43_phy_n_sfo_cfg *e,
3780                                struct ieee80211_channel *new_channel)
3781{
3782        struct b43_phy *phy = &dev->phy;
3783        struct b43_phy_n *nphy = dev->phy.n;
3784
3785        u16 old_band_5ghz;
3786        u32 tmp32;
3787
3788        old_band_5ghz =
3789                b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3790        if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3791                tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3792                b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3793                b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3794                b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3795                b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3796        } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3797                b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3798                tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3799                b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3800                b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3801                b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3802        }
3803
3804        b43_chantab_phy_upload(dev, e);
3805
3806        if (new_channel->hw_value == 14) {
3807                b43_nphy_classifier(dev, 2, 0);
3808                b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3809        } else {
3810                b43_nphy_classifier(dev, 2, 2);
3811                if (new_channel->band == IEEE80211_BAND_2GHZ)
3812                        b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3813        }
3814
3815        if (!nphy->txpwrctrl)
3816                b43_nphy_tx_power_fix(dev);
3817
3818        if (dev->phy.rev < 3)
3819                b43_nphy_adjust_lna_gain_table(dev);
3820
3821        b43_nphy_tx_lp_fbw(dev);
3822
3823        if (dev->phy.rev >= 3 && 0) {
3824                /* TODO */
3825        }
3826
3827        b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3828
3829        if (phy->rev >= 3)
3830                b43_nphy_spur_workaround(dev);
3831}
3832
3833/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3834static int b43_nphy_set_channel(struct b43_wldev *dev,
3835                                struct ieee80211_channel *channel,
3836                                enum nl80211_channel_type channel_type)
3837{
3838        struct b43_phy *phy = &dev->phy;
3839
3840        const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3841        const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
3842
3843        u8 tmp;
3844
3845        if (dev->phy.rev >= 3) {
3846                tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3847                                                        channel->center_freq);
3848                if (!tabent_r3)
3849                        return -ESRCH;
3850        } else {
3851                tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3852                                                        channel->hw_value);
3853                if (!tabent_r2)
3854                        return -ESRCH;
3855        }
3856
3857        /* Channel is set later in common code, but we need to set it on our
3858           own to let this function's subcalls work properly. */
3859        phy->channel = channel->hw_value;
3860        phy->channel_freq = channel->center_freq;
3861
3862        if (b43_channel_type_is_40mhz(phy->channel_type) !=
3863                b43_channel_type_is_40mhz(channel_type))
3864                ; /* TODO: BMAC BW Set (channel_type) */
3865
3866        if (channel_type == NL80211_CHAN_HT40PLUS)
3867                b43_phy_set(dev, B43_NPHY_RXCTL,
3868                                B43_NPHY_RXCTL_BSELU20);
3869        else if (channel_type == NL80211_CHAN_HT40MINUS)
3870                b43_phy_mask(dev, B43_NPHY_RXCTL,
3871                                ~B43_NPHY_RXCTL_BSELU20);
3872
3873        if (dev->phy.rev >= 3) {
3874                tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3875                b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3876                b43_radio_2056_setup(dev, tabent_r3);
3877                b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3878        } else {
3879                tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3880                b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3881                b43_radio_2055_setup(dev, tabent_r2);
3882                b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3883        }
3884
3885        return 0;
3886}
3887
3888static int b43_nphy_op_allocate(struct b43_wldev *dev)
3889{
3890        struct b43_phy_n *nphy;
3891
3892        nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3893        if (!nphy)
3894                return -ENOMEM;
3895        dev->phy.n = nphy;
3896
3897        return 0;
3898}
3899
3900static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3901{
3902        struct b43_phy *phy = &dev->phy;
3903        struct b43_phy_n *nphy = phy->n;
3904
3905        memset(nphy, 0, sizeof(*nphy));
3906
3907        nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3908        nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3909        nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3910        nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3911        nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3912}
3913
3914static void b43_nphy_op_free(struct b43_wldev *dev)
3915{
3916        struct b43_phy *phy = &dev->phy;
3917        struct b43_phy_n *nphy = phy->n;
3918
3919        kfree(nphy);
3920        phy->n = NULL;
3921}
3922
3923static int b43_nphy_op_init(struct b43_wldev *dev)
3924{
3925        return b43_phy_initn(dev);
3926}
3927
3928static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3929{
3930#if B43_DEBUG
3931        if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3932                /* OFDM registers are onnly available on A/G-PHYs */
3933                b43err(dev->wl, "Invalid OFDM PHY access at "
3934                       "0x%04X on N-PHY\n", offset);
3935                dump_stack();
3936        }
3937        if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3938                /* Ext-G registers are only available on G-PHYs */
3939                b43err(dev->wl, "Invalid EXT-G PHY access at "
3940                       "0x%04X on N-PHY\n", offset);
3941                dump_stack();
3942        }
3943#endif /* B43_DEBUG */
3944}
3945
3946static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3947{
3948        check_phyreg(dev, reg);
3949        b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3950        return b43_read16(dev, B43_MMIO_PHY_DATA);
3951}
3952
3953static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3954{
3955        check_phyreg(dev, reg);
3956        b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3957        b43_write16(dev, B43_MMIO_PHY_DATA, value);
3958}
3959
3960static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3961                                 u16 set)
3962{
3963        check_phyreg(dev, reg);
3964        b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3965        b43_write16(dev, B43_MMIO_PHY_DATA,
3966                    (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3967}
3968
3969static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3970{
3971        /* Register 1 is a 32-bit register. */
3972        B43_WARN_ON(reg == 1);
3973        /* N-PHY needs 0x100 for read access */
3974        reg |= 0x100;
3975
3976        b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3977        return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3978}
3979
3980static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3981{
3982        /* Register 1 is a 32-bit register. */
3983        B43_WARN_ON(reg == 1);
3984
3985        b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3986        b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3987}
3988
3989/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3990static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3991                                        bool blocked)
3992{
3993        if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3994                b43err(dev->wl, "MAC not suspended\n");
3995
3996        if (blocked) {
3997                b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3998                                ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3999                if (dev->phy.rev >= 3) {
4000                        b43_radio_mask(dev, 0x09, ~0x2);
4001
4002                        b43_radio_write(dev, 0x204D, 0);
4003                        b43_radio_write(dev, 0x2053, 0);
4004                        b43_radio_write(dev, 0x2058, 0);
4005                        b43_radio_write(dev, 0x205E, 0);
4006                        b43_radio_mask(dev, 0x2062, ~0xF0);
4007                        b43_radio_write(dev, 0x2064, 0);
4008
4009                        b43_radio_write(dev, 0x304D, 0);
4010                        b43_radio_write(dev, 0x3053, 0);
4011                        b43_radio_write(dev, 0x3058, 0);
4012                        b43_radio_write(dev, 0x305E, 0);
4013                        b43_radio_mask(dev, 0x3062, ~0xF0);
4014                        b43_radio_write(dev, 0x3064, 0);
4015                }
4016        } else {
4017                if (dev->phy.rev >= 3) {
4018                        b43_radio_init2056(dev);
4019                        b43_switch_channel(dev, dev->phy.channel);
4020                } else {
4021                        b43_radio_init2055(dev);
4022                }
4023        }
4024}
4025
4026/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4027static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4028{
4029        u16 val = on ? 0 : 0x7FFF;
4030
4031        if (dev->phy.rev >= 3)
4032                b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, val);
4033        b43_phy_write(dev, B43_NPHY_AFECTL_OVER, val);
4034}
4035
4036static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4037                                      unsigned int new_channel)
4038{
4039        struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4040        enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4041
4042        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4043                if ((new_channel < 1) || (new_channel > 14))
4044                        return -EINVAL;
4045        } else {
4046                if (new_channel > 200)
4047                        return -EINVAL;
4048        }
4049
4050        return b43_nphy_set_channel(dev, channel, channel_type);
4051}
4052
4053static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4054{
4055        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4056                return 1;
4057        return 36;
4058}
4059
4060const struct b43_phy_operations b43_phyops_n = {
4061        .allocate               = b43_nphy_op_allocate,
4062        .free                   = b43_nphy_op_free,
4063        .prepare_structs        = b43_nphy_op_prepare_structs,
4064        .init                   = b43_nphy_op_init,
4065        .phy_read               = b43_nphy_op_read,
4066        .phy_write              = b43_nphy_op_write,
4067        .phy_maskset            = b43_nphy_op_maskset,
4068        .radio_read             = b43_nphy_op_radio_read,
4069        .radio_write            = b43_nphy_op_radio_write,
4070        .software_rfkill        = b43_nphy_op_software_rfkill,
4071        .switch_analog          = b43_nphy_op_switch_analog,
4072        .switch_channel         = b43_nphy_op_switch_channel,
4073        .get_default_chan       = b43_nphy_op_get_default_chan,
4074        .recalc_txpower         = b43_nphy_op_recalc_txpower,
4075        .adjust_txpower         = b43_nphy_op_adjust_txpower,
4076};
4077