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18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/etherdevice.h>
23#include <linux/eeprom_93cx6.h>
24#include <net/mac80211.h>
25
26#include "rtl8180.h"
27#include "rtl8225.h"
28#include "sa2400.h"
29#include "max2820.h"
30#include "grf5101.h"
31
32MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
33MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
34MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
35MODULE_LICENSE("GPL");
36
37static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
38
39 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
40 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
42
43
44 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
45 { PCI_DEVICE(0x1799, 0x6001) },
46 { PCI_DEVICE(0x1799, 0x6020) },
47 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
48 { }
49};
50
51MODULE_DEVICE_TABLE(pci, rtl8180_table);
52
53static const struct ieee80211_rate rtl818x_rates[] = {
54 { .bitrate = 10, .hw_value = 0, },
55 { .bitrate = 20, .hw_value = 1, },
56 { .bitrate = 55, .hw_value = 2, },
57 { .bitrate = 110, .hw_value = 3, },
58 { .bitrate = 60, .hw_value = 4, },
59 { .bitrate = 90, .hw_value = 5, },
60 { .bitrate = 120, .hw_value = 6, },
61 { .bitrate = 180, .hw_value = 7, },
62 { .bitrate = 240, .hw_value = 8, },
63 { .bitrate = 360, .hw_value = 9, },
64 { .bitrate = 480, .hw_value = 10, },
65 { .bitrate = 540, .hw_value = 11, },
66};
67
68static const struct ieee80211_channel rtl818x_channels[] = {
69 { .center_freq = 2412 },
70 { .center_freq = 2417 },
71 { .center_freq = 2422 },
72 { .center_freq = 2427 },
73 { .center_freq = 2432 },
74 { .center_freq = 2437 },
75 { .center_freq = 2442 },
76 { .center_freq = 2447 },
77 { .center_freq = 2452 },
78 { .center_freq = 2457 },
79 { .center_freq = 2462 },
80 { .center_freq = 2467 },
81 { .center_freq = 2472 },
82 { .center_freq = 2484 },
83};
84
85
86void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
87{
88 struct rtl8180_priv *priv = dev->priv;
89 int i = 10;
90 u32 buf;
91
92 buf = (data << 8) | addr;
93
94 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
95 while (i--) {
96 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
97 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
98 return;
99 }
100}
101
102static void rtl8180_handle_rx(struct ieee80211_hw *dev)
103{
104 struct rtl8180_priv *priv = dev->priv;
105 unsigned int count = 32;
106 u8 signal, agc, sq;
107
108 while (count--) {
109 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
110 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
111 u32 flags = le32_to_cpu(entry->flags);
112
113 if (flags & RTL818X_RX_DESC_FLAG_OWN)
114 return;
115
116 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
117 RTL818X_RX_DESC_FLAG_FOF |
118 RTL818X_RX_DESC_FLAG_RX_ERR)))
119 goto done;
120 else {
121 u32 flags2 = le32_to_cpu(entry->flags2);
122 struct ieee80211_rx_status rx_status = {0};
123 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
124
125 if (unlikely(!new_skb))
126 goto done;
127
128 pci_unmap_single(priv->pdev,
129 *((dma_addr_t *)skb->cb),
130 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
131 skb_put(skb, flags & 0xFFF);
132
133 rx_status.antenna = (flags2 >> 15) & 1;
134 rx_status.rate_idx = (flags >> 20) & 0xF;
135 agc = (flags2 >> 17) & 0x7F;
136 if (priv->r8185) {
137 if (rx_status.rate_idx > 3)
138 signal = 90 - clamp_t(u8, agc, 25, 90);
139 else
140 signal = 95 - clamp_t(u8, agc, 30, 95);
141 } else {
142 sq = flags2 & 0xff;
143 signal = priv->rf->calc_rssi(agc, sq);
144 }
145 rx_status.signal = signal;
146 rx_status.freq = dev->conf.channel->center_freq;
147 rx_status.band = dev->conf.channel->band;
148 rx_status.mactime = le64_to_cpu(entry->tsft);
149 rx_status.flag |= RX_FLAG_MACTIME_MPDU;
150 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
151 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
152
153 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
154 ieee80211_rx_irqsafe(dev, skb);
155
156 skb = new_skb;
157 priv->rx_buf[priv->rx_idx] = skb;
158 *((dma_addr_t *) skb->cb) =
159 pci_map_single(priv->pdev, skb_tail_pointer(skb),
160 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
161 }
162
163 done:
164 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
165 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
166 MAX_RX_SIZE);
167 if (priv->rx_idx == 31)
168 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
169 priv->rx_idx = (priv->rx_idx + 1) % 32;
170 }
171}
172
173static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
174{
175 struct rtl8180_priv *priv = dev->priv;
176 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
177
178 while (skb_queue_len(&ring->queue)) {
179 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
180 struct sk_buff *skb;
181 struct ieee80211_tx_info *info;
182 u32 flags = le32_to_cpu(entry->flags);
183
184 if (flags & RTL818X_TX_DESC_FLAG_OWN)
185 return;
186
187 ring->idx = (ring->idx + 1) % ring->entries;
188 skb = __skb_dequeue(&ring->queue);
189 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
190 skb->len, PCI_DMA_TODEVICE);
191
192 info = IEEE80211_SKB_CB(skb);
193 ieee80211_tx_info_clear_status(info);
194
195 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
196 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
197 info->flags |= IEEE80211_TX_STAT_ACK;
198
199 info->status.rates[0].count = (flags & 0xFF) + 1;
200 info->status.rates[1].idx = -1;
201
202 ieee80211_tx_status_irqsafe(dev, skb);
203 if (ring->entries - skb_queue_len(&ring->queue) == 2)
204 ieee80211_wake_queue(dev, prio);
205 }
206}
207
208static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
209{
210 struct ieee80211_hw *dev = dev_id;
211 struct rtl8180_priv *priv = dev->priv;
212 u16 reg;
213
214 spin_lock(&priv->lock);
215 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
216 if (unlikely(reg == 0xFFFF)) {
217 spin_unlock(&priv->lock);
218 return IRQ_HANDLED;
219 }
220
221 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
222
223 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
224 rtl8180_handle_tx(dev, 3);
225
226 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
227 rtl8180_handle_tx(dev, 2);
228
229 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
230 rtl8180_handle_tx(dev, 1);
231
232 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
233 rtl8180_handle_tx(dev, 0);
234
235 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
236 rtl8180_handle_rx(dev);
237
238 spin_unlock(&priv->lock);
239
240 return IRQ_HANDLED;
241}
242
243static void rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
244{
245 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
246 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
247 struct rtl8180_priv *priv = dev->priv;
248 struct rtl8180_tx_ring *ring;
249 struct rtl8180_tx_desc *entry;
250 unsigned long flags;
251 unsigned int idx, prio;
252 dma_addr_t mapping;
253 u32 tx_flags;
254 u8 rc_flags;
255 u16 plcp_len = 0;
256 __le16 rts_duration = 0;
257
258 prio = skb_get_queue_mapping(skb);
259 ring = &priv->tx_ring[prio];
260
261 mapping = pci_map_single(priv->pdev, skb->data,
262 skb->len, PCI_DMA_TODEVICE);
263
264 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
265 RTL818X_TX_DESC_FLAG_LS |
266 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
267 skb->len;
268
269 if (priv->r8185)
270 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
271 RTL818X_TX_DESC_FLAG_NO_ENC;
272
273 rc_flags = info->control.rates[0].flags;
274 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
275 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
276 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
277 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
278 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
279 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
280 }
281
282 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
283 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
284 info);
285
286 if (!priv->r8185) {
287 unsigned int remainder;
288
289 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
290 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
291 remainder = (16 * (skb->len + 4)) %
292 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
293 if (remainder <= 6)
294 plcp_len |= 1 << 15;
295 }
296
297 spin_lock_irqsave(&priv->lock, flags);
298
299 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
300 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
301 priv->seqno += 0x10;
302 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
303 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
304 }
305
306 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
307 entry = &ring->desc[idx];
308
309 entry->rts_duration = rts_duration;
310 entry->plcp_len = cpu_to_le16(plcp_len);
311 entry->tx_buf = cpu_to_le32(mapping);
312 entry->frame_len = cpu_to_le32(skb->len);
313 entry->flags2 = info->control.rates[1].idx >= 0 ?
314 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
315 entry->retry_limit = info->control.rates[0].count;
316 entry->flags = cpu_to_le32(tx_flags);
317 __skb_queue_tail(&ring->queue, skb);
318 if (ring->entries - skb_queue_len(&ring->queue) < 2)
319 ieee80211_stop_queue(dev, prio);
320
321 spin_unlock_irqrestore(&priv->lock, flags);
322
323 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
324}
325
326void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
327{
328 u8 reg;
329
330 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
331 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
332 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
333 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
334 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
335 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
336 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
337 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
338}
339
340static int rtl8180_init_hw(struct ieee80211_hw *dev)
341{
342 struct rtl8180_priv *priv = dev->priv;
343 u16 reg;
344
345 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
346 rtl818x_ioread8(priv, &priv->map->CMD);
347 msleep(10);
348
349
350 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
351 rtl818x_ioread8(priv, &priv->map->CMD);
352
353 reg = rtl818x_ioread8(priv, &priv->map->CMD);
354 reg &= (1 << 1);
355 reg |= RTL818X_CMD_RESET;
356 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
357 rtl818x_ioread8(priv, &priv->map->CMD);
358 msleep(200);
359
360
361 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
362 wiphy_err(dev->wiphy, "reset timeout!\n");
363 return -ETIMEDOUT;
364 }
365
366 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
367 rtl818x_ioread8(priv, &priv->map->CMD);
368 msleep(200);
369
370 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
371
372 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
373 reg |= 1 << 1;
374 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
375 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
376 reg |= (1 << 15) | (1 << 14) | (1 << 4);
377 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
378 }
379
380 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
381
382 if (!priv->r8185)
383 rtl8180_set_anaparam(priv, priv->anaparam);
384
385 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
386 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
387 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
388 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
389 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
390
391
392 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
393 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
394 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
395 if (priv->r8185) {
396 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
397 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
398 }
399 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
400
401
402
403
404
405 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
406
407 if (priv->r8185) {
408 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
409 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
410 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
411
412 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
413
414
415 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
416 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
417 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
418 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
419 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
420 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
421 } else {
422 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
423 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
424
425 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
426 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
427 }
428
429 priv->rf->init(dev);
430 if (priv->r8185)
431 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
432 return 0;
433}
434
435static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
436{
437 struct rtl8180_priv *priv = dev->priv;
438 struct rtl8180_rx_desc *entry;
439 int i;
440
441 priv->rx_ring = pci_alloc_consistent(priv->pdev,
442 sizeof(*priv->rx_ring) * 32,
443 &priv->rx_ring_dma);
444
445 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
446 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
447 return -ENOMEM;
448 }
449
450 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
451 priv->rx_idx = 0;
452
453 for (i = 0; i < 32; i++) {
454 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
455 dma_addr_t *mapping;
456 entry = &priv->rx_ring[i];
457 if (!skb)
458 return 0;
459
460 priv->rx_buf[i] = skb;
461 mapping = (dma_addr_t *)skb->cb;
462 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
463 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
464 entry->rx_buf = cpu_to_le32(*mapping);
465 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
466 MAX_RX_SIZE);
467 }
468 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
469 return 0;
470}
471
472static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
473{
474 struct rtl8180_priv *priv = dev->priv;
475 int i;
476
477 for (i = 0; i < 32; i++) {
478 struct sk_buff *skb = priv->rx_buf[i];
479 if (!skb)
480 continue;
481
482 pci_unmap_single(priv->pdev,
483 *((dma_addr_t *)skb->cb),
484 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
485 kfree_skb(skb);
486 }
487
488 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
489 priv->rx_ring, priv->rx_ring_dma);
490 priv->rx_ring = NULL;
491}
492
493static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
494 unsigned int prio, unsigned int entries)
495{
496 struct rtl8180_priv *priv = dev->priv;
497 struct rtl8180_tx_desc *ring;
498 dma_addr_t dma;
499 int i;
500
501 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
502 if (!ring || (unsigned long)ring & 0xFF) {
503 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
504 prio);
505 return -ENOMEM;
506 }
507
508 memset(ring, 0, sizeof(*ring)*entries);
509 priv->tx_ring[prio].desc = ring;
510 priv->tx_ring[prio].dma = dma;
511 priv->tx_ring[prio].idx = 0;
512 priv->tx_ring[prio].entries = entries;
513 skb_queue_head_init(&priv->tx_ring[prio].queue);
514
515 for (i = 0; i < entries; i++)
516 ring[i].next_tx_desc =
517 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
518
519 return 0;
520}
521
522static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
523{
524 struct rtl8180_priv *priv = dev->priv;
525 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
526
527 while (skb_queue_len(&ring->queue)) {
528 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
529 struct sk_buff *skb = __skb_dequeue(&ring->queue);
530
531 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
532 skb->len, PCI_DMA_TODEVICE);
533 kfree_skb(skb);
534 ring->idx = (ring->idx + 1) % ring->entries;
535 }
536
537 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
538 ring->desc, ring->dma);
539 ring->desc = NULL;
540}
541
542static int rtl8180_start(struct ieee80211_hw *dev)
543{
544 struct rtl8180_priv *priv = dev->priv;
545 int ret, i;
546 u32 reg;
547
548 ret = rtl8180_init_rx_ring(dev);
549 if (ret)
550 return ret;
551
552 for (i = 0; i < 4; i++)
553 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
554 goto err_free_rings;
555
556 ret = rtl8180_init_hw(dev);
557 if (ret)
558 goto err_free_rings;
559
560 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
561 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
562 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
563 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
564 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
565
566 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
567 IRQF_SHARED, KBUILD_MODNAME, dev);
568 if (ret) {
569 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
570 goto err_free_rings;
571 }
572
573 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
574
575 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
576 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
577
578 reg = RTL818X_RX_CONF_ONLYERLPKT |
579 RTL818X_RX_CONF_RX_AUTORESETPHY |
580 RTL818X_RX_CONF_MGMT |
581 RTL818X_RX_CONF_DATA |
582 (7 << 8 ) |
583 RTL818X_RX_CONF_BROADCAST |
584 RTL818X_RX_CONF_NICMAC;
585
586 if (priv->r8185)
587 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
588 else {
589 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
590 ? RTL818X_RX_CONF_CSDM1 : 0;
591 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
592 ? RTL818X_RX_CONF_CSDM2 : 0;
593 }
594
595 priv->rx_conf = reg;
596 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
597
598 if (priv->r8185) {
599 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
600 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
601 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
602 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
603
604 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
605 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
606 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
607 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
608 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
609
610
611 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
612 }
613
614 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
615 reg |= (6 << 21 ) |
616 RTL818X_TX_CONF_NO_ICV;
617
618 if (priv->r8185)
619 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
620 else
621 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
622
623
624 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
625
626 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
627
628 reg = rtl818x_ioread8(priv, &priv->map->CMD);
629 reg |= RTL818X_CMD_RX_ENABLE;
630 reg |= RTL818X_CMD_TX_ENABLE;
631 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
632
633 return 0;
634
635 err_free_rings:
636 rtl8180_free_rx_ring(dev);
637 for (i = 0; i < 4; i++)
638 if (priv->tx_ring[i].desc)
639 rtl8180_free_tx_ring(dev, i);
640
641 return ret;
642}
643
644static void rtl8180_stop(struct ieee80211_hw *dev)
645{
646 struct rtl8180_priv *priv = dev->priv;
647 u8 reg;
648 int i;
649
650 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
651
652 reg = rtl818x_ioread8(priv, &priv->map->CMD);
653 reg &= ~RTL818X_CMD_TX_ENABLE;
654 reg &= ~RTL818X_CMD_RX_ENABLE;
655 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
656
657 priv->rf->stop(dev);
658
659 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
660 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
661 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
662 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
663
664 free_irq(priv->pdev->irq, dev);
665
666 rtl8180_free_rx_ring(dev);
667 for (i = 0; i < 4; i++)
668 rtl8180_free_tx_ring(dev, i);
669}
670
671static u64 rtl8180_get_tsf(struct ieee80211_hw *dev)
672{
673 struct rtl8180_priv *priv = dev->priv;
674
675 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
676 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
677}
678
679static void rtl8180_beacon_work(struct work_struct *work)
680{
681 struct rtl8180_vif *vif_priv =
682 container_of(work, struct rtl8180_vif, beacon_work.work);
683 struct ieee80211_vif *vif =
684 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
685 struct ieee80211_hw *dev = vif_priv->dev;
686 struct ieee80211_mgmt *mgmt;
687 struct sk_buff *skb;
688
689
690 if (ieee80211_queue_stopped(dev, 0))
691 goto resched;
692
693
694 skb = ieee80211_beacon_get(dev, vif);
695 if (!skb)
696 goto resched;
697
698
699
700
701
702 mgmt = (struct ieee80211_mgmt *)skb->data;
703 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev));
704
705
706 skb_set_queue_mapping(skb, 0);
707
708 rtl8180_tx(dev, skb);
709
710resched:
711
712
713
714
715 schedule_delayed_work(&vif_priv->beacon_work,
716 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
717}
718
719static int rtl8180_add_interface(struct ieee80211_hw *dev,
720 struct ieee80211_vif *vif)
721{
722 struct rtl8180_priv *priv = dev->priv;
723 struct rtl8180_vif *vif_priv;
724
725
726
727
728 if (priv->vif)
729 return -EBUSY;
730
731 switch (vif->type) {
732 case NL80211_IFTYPE_STATION:
733 case NL80211_IFTYPE_ADHOC:
734 break;
735 default:
736 return -EOPNOTSUPP;
737 }
738
739 priv->vif = vif;
740
741
742 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
743 vif_priv->dev = dev;
744 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
745 vif_priv->enable_beacon = false;
746
747 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
748 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
749 le32_to_cpu(*(__le32 *)vif->addr));
750 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
751 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
752 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
753
754 return 0;
755}
756
757static void rtl8180_remove_interface(struct ieee80211_hw *dev,
758 struct ieee80211_vif *vif)
759{
760 struct rtl8180_priv *priv = dev->priv;
761 priv->vif = NULL;
762}
763
764static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
765{
766 struct rtl8180_priv *priv = dev->priv;
767 struct ieee80211_conf *conf = &dev->conf;
768
769 priv->rf->set_chan(dev, conf);
770
771 return 0;
772}
773
774static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
775 struct ieee80211_vif *vif,
776 struct ieee80211_bss_conf *info,
777 u32 changed)
778{
779 struct rtl8180_priv *priv = dev->priv;
780 struct rtl8180_vif *vif_priv;
781 int i;
782 u8 reg;
783
784 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
785
786 if (changed & BSS_CHANGED_BSSID) {
787 for (i = 0; i < ETH_ALEN; i++)
788 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
789 info->bssid[i]);
790
791 if (is_valid_ether_addr(info->bssid)) {
792 if (vif->type == NL80211_IFTYPE_ADHOC)
793 reg = RTL818X_MSR_ADHOC;
794 else
795 reg = RTL818X_MSR_INFRA;
796 } else
797 reg = RTL818X_MSR_NO_LINK;
798 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
799 }
800
801 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
802 priv->rf->conf_erp(dev, info);
803
804 if (changed & BSS_CHANGED_BEACON_ENABLED)
805 vif_priv->enable_beacon = info->enable_beacon;
806
807 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
808 cancel_delayed_work_sync(&vif_priv->beacon_work);
809 if (vif_priv->enable_beacon)
810 schedule_work(&vif_priv->beacon_work.work);
811 }
812}
813
814static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
815 struct netdev_hw_addr_list *mc_list)
816{
817 return netdev_hw_addr_list_count(mc_list);
818}
819
820static void rtl8180_configure_filter(struct ieee80211_hw *dev,
821 unsigned int changed_flags,
822 unsigned int *total_flags,
823 u64 multicast)
824{
825 struct rtl8180_priv *priv = dev->priv;
826
827 if (changed_flags & FIF_FCSFAIL)
828 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
829 if (changed_flags & FIF_CONTROL)
830 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
831 if (changed_flags & FIF_OTHER_BSS)
832 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
833 if (*total_flags & FIF_ALLMULTI || multicast > 0)
834 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
835 else
836 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
837
838 *total_flags = 0;
839
840 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
841 *total_flags |= FIF_FCSFAIL;
842 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
843 *total_flags |= FIF_CONTROL;
844 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
845 *total_flags |= FIF_OTHER_BSS;
846 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
847 *total_flags |= FIF_ALLMULTI;
848
849 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
850}
851
852static const struct ieee80211_ops rtl8180_ops = {
853 .tx = rtl8180_tx,
854 .start = rtl8180_start,
855 .stop = rtl8180_stop,
856 .add_interface = rtl8180_add_interface,
857 .remove_interface = rtl8180_remove_interface,
858 .config = rtl8180_config,
859 .bss_info_changed = rtl8180_bss_info_changed,
860 .prepare_multicast = rtl8180_prepare_multicast,
861 .configure_filter = rtl8180_configure_filter,
862 .get_tsf = rtl8180_get_tsf,
863};
864
865static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
866{
867 struct ieee80211_hw *dev = eeprom->data;
868 struct rtl8180_priv *priv = dev->priv;
869 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
870
871 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
872 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
873 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
874 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
875}
876
877static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
878{
879 struct ieee80211_hw *dev = eeprom->data;
880 struct rtl8180_priv *priv = dev->priv;
881 u8 reg = 2 << 6;
882
883 if (eeprom->reg_data_in)
884 reg |= RTL818X_EEPROM_CMD_WRITE;
885 if (eeprom->reg_data_out)
886 reg |= RTL818X_EEPROM_CMD_READ;
887 if (eeprom->reg_data_clock)
888 reg |= RTL818X_EEPROM_CMD_CK;
889 if (eeprom->reg_chip_select)
890 reg |= RTL818X_EEPROM_CMD_CS;
891
892 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
893 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
894 udelay(10);
895}
896
897static int __devinit rtl8180_probe(struct pci_dev *pdev,
898 const struct pci_device_id *id)
899{
900 struct ieee80211_hw *dev;
901 struct rtl8180_priv *priv;
902 unsigned long mem_addr, mem_len;
903 unsigned int io_addr, io_len;
904 int err, i;
905 struct eeprom_93cx6 eeprom;
906 const char *chip_name, *rf_name = NULL;
907 u32 reg;
908 u16 eeprom_val;
909 u8 mac_addr[ETH_ALEN];
910
911 err = pci_enable_device(pdev);
912 if (err) {
913 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
914 pci_name(pdev));
915 return err;
916 }
917
918 err = pci_request_regions(pdev, KBUILD_MODNAME);
919 if (err) {
920 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
921 pci_name(pdev));
922 return err;
923 }
924
925 io_addr = pci_resource_start(pdev, 0);
926 io_len = pci_resource_len(pdev, 0);
927 mem_addr = pci_resource_start(pdev, 1);
928 mem_len = pci_resource_len(pdev, 1);
929
930 if (mem_len < sizeof(struct rtl818x_csr) ||
931 io_len < sizeof(struct rtl818x_csr)) {
932 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
933 pci_name(pdev));
934 err = -ENOMEM;
935 goto err_free_reg;
936 }
937
938 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
939 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
940 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
941 pci_name(pdev));
942 goto err_free_reg;
943 }
944
945 pci_set_master(pdev);
946
947 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
948 if (!dev) {
949 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
950 pci_name(pdev));
951 err = -ENOMEM;
952 goto err_free_reg;
953 }
954
955 priv = dev->priv;
956 priv->pdev = pdev;
957
958 dev->max_rates = 2;
959 SET_IEEE80211_DEV(dev, &pdev->dev);
960 pci_set_drvdata(pdev, dev);
961
962 priv->map = pci_iomap(pdev, 1, mem_len);
963 if (!priv->map)
964 priv->map = pci_iomap(pdev, 0, io_len);
965
966 if (!priv->map) {
967 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
968 pci_name(pdev));
969 goto err_free_dev;
970 }
971
972 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
973 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
974
975 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
976 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
977
978 priv->band.band = IEEE80211_BAND_2GHZ;
979 priv->band.channels = priv->channels;
980 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
981 priv->band.bitrates = priv->rates;
982 priv->band.n_bitrates = 4;
983 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
984
985 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
986 IEEE80211_HW_RX_INCLUDES_FCS |
987 IEEE80211_HW_SIGNAL_UNSPEC;
988 dev->vif_data_size = sizeof(struct rtl8180_vif);
989 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
990 BIT(NL80211_IFTYPE_ADHOC);
991 dev->queues = 1;
992 dev->max_signal = 65;
993
994 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
995 reg &= RTL818X_TX_CONF_HWVER_MASK;
996 switch (reg) {
997 case RTL818X_TX_CONF_R8180_ABCD:
998 chip_name = "RTL8180";
999 break;
1000 case RTL818X_TX_CONF_R8180_F:
1001 chip_name = "RTL8180vF";
1002 break;
1003 case RTL818X_TX_CONF_R8185_ABC:
1004 chip_name = "RTL8185";
1005 break;
1006 case RTL818X_TX_CONF_R8185_D:
1007 chip_name = "RTL8185vD";
1008 break;
1009 default:
1010 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1011 pci_name(pdev), reg >> 25);
1012 goto err_iounmap;
1013 }
1014
1015 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1016 if (priv->r8185) {
1017 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1018 pci_try_set_mwi(pdev);
1019 }
1020
1021 eeprom.data = dev;
1022 eeprom.register_read = rtl8180_eeprom_register_read;
1023 eeprom.register_write = rtl8180_eeprom_register_write;
1024 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1025 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1026 else
1027 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1028
1029 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1030 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1031 udelay(10);
1032
1033 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1034 eeprom_val &= 0xFF;
1035 switch (eeprom_val) {
1036 case 1: rf_name = "Intersil";
1037 break;
1038 case 2: rf_name = "RFMD";
1039 break;
1040 case 3: priv->rf = &sa2400_rf_ops;
1041 break;
1042 case 4: priv->rf = &max2820_rf_ops;
1043 break;
1044 case 5: priv->rf = &grf5101_rf_ops;
1045 break;
1046 case 9: priv->rf = rtl8180_detect_rf(dev);
1047 break;
1048 case 10:
1049 rf_name = "RTL8255";
1050 break;
1051 default:
1052 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1053 pci_name(pdev), eeprom_val);
1054 goto err_iounmap;
1055 }
1056
1057 if (!priv->rf) {
1058 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1059 pci_name(pdev), rf_name);
1060 goto err_iounmap;
1061 }
1062
1063 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1064 priv->csthreshold = eeprom_val >> 8;
1065 if (!priv->r8185) {
1066 __le32 anaparam;
1067 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1068 priv->anaparam = le32_to_cpu(anaparam);
1069 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1070 }
1071
1072 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1073 if (!is_valid_ether_addr(mac_addr)) {
1074 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1075 " randomly generated MAC addr\n", pci_name(pdev));
1076 random_ether_addr(mac_addr);
1077 }
1078 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1079
1080
1081 for (i = 0; i < 14; i += 2) {
1082 u16 txpwr;
1083 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1084 priv->channels[i].hw_value = txpwr & 0xFF;
1085 priv->channels[i + 1].hw_value = txpwr >> 8;
1086 }
1087
1088
1089 if (priv->r8185) {
1090 for (i = 0; i < 14; i += 2) {
1091 u16 txpwr;
1092 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1093 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1094 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1095 }
1096 }
1097
1098 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1099
1100 spin_lock_init(&priv->lock);
1101
1102 err = ieee80211_register_hw(dev);
1103 if (err) {
1104 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1105 pci_name(pdev));
1106 goto err_iounmap;
1107 }
1108
1109 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1110 mac_addr, chip_name, priv->rf->name);
1111
1112 return 0;
1113
1114 err_iounmap:
1115 iounmap(priv->map);
1116
1117 err_free_dev:
1118 pci_set_drvdata(pdev, NULL);
1119 ieee80211_free_hw(dev);
1120
1121 err_free_reg:
1122 pci_release_regions(pdev);
1123 pci_disable_device(pdev);
1124 return err;
1125}
1126
1127static void __devexit rtl8180_remove(struct pci_dev *pdev)
1128{
1129 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1130 struct rtl8180_priv *priv;
1131
1132 if (!dev)
1133 return;
1134
1135 ieee80211_unregister_hw(dev);
1136
1137 priv = dev->priv;
1138
1139 pci_iounmap(pdev, priv->map);
1140 pci_release_regions(pdev);
1141 pci_disable_device(pdev);
1142 ieee80211_free_hw(dev);
1143}
1144
1145#ifdef CONFIG_PM
1146static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1147{
1148 pci_save_state(pdev);
1149 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1150 return 0;
1151}
1152
1153static int rtl8180_resume(struct pci_dev *pdev)
1154{
1155 pci_set_power_state(pdev, PCI_D0);
1156 pci_restore_state(pdev);
1157 return 0;
1158}
1159
1160#endif
1161
1162static struct pci_driver rtl8180_driver = {
1163 .name = KBUILD_MODNAME,
1164 .id_table = rtl8180_table,
1165 .probe = rtl8180_probe,
1166 .remove = __devexit_p(rtl8180_remove),
1167#ifdef CONFIG_PM
1168 .suspend = rtl8180_suspend,
1169 .resume = rtl8180_resume,
1170#endif
1171};
1172
1173static int __init rtl8180_init(void)
1174{
1175 return pci_register_driver(&rtl8180_driver);
1176}
1177
1178static void __exit rtl8180_exit(void)
1179{
1180 pci_unregister_driver(&rtl8180_driver);
1181}
1182
1183module_init(rtl8180_init);
1184module_exit(rtl8180_exit);
1185
