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18#ifndef __BFA_DEFS_H__
19#define __BFA_DEFS_H__
20
21#include "bfa_fc.h"
22#include "bfad_drv.h"
23
24#define BFA_MFG_SERIALNUM_SIZE 11
25#define STRSZ(_n) (((_n) + 4) & ~3)
26
27
28
29
30enum {
31 BFA_MFG_TYPE_CB_MAX = 825,
32 BFA_MFG_TYPE_FC8P2 = 825,
33 BFA_MFG_TYPE_FC8P1 = 815,
34 BFA_MFG_TYPE_FC4P2 = 425,
35 BFA_MFG_TYPE_FC4P1 = 415,
36 BFA_MFG_TYPE_CNA10P2 = 1020,
37 BFA_MFG_TYPE_CNA10P1 = 1010,
38 BFA_MFG_TYPE_JAYHAWK = 804,
39 BFA_MFG_TYPE_WANCHESE = 1007,
40 BFA_MFG_TYPE_ASTRA = 807,
41 BFA_MFG_TYPE_LIGHTNING_P0 = 902,
42 BFA_MFG_TYPE_LIGHTNING = 1741,
43 BFA_MFG_TYPE_INVALID = 0,
44};
45
46#pragma pack(1)
47
48
49
50
51#define bfa_mfg_is_mezz(type) (( \
52 (type) == BFA_MFG_TYPE_JAYHAWK || \
53 (type) == BFA_MFG_TYPE_WANCHESE || \
54 (type) == BFA_MFG_TYPE_ASTRA || \
55 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
56 (type) == BFA_MFG_TYPE_LIGHTNING))
57
58
59
60
61#define bfa_mfg_is_old_wwn_mac_model(type) (( \
62 (type) == BFA_MFG_TYPE_FC8P2 || \
63 (type) == BFA_MFG_TYPE_FC8P1 || \
64 (type) == BFA_MFG_TYPE_FC4P2 || \
65 (type) == BFA_MFG_TYPE_FC4P1 || \
66 (type) == BFA_MFG_TYPE_CNA10P2 || \
67 (type) == BFA_MFG_TYPE_CNA10P1 || \
68 (type) == BFA_MFG_TYPE_JAYHAWK || \
69 (type) == BFA_MFG_TYPE_WANCHESE))
70
71#define bfa_mfg_increment_wwn_mac(m, i) \
72do { \
73 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
74 (u32)(m)[2]; \
75 t += (i); \
76 (m)[0] = (t >> 16) & 0xFF; \
77 (m)[1] = (t >> 8) & 0xFF; \
78 (m)[2] = t & 0xFF; \
79} while (0)
80
81
82
83
84#define BFA_MFG_VPD_LEN 512
85
86
87
88
89enum {
90 BFA_MFG_VPD_UNKNOWN = 0,
91 BFA_MFG_VPD_IBM = 1,
92 BFA_MFG_VPD_HP = 2,
93 BFA_MFG_VPD_DELL = 3,
94 BFA_MFG_VPD_PCI_IBM = 0x08,
95 BFA_MFG_VPD_PCI_HP = 0x10,
96 BFA_MFG_VPD_PCI_DELL = 0x20,
97 BFA_MFG_VPD_PCI_BRCD = 0xf8,
98};
99
100
101
102
103struct bfa_mfg_vpd_s {
104 u8 version;
105 u8 vpd_sig[3];
106 u8 chksum;
107 u8 vendor;
108 u8 len;
109 u8 rsv;
110 u8 data[BFA_MFG_VPD_LEN];
111};
112
113#pragma pack()
114
115
116
117
118enum bfa_status {
119 BFA_STATUS_OK = 0,
120 BFA_STATUS_FAILED = 1,
121 BFA_STATUS_EINVAL = 2,
122
123 BFA_STATUS_ENOMEM = 3,
124 BFA_STATUS_ETIMER = 5,
125
126 BFA_STATUS_EPROTOCOL = 6,
127 BFA_STATUS_DEVBUSY = 13,
128 BFA_STATUS_UNKNOWN_LWWN = 18,
129 BFA_STATUS_UNKNOWN_RWWN = 19,
130 BFA_STATUS_VPORT_EXISTS = 21,
131 BFA_STATUS_VPORT_MAX = 22,
132 BFA_STATUS_UNSUPP_SPEED = 23,
133 BFA_STATUS_INVLD_DFSZ = 24,
134 BFA_STATUS_FABRIC_RJT = 29,
135 BFA_STATUS_VPORT_WWN_BP = 46,
136 BFA_STATUS_NO_FCPIM_NEXUS = 52,
137 BFA_STATUS_IOC_FAILURE = 56,
138
139 BFA_STATUS_INVALID_WWN = 57,
140 BFA_STATUS_DIAG_BUSY = 71,
141 BFA_STATUS_ENOFSAVE = 78,
142 BFA_STATUS_IOC_DISABLED = 82,
143 BFA_STATUS_INVALID_MAC = 134,
144 BFA_STATUS_PBC = 154,
145
146 BFA_STATUS_TRUNK_ENABLED = 164,
147
148 BFA_STATUS_TRUNK_DISABLED = 165,
149
150 BFA_STATUS_IOPROFILE_OFF = 175,
151 BFA_STATUS_MAX_VAL
152};
153#define bfa_status_t enum bfa_status
154
155enum bfa_eproto_status {
156 BFA_EPROTO_BAD_ACCEPT = 0,
157 BFA_EPROTO_UNKNOWN_RSP = 1
158};
159#define bfa_eproto_status_t enum bfa_eproto_status
160
161enum bfa_boolean {
162 BFA_FALSE = 0,
163 BFA_TRUE = 1
164};
165#define bfa_boolean_t enum bfa_boolean
166
167#define BFA_STRING_32 32
168#define BFA_VERSION_LEN 64
169
170
171
172
173
174
175
176
177enum {
178 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
179
180
181
182 BFA_ADAPTER_MODEL_NAME_LEN = 16,
183 BFA_ADAPTER_MODEL_DESCR_LEN = 128,
184 BFA_ADAPTER_MFG_NAME_LEN = 8,
185 BFA_ADAPTER_SYM_NAME_LEN = 64,
186 BFA_ADAPTER_OS_TYPE_LEN = 64,
187};
188
189struct bfa_adapter_attr_s {
190 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
191 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
192 u32 card_type;
193 char model[BFA_ADAPTER_MODEL_NAME_LEN];
194 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
195 wwn_t pwwn;
196 char node_symname[FC_SYMNAME_MAX];
197 char hw_ver[BFA_VERSION_LEN];
198 char fw_ver[BFA_VERSION_LEN];
199 char optrom_ver[BFA_VERSION_LEN];
200 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
201 struct bfa_mfg_vpd_s vpd;
202 struct mac_s mac;
203
204 u8 nports;
205 u8 max_speed;
206 u8 prototype;
207 char asic_rev;
208
209 u8 pcie_gen;
210 u8 pcie_lanes_orig;
211 u8 pcie_lanes;
212 u8 cna_capable;
213
214 u8 is_mezz;
215 u8 trunk_capable;
216};
217
218
219
220
221
222enum {
223 BFA_IOC_DRIVER_LEN = 16,
224 BFA_IOC_CHIP_REV_LEN = 8,
225};
226
227
228
229
230struct bfa_ioc_driver_attr_s {
231 char driver[BFA_IOC_DRIVER_LEN];
232 char driver_ver[BFA_VERSION_LEN];
233 char fw_ver[BFA_VERSION_LEN];
234 char bios_ver[BFA_VERSION_LEN];
235 char efi_ver[BFA_VERSION_LEN];
236 char ob_ver[BFA_VERSION_LEN];
237};
238
239
240
241
242struct bfa_ioc_pci_attr_s {
243 u16 vendor_id;
244 u16 device_id;
245 u16 ssid;
246 u16 ssvid;
247 u32 pcifn;
248 u32 rsvd;
249 char chip_rev[BFA_IOC_CHIP_REV_LEN];
250};
251
252
253
254
255enum bfa_ioc_state {
256 BFA_IOC_UNINIT = 1,
257 BFA_IOC_RESET = 2,
258 BFA_IOC_SEMWAIT = 3,
259 BFA_IOC_HWINIT = 4,
260 BFA_IOC_GETATTR = 5,
261 BFA_IOC_OPERATIONAL = 6,
262 BFA_IOC_INITFAIL = 7,
263 BFA_IOC_FAIL = 8,
264 BFA_IOC_DISABLING = 9,
265 BFA_IOC_DISABLED = 10,
266 BFA_IOC_FWMISMATCH = 11,
267 BFA_IOC_ENABLING = 12,
268};
269
270
271
272
273struct bfa_fw_ioc_stats_s {
274 u32 enable_reqs;
275 u32 disable_reqs;
276 u32 get_attr_reqs;
277 u32 dbg_sync;
278 u32 dbg_dump;
279 u32 unknown_reqs;
280};
281
282
283
284
285struct bfa_ioc_drv_stats_s {
286 u32 ioc_isrs;
287 u32 ioc_enables;
288 u32 ioc_disables;
289 u32 ioc_hbfails;
290 u32 ioc_boots;
291 u32 stats_tmos;
292 u32 hb_count;
293 u32 disable_reqs;
294 u32 enable_reqs;
295 u32 disable_replies;
296 u32 enable_replies;
297};
298
299
300
301
302struct bfa_ioc_stats_s {
303 struct bfa_ioc_drv_stats_s drv_stats;
304 struct bfa_fw_ioc_stats_s fw_stats;
305};
306
307enum bfa_ioc_type_e {
308 BFA_IOC_TYPE_FC = 1,
309 BFA_IOC_TYPE_FCoE = 2,
310 BFA_IOC_TYPE_LL = 3,
311};
312
313
314
315
316struct bfa_ioc_attr_s {
317 enum bfa_ioc_type_e ioc_type;
318 enum bfa_ioc_state state;
319 struct bfa_adapter_attr_s adapter_attr;
320 struct bfa_ioc_driver_attr_s driver_attr;
321 struct bfa_ioc_pci_attr_s pci_attr;
322 u8 port_id;
323 u8 rsvd[7];
324};
325
326
327
328
329
330
331
332
333#define BFA_MFG_CHKSUM_SIZE 16
334
335#define BFA_MFG_PARTNUM_SIZE 14
336#define BFA_MFG_SUPPLIER_ID_SIZE 10
337#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
338#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
339#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
340
341#pragma pack(1)
342
343
344
345
346struct bfa_mfg_block_s {
347 u8 version;
348 u8 mfg_sig[3];
349 u16 mfgsize;
350 u16 u16_chksum;
351 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
352 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
353 u8 mfg_day;
354 u8 mfg_month;
355 u16 mfg_year;
356 wwn_t mfg_wwn;
357 u8 num_wwn;
358 u8 mfg_speeds;
359 u8 rsv[2];
360 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
361 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
362 char
363 supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
364 char
365 supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
366 mac_t mfg_mac;
367 u8 num_mac;
368 u8 rsv2;
369 u32 mfg_type;
370 u8 rsv3[108];
371 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE];
372};
373
374#pragma pack()
375
376
377
378
379
380
381
382
383enum {
384 BFA_PCI_VENDOR_ID_BROCADE = 0x1657,
385 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13,
386 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
387 BFA_PCI_DEVICE_ID_CT = 0x14,
388 BFA_PCI_DEVICE_ID_CT_FC = 0x21,
389};
390
391#define bfa_asic_id_ct(devid) \
392 ((devid) == BFA_PCI_DEVICE_ID_CT || \
393 (devid) == BFA_PCI_DEVICE_ID_CT_FC)
394
395
396
397
398enum {
399 BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
400};
401
402
403
404
405#define BFA_PCI_ACCESS_RANGES 1
406
407
408
409
410
411enum bfa_port_speed {
412 BFA_PORT_SPEED_UNKNOWN = 0,
413 BFA_PORT_SPEED_1GBPS = 1,
414 BFA_PORT_SPEED_2GBPS = 2,
415 BFA_PORT_SPEED_4GBPS = 4,
416 BFA_PORT_SPEED_8GBPS = 8,
417 BFA_PORT_SPEED_10GBPS = 10,
418 BFA_PORT_SPEED_16GBPS = 16,
419 BFA_PORT_SPEED_AUTO =
420 (BFA_PORT_SPEED_1GBPS | BFA_PORT_SPEED_2GBPS |
421 BFA_PORT_SPEED_4GBPS | BFA_PORT_SPEED_8GBPS),
422};
423#define bfa_port_speed_t enum bfa_port_speed
424
425enum {
426 BFA_BOOT_BOOTLUN_MAX = 4,
427 BFA_PREBOOT_BOOTLUN_MAX = 8,
428};
429
430#define BOOT_CFG_REV1 1
431#define BOOT_CFG_VLAN 1
432
433
434
435
436
437enum bfa_boot_bootopt {
438 BFA_BOOT_AUTO_DISCOVER = 0,
439 BFA_BOOT_STORED_BLUN = 1,
440 BFA_BOOT_FIRST_LUN = 2,
441 BFA_BOOT_PBC = 3,
442};
443
444#pragma pack(1)
445
446
447
448struct bfa_boot_bootlun_s {
449 wwn_t pwwn;
450 struct scsi_lun lun;
451};
452#pragma pack()
453
454
455
456
457struct bfa_boot_pbc_s {
458 u8 enable;
459 u8 speed;
460 u8 topology;
461 u8 rsvd1;
462 u32 nbluns;
463 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX];
464};
465
466#endif
467