LXR linux/drivers/spi/dw

   1#ifndef DW_SPI_HEADER_H
   2#define DW_SPI_HEADER_H
   3
   4#include <linux/io.h>
   5#include <linux/scatterlist.h>
   6
   7/* Bit fields in CTRLR0 */
   8#define SPI_DFS_OFFSET                  0
   9
  10#define SPI_FRF_OFFSET                  4
  11#define SPI_FRF_SPI                     0x0
  12#define SPI_FRF_SSP                     0x1
  13#define SPI_FRF_MICROWIRE               0x2
  14#define SPI_FRF_RESV                    0x3
  15
  16#define SPI_MODE_OFFSET                 6
  17#define SPI_SCPH_OFFSET                 6
  18#define SPI_SCOL_OFFSET                 7
  19
  20#define SPI_TMOD_OFFSET                 8
  21#define SPI_TMOD_MASK                   (0x3 << SPI_TMOD_OFFSET)
  22#define SPI_TMOD_TR                     0x0             /* xmit & recv */
  23#define SPI_TMOD_TO                     0x1             /* xmit only */
  24#define SPI_TMOD_RO                     0x2             /* recv only */
  25#define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  26
  27#define SPI_SLVOE_OFFSET                10
  28#define SPI_SRL_OFFSET                  11
  29#define SPI_CFS_OFFSET                  12
  30
  31/* Bit fields in SR, 7 bits */
  32#define SR_MASK                         0x7f            /* cover 7 bits */
  33#define SR_BUSY                         (1 << 0)
  34#define SR_TF_NOT_FULL                  (1 << 1)
  35#define SR_TF_EMPT                      (1 << 2)
  36#define SR_RF_NOT_EMPT                  (1 << 3)
  37#define SR_RF_FULL                      (1 << 4)
  38#define SR_TX_ERR                       (1 << 5)
  39#define SR_DCOL                         (1 << 6)
  40
  41/* Bit fields in ISR, IMR, RISR, 7 bits */
  42#define SPI_INT_TXEI                    (1 << 0)
  43#define SPI_INT_TXOI                    (1 << 1)
  44#define SPI_INT_RXUI                    (1 << 2)
  45#define SPI_INT_RXOI                    (1 << 3)
  46#define SPI_INT_RXFI                    (1 << 4)
  47#define SPI_INT_MSTI                    (1 << 5)
  48
  49/* TX RX interrupt level threshold, max can be 256 */
  50#define SPI_INT_THRESHOLD               32
  51
  52enum dw_ssi_type {
  53        SSI_MOTO_SPI = 0,
  54        SSI_TI_SSP,
  55        SSI_NS_MICROWIRE,
  56};
  57
  58struct dw_spi_reg {
  59        u32     ctrl0;
  60        u32     ctrl1;
  61        u32     ssienr;
  62        u32     mwcr;
  63        u32     ser;
  64        u32     baudr;
  65        u32     txfltr;
  66        u32     rxfltr;
  67        u32     txflr;
  68        u32     rxflr;
  69        u32     sr;
  70        u32     imr;
  71        u32     isr;
  72        u32     risr;
  73        u32     txoicr;
  74        u32     rxoicr;
  75        u32     rxuicr;
  76        u32     msticr;
  77        u32     icr;
  78        u32     dmacr;
  79        u32     dmatdlr;
  80        u32     dmardlr;
  81        u32     idr;
  82        u32     version;
  83        u32     dr;             /* Currently oper as 32 bits,
  84                                though only low 16 bits matters */
  85} __packed;
  86
  87struct dw_spi;
  88struct dw_spi_dma_ops {
  89        int (*dma_init)(struct dw_spi *dws);
  90        void (*dma_exit)(struct dw_spi *dws);
  91        int (*dma_transfer)(struct dw_spi *dws, int cs_change);
  92};
  93
  94struct dw_spi {
  95        struct spi_master       *master;
  96        struct spi_device       *cur_dev;
  97        struct device           *parent_dev;
  98        enum dw_ssi_type        type;
  99
 100        void __iomem            *regs;
 101        unsigned long           paddr;
 102        u32                     iolen;
 103        int                     irq;
 104        u32                     fifo_len;       /* depth of the FIFO buffer */
 105        u32                     max_freq;       /* max bus freq supported */
 106
 107        u16                     bus_num;
 108        u16                     num_cs;         /* supported slave numbers */
 109
 110        /* Driver message queue */
 111        struct workqueue_struct *workqueue;
 112        struct work_struct      pump_messages;
 113        spinlock_t              lock;
 114        struct list_head        queue;
 115        int                     busy;
 116        int                     run;
 117
 118        /* Message Transfer pump */
 119        struct tasklet_struct   pump_transfers;
 120
 121        /* Current message transfer state info */
 122        struct spi_message      *cur_msg;
 123        struct spi_transfer     *cur_transfer;
 124        struct chip_data        *cur_chip;
 125        struct chip_data        *prev_chip;
 126        size_t                  len;
 127        void                    *tx;
 128        void                    *tx_end;
 129        void                    *rx;
 130        void                    *rx_end;
 131        int                     dma_mapped;
 132        dma_addr_t              rx_dma;
 133        dma_addr_t              tx_dma;
 134        size_t                  rx_map_len;
 135        size_t                  tx_map_len;
 136        u8                      n_bytes;        /* current is a 1/2 bytes op */
 137        u8                      max_bits_per_word;      /* maxim is 16b */
 138        u32                     dma_width;
 139        int                     cs_change;
 140        irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 141        void                    (*cs_control)(u32 command);
 142
 143        /* Dma info */
 144        int                     dma_inited;
 145        struct dma_chan         *txchan;
 146        struct scatterlist      tx_sgl;
 147        struct dma_chan         *rxchan;
 148        struct scatterlist      rx_sgl;
 149        int                     dma_chan_done;
 150        struct device           *dma_dev;
 151        dma_addr_t              dma_addr; /* phy address of the Data register */
 152        struct dw_spi_dma_ops   *dma_ops;
 153        void                    *dma_priv; /* platform relate info */
 154        struct pci_dev          *dmac;
 155
 156        /* Bus interface info */
 157        void                    *priv;
 158#ifdef CONFIG_DEBUG_FS
 159        struct dentry *debugfs;
 160#endif
 161};
 162
 163#define dw_readl(dw, name) \
 164        __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
 165#define dw_writel(dw, name, val) \
 166        __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
 167#define dw_readw(dw, name) \
 168        __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
 169#define dw_writew(dw, name, val) \
 170        __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
 171
 172static inline void spi_enable_chip(struct dw_spi *dws, int enable)
 173{
 174        dw_writel(dws, ssienr, (enable ? 1 : 0));
 175}
 176
 177static inline void spi_set_clk(struct dw_spi *dws, u16 div)
 178{
 179        dw_writel(dws, baudr, div);
 180}
 181
 182static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
 183{
 184        if (cs > dws->num_cs)
 185                return;
 186
 187        if (dws->cs_control)
 188                dws->cs_control(1);
 189
 190        dw_writel(dws, ser, 1 << cs);
 191}
 192
 193/* Disable IRQ bits */
 194static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
 195{
 196        u32 new_mask;
 197
 198        new_mask = dw_readl(dws, imr) & ~mask;
 199        dw_writel(dws, imr, new_mask);
 200}
 201
 202/* Enable IRQ bits */
 203static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
 204{
 205        u32 new_mask;
 206
 207        new_mask = dw_readl(dws, imr) | mask;
 208        dw_writel(dws, imr, new_mask);
 209}
 210
 211/*
 212 * Each SPI slave device to work with dw_api controller should
 213 * has such a structure claiming its working mode (PIO/DMA etc),
 214 * which can be save in the "controller_data" member of the
 215 * struct spi_device
 216 */
 217struct dw_spi_chip {
 218        u8 poll_mode;   /* 0 for contoller polling mode */
 219        u8 type;        /* SPI/SSP/Micrwire */
 220        u8 enable_dma;
 221        void (*cs_control)(u32 command);
 222};
 223
 224extern int dw_spi_add_host(struct dw_spi *dws);
 225extern void dw_spi_remove_host(struct dw_spi *dws);
 226extern int dw_spi_suspend_host(struct dw_spi *dws);
 227extern int dw_spi_resume_host(struct dw_spi *dws);
 228extern void dw_spi_xfer_done(struct dw_spi *dws);
 229
 230/* platform related setup */
 231extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
 232#endif /* DW_SPI_HEADER_H */
 233