1/* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef _sbsdpcmdev_h_ 18#define _sbsdpcmdev_h_ 19 20/* cpp contortions to concatenate w/arg prescan */ 21#ifndef PAD 22#define _PADLINE(line) pad ## line 23#define _XSTR(line) _PADLINE(line) 24#define PAD _XSTR(__LINE__) 25#endif /* PAD */ 26 27typedef volatile struct { 28 dma64regs_t xmt; /* dma tx */ 29 u32 PAD[2]; 30 dma64regs_t rcv; /* dma rx */ 31 u32 PAD[2]; 32} dma64p_t; 33 34/* dma64 sdiod corerev >= 1 */ 35typedef volatile struct { 36 dma64p_t dma64regs[2]; 37 dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */ 38 u32 PAD[92]; 39} sdiodma64_t; 40 41/* dma32 sdiod corerev == 0 */ 42typedef volatile struct { 43 dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */ 44 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */ 45 u32 PAD[108]; 46} sdiodma32_t; 47 48/* dma32 regs for pcmcia core */ 49typedef volatile struct { 50 dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */ 51 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */ 52 u32 PAD[116]; 53} pcmdma32_t; 54 55/* core registers */ 56typedef volatile struct { 57 u32 corecontrol; /* CoreControl, 0x000, rev8 */ 58 u32 corestatus; /* CoreStatus, 0x004, rev8 */ 59 u32 PAD[1]; 60 u32 biststatus; /* BistStatus, 0x00c, rev8 */ 61 62 /* PCMCIA access */ 63 u16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ 64 u16 PAD[1]; 65 u16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */ 66 u16 PAD[1]; 67 u16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */ 68 u16 PAD[1]; 69 u16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */ 70 u16 PAD[1]; 71 72 /* interrupt */ 73 u32 intstatus; /* IntStatus, 0x020, rev8 */ 74 u32 hostintmask; /* IntHostMask, 0x024, rev8 */ 75 u32 intmask; /* IntSbMask, 0x028, rev8 */ 76 u32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */ 77 u32 sbintmask; /* SBIntMask, 0x030, rev8 */ 78 u32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */ 79 u32 PAD[2]; 80 u32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */ 81 u32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */ 82 u32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */ 83 u32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */ 84 85 /* synchronized access to registers in SDIO clock domain */ 86 u32 sdioaccess; /* SdioAccess, 0x050, rev8 */ 87 u32 PAD[3]; 88 89 /* PCMCIA frame control */ 90 u8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */ 91 u8 PAD[3]; 92 u8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */ 93 u8 PAD[155]; 94 95 /* interrupt batching control */ 96 u32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */ 97 u32 PAD[3]; 98 99 /* counters */ 100 u32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */ 101 u32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */ 102 u32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */ 103 u32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */ 104 u32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */ 105 u32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */ 106 u32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */ 107 u32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */ 108 u32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */ 109 u32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */ 110 u32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */ 111 u32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */ 112 u32 PAD[40]; 113 u32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */ 114 u32 PAD[7]; 115 116 /* DMA engines */ 117 volatile union { 118 pcmdma32_t pcm32; 119 sdiodma32_t sdiod32; 120 sdiodma64_t sdiod64; 121 } dma; 122 123 /* SDIO/PCMCIA CIS region */ 124 char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */ 125 126 /* PCMCIA function control registers */ 127 char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */ 128 u16 PAD[55]; 129 130 /* PCMCIA backplane access */ 131 u16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */ 132 u16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */ 133 u16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */ 134 u16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */ 135 u16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */ 136 u16 backplanedata0; /* BackplaneData0, 0x778, rev6 */ 137 u16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */ 138 u16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */ 139 u16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */ 140 u16 PAD[31]; 141 142 /* sprom "size" & "blank" info */ 143 u16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ 144 u32 PAD[464]; 145 146 /* Sonics SiliconBackplane registers */ 147 sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */ 148} sdpcmd_regs_t; 149 150/* corecontrol */ 151#define CC_CISRDY (1 << 0) /* CIS Ready */ 152#define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */ 153#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 154#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */ 155#define CC_XMTDATAAVAIL_MODE (1 << 4) /* data avail generates an interrupt */ 156#define CC_XMTDATAAVAIL_CTRL (1 << 5) /* data avail interrupt ctrl */ 157 158/* corestatus */ 159#define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */ 160#define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */ 161#define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */ 162 163#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */ 164#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */ 165#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */ 166#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */ 167 168/* intstatus */ 169#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 170#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 171#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 172#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 173#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 174#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 175#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 176#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 177#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 178#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 179#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 180#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 181#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 182#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 183#define I_PC (1 << 10) /* descriptor error */ 184#define I_PD (1 << 11) /* data error */ 185#define I_DE (1 << 12) /* Descriptor protocol Error */ 186#define I_RU (1 << 13) /* Receive descriptor Underflow */ 187#define I_RO (1 << 14) /* Receive fifo Overflow */ 188#define I_XU (1 << 15) /* Transmit fifo Underflow */ 189#define I_RI (1 << 16) /* Receive Interrupt */ 190#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 191#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 192#define I_XI (1 << 24) /* Transmit Interrupt */ 193#define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 194#define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 195#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 196#define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 197#define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */ 198#define I_SRESET (1 << 30) /* CCCR RES interrupt */ 199#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 200#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */ 201#define I_DMA (I_RI | I_XI | I_ERRORS) 202 203/* sbintstatus */ 204#define I_SB_SERR (1 << 8) /* Backplane SError (write) */ 205#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */ 206#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */ 207 208/* sdioaccess */ 209#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */ 210#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */ 211#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */ 212#define SDA_WRITE 0x01000000 /* Write bit */ 213#define SDA_READ 0x00000000 /* Write bit cleared for Read */ 214#define SDA_BUSY 0x80000000 /* Busy bit */ 215 216/* sdioaccess-accessible register address spaces */ 217#define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */ 218#define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */ 219#define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */ 220#define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */ 221 222/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */ 223#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */ 224#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */ 225#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */ 226#define SDA_DEVICECONTROL 0x009 /* DeviceControl */ 227#define SDA_SBADDRLOW 0x00a /* SbAddrLow */ 228#define SDA_SBADDRMID 0x00b /* SbAddrMid */ 229#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */ 230#define SDA_FRAMECTRL 0x00d /* FrameCtrl */ 231#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */ 232#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */ 233#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */ 234#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */ 235#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */ 236#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */ 237 238/* SDA_F2WATERMARK */ 239#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */ 240 241/* SDA_SBADDRLOW */ 242#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */ 243 244/* SDA_SBADDRMID */ 245#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */ 246 247/* SDA_SBADDRHIGH */ 248#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */ 249 250/* SDA_FRAMECTRL */ 251#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 252#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 253#define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */ 254#define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */ 255 256/* pcmciaframectrl */ 257#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 258#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 259 260/* intrcvlazy */ 261#define IRL_TO_MASK 0x00ffffff /* timeout */ 262#define IRL_FC_MASK 0xff000000 /* frame count */ 263#define IRL_FC_SHIFT 24 /* frame count */ 264 265/* rx header */ 266typedef volatile struct { 267 u16 len; 268 u16 flags; 269} sdpcmd_rxh_t; 270 271/* rx header flags */ 272#define RXF_CRC 0x0001 /* CRC error detected */ 273#define RXF_WOOS 0x0002 /* write frame out of sync */ 274#define RXF_WF_TERM 0x0004 /* write frame terminated */ 275#define RXF_ABORT 0x0008 /* write frame aborted */ 276#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */ 277 278/* HW frame tag */ 279#define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */ 280 281#endif /* _sbsdpcmdev_h_ */ 282