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30#ifndef _FT1000H_
31#define _FT1000H_
32
33
34#define FT1000_DRV_VER 0x01010300
35
36#define DSPVERSZ 4
37#define HWSERNUMSZ 16
38#define SKUSZ 20
39#define EUISZ 8
40#define MODESZ 2
41#define CALVERSZ 2
42#define CALDATESZ 6
43
44
45typedef struct _PSEUDO_HDR
46{
47 unsigned short length;
48 unsigned char source;
49
50
51 unsigned char destination;
52 unsigned char portdest;
53
54
55
56
57
58
59
60 unsigned char portsrc;
61 unsigned short sh_str_id;
62 unsigned char control;
63 unsigned char rsvd1;
64 unsigned char seq_num;
65 unsigned char rsvd2;
66 unsigned short qos_class;
67 unsigned short checksum;
68} __attribute__ ((packed)) PSEUDO_HDR, *PPSEUDO_HDR;
69
70
71#define UCHAR u8
72#define USHORT u16
73#define ULONG u32
74#define BOOLEAN u8
75#define PULONG u32 *
76#define PUSHORT u16 *
77#define PUCHAR u8 *
78#define PCHAR u8 *
79#define UINT u32
80
81#define ELECTRABUZZ_ID 0
82#define MAGNEMITE_ID 0x1a01
83
84
85#define FT1000_REG_DPRAM_ADDR 0x000E
86#define FT1000_REG_SUP_CTRL 0x0020
87#define FT1000_REG_SUP_STAT 0x0022
88#define FT1000_REG_RESET 0x0024
89#define FT1000_REG_SUP_ISR 0x0026
90#define FT1000_REG_SUP_IMASK 0x0028
91#define FT1000_REG_DOORBELL 0x002a
92#define FT1000_REG_ASIC_ID 0x002e
93
94
95
96
97#define FT1000_REG_UFIFO_STAT 0x0000
98#define FT1000_REG_UFIFO_BEG 0x0002
99#define FT1000_REG_UFIFO_MID 0x0004
100#define FT1000_REG_UFIFO_END 0x0006
101#define FT1000_REG_DFIFO_STAT 0x0008
102#define FT1000_REG_DFIFO 0x000A
103#define FT1000_REG_DPRAM_DATA 0x000C
104#define FT1000_REG_WATERMARK 0x0010
105
106
107#define FT1000_REG_MAG_UFDR 0x0000
108#define FT1000_REG_MAG_UFDRL 0x0000
109#define FT1000_REG_MAG_UFDRH 0x0002
110#define FT1000_REG_MAG_UFER 0x0004
111#define FT1000_REG_MAG_UFSR 0x0006
112#define FT1000_REG_MAG_DFR 0x0008
113#define FT1000_REG_MAG_DFRL 0x0008
114#define FT1000_REG_MAG_DFRH 0x000a
115#define FT1000_REG_MAG_DFSR 0x000c
116#define FT1000_REG_MAG_DPDATA 0x0010
117#define FT1000_REG_MAG_DPDATAL 0x0010
118#define FT1000_REG_MAG_DPDATAH 0x0012
119#define FT1000_REG_MAG_WATERMARK 0x002c
120
121
122#define FT1000_DPRAM_TX_BASE 0x0002
123#define FT1000_DPRAM_RX_BASE 0x0800
124#define FT1000_FIFO_LEN 0x7FC
125#define FT1000_HI_HO 0x7FE
126#define FT1000_DSP_STATUS 0xFFE
127#define FT1000_DSP_LED 0xFFA
128#define FT1000_DSP_CON_STATE 0xFF8
129#define FT1000_DPRAM_FEFE 0x002
130#define FT1000_DSP_TIMER0 0x1FF0
131#define FT1000_DSP_TIMER1 0x1FF2
132#define FT1000_DSP_TIMER2 0x1FF4
133#define FT1000_DSP_TIMER3 0x1FF6
134
135
136#define FT1000_DPRAM_MAG_TX_BASE 0x0000
137#define FT1000_DPRAM_MAG_RX_BASE 0x0200
138#define FT1000_MAG_FIFO_LEN 0x1FF
139#define FT1000_MAG_FIFO_LEN_INDX 0x1
140#define FT1000_MAG_HI_HO 0x1FF
141#define FT1000_MAG_HI_HO_INDX 0x0
142#define FT1000_MAG_DSP_LED 0x3FE
143#define FT1000_MAG_DSP_LED_INDX 0x0
144
145#define FT1000_MAG_DSP_CON_STATE 0x3FE
146#define FT1000_MAG_DSP_CON_STATE_INDX 0x1
147
148#define FT1000_MAG_DPRAM_FEFE 0x000
149#define FT1000_MAG_DPRAM_FEFE_INDX 0x0
150
151#define FT1000_MAG_DSP_TIMER0 0x3FC
152#define FT1000_MAG_DSP_TIMER0_INDX 0x1
153
154#define FT1000_MAG_DSP_TIMER1 0x3FC
155#define FT1000_MAG_DSP_TIMER1_INDX 0x0
156
157#define FT1000_MAG_DSP_TIMER2 0x3FD
158#define FT1000_MAG_DSP_TIMER2_INDX 0x1
159
160#define FT1000_MAG_DSP_TIMER3 0x3FD
161#define FT1000_MAG_DSP_TIMER3_INDX 0x0
162
163#define FT1000_MAG_TOTAL_LEN 0x200
164#define FT1000_MAG_TOTAL_LEN_INDX 0x1
165
166#define FT1000_MAG_PH_LEN 0x200
167#define FT1000_MAG_PH_LEN_INDX 0x0
168
169#define FT1000_MAG_PORT_ID 0x201
170#define FT1000_MAG_PORT_ID_INDX 0x0
171
172#define HOST_INTF_LE 0x0
173#define HOST_INTF_BE 0x1
174
175
176#define FT1000_DB_DPRAM_RX 0x0001
177
178#define FT1000_ASIC_RESET_REQ 0x0004
179#define FT1000_DSP_ASIC_RESET 0x0008
180#define FT1000_DB_COND_RESET 0x0010
181
182
183#define FT1000_DB_DPRAM_TX 0x0100
184
185#define FT1000_ASIC_RESET_DSP 0x0400
186#define FT1000_DB_HB 0x1000
187
188
189#define FT1000_DPRAM_BASE 0x0000
190
191#define hi 0x6869
192#define ho 0x686f
193
194
195#define hi_mag 0x6968
196#define ho_mag 0x6f68
197
198
199
200
201
202
203#define ISR_EMPTY 0x00
204#define ISR_DOORBELL_ACK 0x01
205#define ISR_DOORBELL_PEND 0x02
206#define ISR_RCV 0x04
207#define ISR_WATERMARK 0x08
208
209
210#define ISR_MASK_NONE 0x0000
211#define ISR_MASK_DOORBELL_ACK 0x0001
212#define ISR_MASK_DOORBELL_PEND 0x0002
213#define ISR_MASK_RCV 0x0004
214#define ISR_MASK_WATERMARK 0x0008
215#define ISR_MASK_ALL 0xffff
216
217
218#define DSP_RESET_BIT 0x0001
219
220#define ASIC_RESET_BIT 0x0002
221
222
223
224#define ISR_DEFAULT_MASK 0x7ff9
225
226
227#define DSPID 0x20
228#define HOSTID 0x10
229#define DSPAIRID 0x90
230#define DRIVERID 0x00
231#define NETWORKID 0x20
232
233
234#define MAX_CMD_SQSIZE 1780
235
236#define ENET_MAX_SIZE 1514
237#define ENET_HEADER_SIZE 14
238
239#define SLOWQ_TYPE 0
240#define FASTQ_TYPE 1
241
242#define MAX_DSP_SESS_REC 1024
243
244#define DSP_QID_OFFSET 4
245#define PSEUDOSZ 16
246#define PSEUDOSZWRD 8
247
248
249#define MAX_PH_ERR 300
250
251
252#define MEDIA_STATE 0x0010
253#define TIME_UPDATE 0x0020
254#define DSP_PROVISION 0x0030
255#define DSP_INIT_MSG 0x0050
256#define DSP_HIBERNATE 0x0060
257
258#define DSP_STORE_INFO 0x0070
259#define DSP_GET_INFO 0x0071
260#define GET_DRV_ERR_RPT_MSG 0x0073
261#define RSP_DRV_ERR_RPT_MSG 0x0074
262
263
264#define DSP_HB_INFO 0x7ef0
265#define DSP_FIFO_INFO 0x7ef1
266#define DSP_CONDRESET_INFO 0x7ef2
267#define DSP_CMDLEN_INFO 0x7ef3
268#define DSP_CMDPHCKSUM_INFO 0x7ef4
269#define DSP_PKTPHCKSUM_INFO 0x7ef5
270#define DSP_PKTLEN_INFO 0x7ef6
271#define DSP_USER_RESET 0x7ef7
272#define FIFO_FLUSH_MAXLIMIT 0x7ef8
273#define FIFO_FLUSH_BADCNT 0x7ef9
274#define FIFO_ZERO_LEN 0x7efa
275
276#define HOST_QID_OFFSET 5
277#define QTYPE_OFFSET 13
278
279#define SUCCESS 0x00
280#define FAILURE 0x01
281#define TRUE 0x1
282#define FALSE 0x0
283
284#define MAX_NUM_APP 6
285
286#define MAXIMUM_ASIC_HB_CNT 15
287
288typedef struct _DRVMSG {
289 PSEUDO_HDR pseudo;
290 u16 type;
291 u16 length;
292 u8 data[0];
293} __attribute__ ((packed)) DRVMSG, *PDRVMSG;
294
295typedef struct _MEDIAMSG {
296 PSEUDO_HDR pseudo;
297 u16 type;
298 u16 length;
299 u16 state;
300 u32 ip_addr;
301 u32 net_mask;
302 u32 gateway;
303 u32 dns_1;
304 u32 dns_2;
305} __attribute__ ((packed)) MEDIAMSG, *PMEDIAMSG;
306
307typedef struct _TIMEMSG {
308 PSEUDO_HDR pseudo;
309 u16 type;
310 u16 length;
311 u8 timeval[8];
312} __attribute__ ((packed)) TIMEMSG, *PTIMEMSG;
313
314typedef struct _DSPINITMSG {
315 PSEUDO_HDR pseudo;
316 u16 type;
317 u16 length;
318 u8 DspVer[DSPVERSZ];
319 u8 HwSerNum[HWSERNUMSZ];
320 u8 Sku[SKUSZ];
321 u8 eui64[EUISZ];
322 u8 ProductMode[MODESZ];
323 u8 RfCalVer[CALVERSZ];
324 u8 RfCalDate[CALDATESZ];
325} __attribute__ ((packed)) DSPINITMSG, *PDSPINITMSG;
326
327typedef struct _DSPHIBERNATE {
328 PSEUDO_HDR pseudo;
329 u16 type;
330 u16 length;
331 u32 timeout;
332 u16 sess_info[0];
333} DSPHIBERNATE, *PDSPHIBERNATE;
334
335typedef struct _APP_INFO_BLOCK
336{
337 u32 fileobject;
338 u16 app_id;
339} APP_INFO_BLOCK, *PAPP_INFO_BLOCK;
340
341typedef struct _PROV_RECORD {
342 struct list_head list;
343 u8 *pprov_data;
344} PROV_RECORD, *PPROV_RECORD;
345
346typedef struct _FT1000_INFO {
347 struct net_device_stats stats;
348 u16 DrvErrNum;
349 u16 AsicID;
350 int ASICResetNum;
351 int DspAsicReset;
352 int PktIntfErr;
353 int DSPResetNum;
354 int NumIOCTLBufs;
355 int IOCTLBufLvl;
356 int DeviceCreated;
357 int CardReady;
358 int DspHibernateFlag;
359 int DSPReady;
360 u8 DeviceName[15];
361 int DeviceMajor;
362 int registered;
363 int mediastate;
364 u16 packetseqnum;
365 u8 squeseqnum;
366 spinlock_t dpram_lock;
367 u16 CurrentInterruptEnableMask;
368 int InterruptsEnabled;
369 u16 fifo_cnt;
370 u8 DspVer[DSPVERSZ];
371 u8 HwSerNum[HWSERNUMSZ];
372 u8 Sku[SKUSZ];
373 u8 eui64[EUISZ];
374 time_t ConTm;
375 u16 LedStat;
376 u16 ConStat;
377 u16 ProgConStat;
378 u8 ProductMode[MODESZ];
379 u8 RfCalVer[CALVERSZ];
380 u8 RfCalDate[CALDATESZ];
381 u16 DSP_TIME[4];
382 struct list_head prov_list;
383 int appcnt;
384 APP_INFO_BLOCK app_info[MAX_NUM_APP];
385 u16 DSPInfoBlklen;
386 u16 DrvMsgPend;
387 int (*ft1000_reset)(void *);
388 void *link;
389 u16 DSPInfoBlk[MAX_DSP_SESS_REC];
390 union {
391 u16 Rec[MAX_DSP_SESS_REC];
392 u32 MagRec[MAX_DSP_SESS_REC/2];
393 } DSPSess;
394 struct proc_dir_entry *proc_ft1000;
395 char netdevname[IFNAMSIZ];
396} FT1000_INFO, *PFT1000_INFO;
397
398typedef struct _DPRAM_BLK {
399 struct list_head list;
400 u16 *pbuffer;
401} __attribute__ ((packed)) DPRAM_BLK, *PDPRAM_BLK;
402
403extern u16 ft1000_read_dpram (struct net_device *dev, int offset);
404extern void card_bootload(struct net_device *dev);
405extern u16 ft1000_read_dpram_mag_16 (struct net_device *dev, int offset, int Index);
406extern u32 ft1000_read_dpram_mag_32 (struct net_device *dev, int offset);
407void ft1000_write_dpram_mag_32 (struct net_device *dev, int offset, u32 value);
408
409#endif
410