LXR linux/drivers/staging/rtl8712/rtl871x

   1/******************************************************************************
   2 * rtl871x_mp.c
   3 *
   4 * Description :
   5 *
   6 * Author :
   7 *
   8 * History :
   9 *
  10 * Copyright 2007, Realtek Corp.
  11 *
  12 * The contents of this file is the sole property of Realtek Corp. It can not be
  13 * be used, copied or modified without written permission from Realtek Corp.
  14 *
  15*******************************************************************************/
  16#define _RTL871X_MP_C_
  17
  18#include "osdep_service.h"
  19#include "drv_types.h"
  20#include "rtl871x_mp_phy_regdef.h"
  21#include "rtl8712_cmd.h"
  22
  23static void _init_mp_priv_(struct mp_priv *pmp_priv)
  24{
  25        pmp_priv->mode = _LOOPBOOK_MODE_;
  26        pmp_priv->curr_ch = 1;
  27        pmp_priv->curr_modem = MIXED_PHY;
  28        pmp_priv->curr_rateidx = 0;
  29        pmp_priv->curr_txpoweridx = 0x14;
  30        pmp_priv->antenna_tx = ANTENNA_A;
  31        pmp_priv->antenna_rx = ANTENNA_AB;
  32        pmp_priv->check_mp_pkt = 0;
  33        pmp_priv->tx_pktcount = 0;
  34        pmp_priv->rx_pktcount = 0;
  35        pmp_priv->rx_crcerrpktcount = 0;
  36}
  37
  38static int init_mp_priv(struct mp_priv *pmp_priv)
  39{
  40        int i, res;
  41        struct mp_xmit_frame *pmp_xmitframe;
  42
  43        _init_mp_priv_(pmp_priv);
  44        _init_queue(&pmp_priv->free_mp_xmitqueue);
  45        pmp_priv->pallocated_mp_xmitframe_buf = NULL;
  46        pmp_priv->pallocated_mp_xmitframe_buf = _malloc(NR_MP_XMITFRAME *
  47                                         sizeof(struct mp_xmit_frame) + 4);
  48        if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
  49                res = _FAIL;
  50                goto _exit_init_mp_priv;
  51        }
  52        pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
  53                         4 -
  54                         ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
  55        pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
  56        for (i = 0; i < NR_MP_XMITFRAME; i++) {
  57                _init_listhead(&(pmp_xmitframe->list));
  58                list_insert_tail(&(pmp_xmitframe->list),
  59                                 &(pmp_priv->free_mp_xmitqueue.queue));
  60                pmp_xmitframe->pkt = NULL;
  61                pmp_xmitframe->frame_tag = MP_FRAMETAG;
  62                pmp_xmitframe->padapter = pmp_priv->papdater;
  63                pmp_xmitframe++;
  64        }
  65        pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
  66        res = _SUCCESS;
  67_exit_init_mp_priv:
  68        return res;
  69}
  70
  71static int free_mp_priv(struct mp_priv *pmp_priv)
  72{
  73        int res = 0;
  74        kfree(pmp_priv->pallocated_mp_xmitframe_buf);
  75        return res;
  76}
  77
  78void mp871xinit(struct _adapter *padapter)
  79{
  80        struct mp_priv *pmppriv = &padapter->mppriv;
  81
  82        pmppriv->papdater = padapter;
  83        init_mp_priv(pmppriv);
  84}
  85
  86void mp871xdeinit(struct _adapter *padapter)
  87{
  88        struct mp_priv *pmppriv = &padapter->mppriv;
  89
  90        free_mp_priv(pmppriv);
  91}
  92
  93/*
  94 * Special for bb and rf reg read/write
  95 */
  96static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
  97{
  98        u32 cmd32 = 0, val32 = 0;
  99        u8 iocmd_class  = iocmd.cmdclass;
 100        u16 iocmd_value = iocmd.value;
 101        u8 iocmd_idx    = iocmd.index;
 102
 103        cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx ;
 104        if (r8712_fw_cmd(pAdapter, cmd32))
 105                r8712_fw_cmd_data(pAdapter, &val32, 1);
 106        else
 107                val32 = 0;
 108        return val32;
 109}
 110
 111static u8 fw_iocmd_write(struct _adapter *pAdapter,
 112                         struct IOCMD_STRUCT iocmd, u32 value)
 113{
 114        u32 cmd32 = 0;
 115        u8 iocmd_class  = iocmd.cmdclass;
 116        u32 iocmd_value = iocmd.value;
 117        u8 iocmd_idx    = iocmd.index;
 118
 119        r8712_fw_cmd_data(pAdapter, &value, 0);
 120        msleep(100);
 121        cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx ;
 122        return r8712_fw_cmd(pAdapter, cmd32);
 123}
 124
 125/* offset : 0X800~0XFFF */
 126u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
 127{
 128        u8 shift = offset & 0x0003;     /* 4 byte access */
 129        u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 130        u32 bb_val = 0;
 131        struct IOCMD_STRUCT iocmd;
 132
 133        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 134        iocmd.value     = bb_addr;
 135        iocmd.index     = IOCMD_BB_READ_IDX;
 136        bb_val = fw_iocmd_read(pAdapter, iocmd);
 137        if (shift != 0) {
 138                u32 bb_val2 = 0;
 139                bb_val >>= (shift * 8);
 140                iocmd.value += 4;
 141                bb_val2 = fw_iocmd_read(pAdapter, iocmd);
 142                bb_val2 <<= ((4 - shift) * 8);
 143                bb_val |= bb_val2;
 144        }
 145        return bb_val;
 146}
 147
 148/* offset : 0X800~0XFFF */
 149u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
 150{
 151        u8 shift = offset & 0x0003;     /* 4 byte access */
 152        u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 153        struct IOCMD_STRUCT iocmd;
 154
 155        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 156        iocmd.value     = bb_addr;
 157        iocmd.index     = IOCMD_BB_WRITE_IDX;
 158        if (shift != 0) {
 159                u32 oldValue = 0;
 160                u32 newValue = value;
 161
 162                oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 163                oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
 164                value = oldValue | (newValue << (shift * 8));
 165                if (fw_iocmd_write(pAdapter, iocmd, value) == false)
 166                        return false;
 167                iocmd.value += 4;
 168                oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 169                oldValue &= (0xFFFFFFFF << (shift * 8));
 170                value = oldValue | (newValue >> ((4 - shift) * 8));
 171        }
 172        return fw_iocmd_write(pAdapter, iocmd, value);
 173}
 174
 175/* offset : 0x00 ~ 0xFF */
 176u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
 177{
 178        u16 rf_addr = (path << 8) | offset;
 179        u32 rf_data;
 180        struct IOCMD_STRUCT iocmd;
 181
 182        iocmd.cmdclass  = IOCMD_CLASS_BB_RF ;
 183        iocmd.value     = rf_addr ;
 184        iocmd.index     = IOCMD_RF_READ_IDX;
 185        rf_data = fw_iocmd_read(pAdapter, iocmd);
 186        return rf_data;
 187}
 188
 189u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
 190{
 191        u16 rf_addr = (path << 8) | offset;
 192        struct IOCMD_STRUCT iocmd;
 193
 194        iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 195        iocmd.value     = rf_addr;
 196        iocmd.index     = IOCMD_RF_WRIT_IDX;
 197        return fw_iocmd_write(pAdapter, iocmd, value);
 198}
 199
 200static u32 bitshift(u32 bitmask)
 201{
 202        u32 i;
 203
 204        for (i = 0; i <= 31; i++)
 205                if (((bitmask>>i) &  0x1) == 1)
 206                        break;
 207        return i;
 208}
 209
 210static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
 211{
 212        u32 org_value, bit_shift, new_value;
 213
 214        org_value = r8712_bb_reg_read(pAdapter, offset);
 215        bit_shift = bitshift(bitmask);
 216        new_value = (org_value & bitmask) >> bit_shift;
 217        return new_value;
 218}
 219
 220static u8 set_bb_reg(struct _adapter *pAdapter,
 221                     u16 offset,
 222                     u32 bitmask,
 223                     u32 value)
 224{
 225        u32 org_value, bit_shift, new_value;
 226
 227        if (bitmask != bMaskDWord) {
 228                org_value = r8712_bb_reg_read(pAdapter, offset);
 229                bit_shift = bitshift(bitmask);
 230                new_value = ((org_value & (~bitmask)) | (value << bit_shift));
 231        } else
 232                new_value = value;
 233        return r8712_bb_reg_write(pAdapter, offset, new_value);
 234}
 235
 236static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
 237                      u32 bitmask)
 238{
 239        u32 org_value, bit_shift, new_value;
 240
 241        org_value = r8712_rf_reg_read(pAdapter, path, offset);
 242        bit_shift = bitshift(bitmask);
 243        new_value = (org_value & bitmask) >> bit_shift;
 244        return new_value;
 245}
 246
 247static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
 248              u32 value)
 249{
 250        u32 org_value, bit_shift, new_value;
 251
 252        if (bitmask != bMaskDWord) {
 253                org_value = r8712_rf_reg_read(pAdapter, path, offset);
 254                bit_shift = bitshift(bitmask);
 255                new_value = ((org_value & (~bitmask)) | (value << bit_shift));
 256        } else
 257                new_value = value;
 258        return r8712_rf_reg_write(pAdapter, path, offset, new_value);
 259}
 260
 261/*
 262 * SetChannel
 263 * Description
 264 *      Use H2C command to change channel,
 265 *      not only modify rf register, but also other setting need to be done.
 266 */
 267void r8712_SetChannel(struct _adapter *pAdapter)
 268{
 269        struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
 270        struct cmd_obj *pcmd = NULL;
 271        struct SetChannel_parm *pparm = NULL;
 272        u16 code = GEN_CMD_CODE(_SetChannel);
 273
 274        pcmd = (struct cmd_obj *)_malloc(sizeof(struct cmd_obj));
 275        if (pcmd == NULL)
 276                return;
 277        pparm = (struct SetChannel_parm *)_malloc(sizeof(struct
 278                                         SetChannel_parm));
 279        if (pparm == NULL) {
 280                kfree(pcmd);
 281                return;
 282        }
 283        pparm->curr_ch = pAdapter->mppriv.curr_ch;
 284        init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
 285        r8712_enqueue_cmd(pcmdpriv, pcmd);
 286}
 287
 288static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
 289{
 290        u16 TxAGC = 0;
 291
 292        TxAGC = TxPower;
 293        set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 294}
 295
 296static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
 297{
 298        u32 TxAGC = 0;
 299
 300        TxAGC |= ((TxPower<<24)|(TxPower<<16)|(TxPower<<8)|TxPower);
 301        set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
 302        set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
 303        set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
 304        set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
 305        set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
 306        set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
 307}
 308
 309void r8712_SetTxPower(struct _adapter *pAdapter)
 310{
 311        u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
 312        SetCCKTxPower(pAdapter, TxPower);
 313        SetOFDMTxPower(pAdapter, TxPower);
 314}
 315
 316void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
 317{
 318        u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
 319
 320        TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
 321        TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
 322        TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
 323        tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
 324        set_bb_reg(pAdapter, rFPGA0_TxGainStage,
 325                        (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
 326}
 327
 328void r8712_SetDataRate(struct _adapter *pAdapter)
 329{
 330        u8 path = RF_PATH_A;
 331        u8 offset = RF_SYN_G2;
 332        u32 value;
 333
 334        value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
 335        r8712_rf_reg_write(pAdapter, path, offset, value);
 336}
 337
 338void r8712_SwitchBandwidth(struct _adapter *pAdapter)
 339{
 340        /* 3 1.Set MAC register : BWOPMODE  bit2:1 20MhzBW */
 341        u8 regBwOpMode = 0;
 342        u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
 343
 344        regBwOpMode = r8712_read8(pAdapter, 0x10250203);
 345        if (Bandwidth == HT_CHANNEL_WIDTH_20)
 346                regBwOpMode |= BIT(2);
 347        else
 348                regBwOpMode &= ~(BIT(2));
 349        r8712_write8(pAdapter, 0x10250203, regBwOpMode);
 350        /* 3 2.Set PHY related register */
 351        switch (Bandwidth) {
 352        /* 20 MHz channel*/
 353        case HT_CHANNEL_WIDTH_20:
 354                set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
 355                set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
 356                /* Use PHY_REG.txt default value. Do not need to change.
 357                 * Correct the tx power for CCK rate in 40M.
 358                 * It is set in Tx descriptor for 8192x series
 359                 */
 360                set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
 361                break;
 362        /* 40 MHz channel*/
 363        case HT_CHANNEL_WIDTH_40:
 364                set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
 365                set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
 366                /* Use PHY_REG.txt default value. Do not need to change.
 367                 * Correct the tx power for CCK rate in 40M.
 368                 * Set Control channel to upper or lower. These settings are
 369                 * required only for 40MHz */
 370                set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
 371                           (HAL_PRIME_CHNL_OFFSET_DONT_CARE>>1));
 372                set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
 373                           HAL_PRIME_CHNL_OFFSET_DONT_CARE);
 374                set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
 375                break;
 376        default:
 377                break;
 378        }
 379
 380        /* 3 3.Set RF related register */
 381        switch (Bandwidth) {
 382        case HT_CHANNEL_WIDTH_20:
 383                set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 384                           BIT(10) | BIT(11), 0x01);
 385                break;
 386        case HT_CHANNEL_WIDTH_40:
 387                set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 388                           BIT(10) | BIT(11), 0x00);
 389                break;
 390        default:
 391                break;
 392        }
 393}
 394/*------------------------------Define structure----------------------------*/
 395struct R_ANTENNA_SELECT_OFDM {
 396        u32     r_tx_antenna:4;
 397        u32     r_ant_l:4;
 398        u32     r_ant_non_ht:4;
 399        u32     r_ant_ht1:4;
 400        u32     r_ant_ht2:4;
 401        u32     r_ant_ht_s1:4;
 402        u32     r_ant_non_ht_s1:4;
 403        u32     OFDM_TXSC:2;
 404        u32     Reserved:2;
 405};
 406
 407struct R_ANTENNA_SELECT_CCK {
 408        u8      r_cckrx_enable_2:2;
 409        u8      r_cckrx_enable:2;
 410        u8      r_ccktx_enable:4;
 411};
 412
 413void r8712_SwitchAntenna(struct _adapter *pAdapter)
 414{
 415        u32     ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
 416        u8      ofdm_rx_ant_sel_val = 0;
 417        u8      cck_ant_select_val = 0;
 418        u32     cck_ant_sel_val = 0;
 419        struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
 420
 421        p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
 422
 423        switch (pAdapter->mppriv.antenna_tx) {
 424        case ANTENNA_A:
 425                /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
 426                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 427                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
 428                ofdm_tx_en_val = 0x3;
 429                ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
 430                p_cck_txrx->r_ccktx_enable = 0x8;
 431                break;
 432        case ANTENNA_B:
 433                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
 434                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 435                ofdm_tx_en_val = 0x3;
 436                ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
 437                p_cck_txrx->r_ccktx_enable = 0x4;
 438                break;
 439        case ANTENNA_AB:        /* For 8192S */
 440                set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 441                set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 442                ofdm_tx_en_val = 0x3;
 443                ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
 444                p_cck_txrx->r_ccktx_enable = 0xC;
 445                break;
 446        default:
 447                break;
 448        }
 449        /*OFDM Tx*/
 450        set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
 451        /*OFDM Tx*/
 452        set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
 453        switch (pAdapter->mppriv.antenna_rx) {
 454        case ANTENNA_A:
 455                ofdm_rx_ant_sel_val = 0x1;      /* A */
 456                p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
 457                p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
 458                break;
 459        case ANTENNA_B:
 460                ofdm_rx_ant_sel_val = 0x2;      /* B */
 461                p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
 462                p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
 463                break;
 464        case ANTENNA_AB:
 465                ofdm_rx_ant_sel_val = 0x3; /* AB */
 466                p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
 467                p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
 468                break;
 469        default:
 470                break;
 471        }
 472        /*OFDM Rx*/
 473        set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
 474                   ofdm_rx_ant_sel_val);
 475        /*OFDM Rx*/
 476        set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
 477                   ofdm_rx_ant_sel_val);
 478
 479        cck_ant_sel_val = cck_ant_select_val;
 480        /*CCK TxRx*/
 481        set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
 482}
 483
 484void r8712_SetCrystalCap(struct _adapter *pAdapter)
 485{
 486        set_bb_reg(pAdapter, rFPGA0_AnalogParameter1, bXtalCap,
 487                   pAdapter->mppriv.curr_crystalcap);
 488}
 489
 490static void TriggerRFThermalMeter(struct _adapter *pAdapter)
 491{
 492        /* 0x24: RF Reg[6:5] */
 493        set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
 494}
 495
 496static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
 497{
 498        u32 ThermalValue = 0;
 499
 500        /* 0x24: RF Reg[4:0] */
 501        ThermalValue = get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
 502        return ThermalValue;
 503}
 504
 505void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
 506{
 507        TriggerRFThermalMeter(pAdapter);
 508        msleep(1000);
 509        *value = ReadRFThermalMeter(pAdapter);
 510}
 511
 512void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
 513{
 514        if (bStart) { /* Start Single Carrier. */
 515                /* 1. if OFDM block on? */
 516                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 517                        /*set OFDM block on*/
 518                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 519                /* 2. set CCK test mode off, set to CCK normal mode */
 520                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 521                /* 3. turn on scramble setting */
 522                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 523                /* 4. Turn On Single Carrier Tx and off the other test modes. */
 524                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 525                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
 526                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 527        } else { /* Stop Single Carrier.*/
 528                /* Turn off all test modes.*/
 529                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 530                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 531                           bDisable);
 532                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 533                msleep(20);
 534                /*BB Reset*/
 535                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 536                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 537        }
 538}
 539
 540void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
 541{
 542        u8 rfPath = pAdapter->mppriv.curr_rfpath;
 543        switch (pAdapter->mppriv.antenna_tx) {
 544        case ANTENNA_B:
 545                rfPath = RF_PATH_B;
 546                break;
 547        case ANTENNA_A:
 548        default:
 549                rfPath = RF_PATH_A;
 550                break;
 551        }
 552        if (bStart) { /* Start Single Tone.*/
 553                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
 554                set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
 555                set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 556                           0xd4000);
 557                msleep(100);
 558                /* PAD all on.*/
 559                set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
 560                msleep(100);
 561        } else { /* Stop Single Tone.*/
 562                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 563                set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 564                set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 565                           0x54000);
 566                msleep(100);
 567                /* PAD all on.*/
 568                set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
 569                msleep(100);
 570        }
 571}
 572
 573void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
 574{
 575        if (bStart) { /* Start Carrier Suppression.*/
 576                if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 577                        /* 1. if CCK block on? */
 578                        if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 579                                /*set CCK block on*/
 580                                set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
 581                                           bEnable);
 582                        }
 583                        /* Turn Off All Test Mode */
 584                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
 585                                   bDisable);
 586                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 587                                   bDisable);
 588                        set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
 589                                   bDisable);
 590                        /*transmit mode*/
 591                        set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 592                        /*turn off scramble setting*/
 593                        set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 594                                   bDisable);
 595                        /*Set CCK Tx Test Rate*/
 596                        /*Set FTxRate to 1Mbps*/
 597                        set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
 598                }
 599        } else { /* Stop Carrier Suppression. */
 600                if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 601                        /*normal mode*/
 602                        set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 603                        /*turn on scramble setting*/
 604                        set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 605                                   bEnable);
 606                        /*BB Reset*/
 607                        set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 608                        set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 609                }
 610        }
 611}
 612
 613static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
 614{
 615        u32 cckrate;
 616
 617        if (bStart) {
 618                /* 1. if CCK block on? */
 619                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 620                        /*set CCK block on*/
 621                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 622                }
 623                /* Turn Off All Test Mode */
 624                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 625                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 626                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 627                /*Set CCK Tx Test Rate*/
 628                cckrate  = pAdapter->mppriv.curr_rateidx;
 629                set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
 630                /*transmit mode*/
 631                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 632                /*turn on scramble setting*/
 633                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 634        } else {
 635                /*normal mode*/
 636                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 637                /*turn on scramble setting*/
 638                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 639                /*BB Reset*/
 640                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 641                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 642        }
 643} /* mpt_StartCckContTx */
 644
 645static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
 646{
 647        if (bStart) {
 648                /* 1. if OFDM block on? */
 649                if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
 650                        /*set OFDM block on*/
 651                        set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 652                }
 653                /* 2. set CCK test mode off, set to CCK normal mode*/
 654                set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 655                /* 3. turn on scramble setting */
 656                set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 657                /* 4. Turn On Continue Tx and turn off the other test modes.*/
 658                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
 659                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 660                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 661        } else {
 662                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 663                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 664                           bDisable);
 665                set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 666                msleep(20);
 667                /*BB Reset*/
 668                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 669                set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 670        }
 671} /* mpt_StartOfdmContTx */
 672
 673void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
 674{
 675        /* ADC turn off [bit24-21] adc port0 ~ port1 */
 676        if (bStart) {
 677                r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 678                                   r8712_bb_reg_read(pAdapter,
 679                                   rRx_Wait_CCCA) & 0xFE1FFFFF);
 680                msleep(100);
 681        }
 682        if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
 683                SetCCKContinuousTx(pAdapter, bStart);
 684        else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
 685                 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
 686                SetOFDMContinuousTx(pAdapter, bStart);
 687        /* ADC turn on [bit24-21] adc port0 ~ port1 */
 688        if (!bStart)
 689                r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 690                                   r8712_bb_reg_read(pAdapter,
 691                                   rRx_Wait_CCCA) | 0x01E00000);
 692}
 693
 694void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
 695{
 696        u32 i, phyrx_set = 0;
 697
 698        for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
 699                phyrx_set = 0;
 700                phyrx_set |= (i << 28);         /*select*/
 701                phyrx_set |= 0x08000000;        /* set counter to zero*/
 702                r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 703        }
 704}
 705
 706static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
 707{
 708        /*selection*/
 709        u32 phyrx_set = 0, count = 0;
 710        u32 SelectBit;
 711
 712        SelectBit = selbit << 28;
 713        phyrx_set |= (SelectBit & 0xF0000000);
 714        r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 715        /*Read packet count*/
 716        count = r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
 717        return count;
 718}
 719
 720u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
 721{
 722        u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
 723
 724        OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
 725        CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
 726        HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
 727        return OFDM_cnt + CCK_cnt + HT_cnt;
 728}
 729
 730u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
 731{
 732        u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
 733
 734        OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
 735        CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
 736        HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
 737        return OFDM_cnt + CCK_cnt + HT_cnt;
 738}
 739