1#ifndef _SUNZILOG_H 2#define _SUNZILOG_H 3 4struct zilog_channel { 5 volatile unsigned char control; 6 volatile unsigned char __pad1; 7 volatile unsigned char data; 8 volatile unsigned char __pad2; 9}; 10 11struct zilog_layout { 12 struct zilog_channel channelB; 13 struct zilog_channel channelA; 14}; 15 16#define NUM_ZSREGS 17 17#define R7p 16 /* Written as R7 with P15 bit 0 set */ 18 19/* Conversion routines to/from brg time constants from/to bits 20 * per second. 21 */ 22#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) 23#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) 24 25/* The Zilog register set */ 26 27#define FLAG 0x7e 28 29/* Write Register 0 */ 30#define R0 0 /* Register selects */ 31#define R1 1 32#define R2 2 33#define R3 3 34#define R4 4 35#define R5 5 36#define R6 6 37#define R7 7 38#define R8 8 39#define R9 9 40#define R10 10 41#define R11 11 42#define R12 12 43#define R13 13 44#define R14 14 45#define R15 15 46 47#define NULLCODE 0 /* Null Code */ 48#define POINT_HIGH 0x8 /* Select upper half of registers */ 49#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 50#define SEND_ABORT 0x18 /* HDLC Abort */ 51#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 52#define RES_Tx_P 0x28 /* Reset TxINT Pending */ 53#define ERR_RES 0x30 /* Error Reset */ 54#define RES_H_IUS 0x38 /* Reset highest IUS */ 55 56#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 57#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 58#define RES_EOM_L 0xC0 /* Reset EOM latch */ 59 60/* Write Register 1 */ 61 62#define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 63#define TxINT_ENAB 0x2 /* Tx Int Enable */ 64#define PAR_SPEC 0x4 /* Parity is special condition */ 65 66#define RxINT_DISAB 0 /* Rx Int Disable */ 67#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ 68#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ 69#define INT_ERR_Rx 0x18 /* Int on error only */ 70#define RxINT_MASK 0x18 71 72#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */ 73#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */ 74#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */ 75 76/* Write Register #2 (Interrupt Vector) */ 77 78/* Write Register 3 */ 79 80#define RxENAB 0x1 /* Rx Enable */ 81#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ 82#define ADD_SM 0x4 /* Address Search Mode (SDLC) */ 83#define RxCRC_ENAB 0x8 /* Rx CRC Enable */ 84#define ENT_HM 0x10 /* Enter Hunt Mode */ 85#define AUTO_ENAB 0x20 /* Auto Enables */ 86#define Rx5 0x0 /* Rx 5 Bits/Character */ 87#define Rx7 0x40 /* Rx 7 Bits/Character */ 88#define Rx6 0x80 /* Rx 6 Bits/Character */ 89#define Rx8 0xc0 /* Rx 8 Bits/Character */ 90#define RxN_MASK 0xc0 91 92/* Write Register 4 */ 93 94#define PAR_ENAB 0x1 /* Parity Enable */ 95#define PAR_EVEN 0x2 /* Parity Even/Odd* */ 96 97#define SYNC_ENAB 0 /* Sync Modes Enable */ 98#define SB1 0x4 /* 1 stop bit/char */ 99#define SB15 0x8 /* 1.5 stop bits/char */ 100#define SB2 0xc /* 2 stop bits/char */ 101 102#define MONSYNC 0 /* 8 Bit Sync character */ 103#define BISYNC 0x10 /* 16 bit sync character */ 104#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ 105#define EXTSYNC 0x30 /* External Sync Mode */ 106 107#define X1CLK 0x0 /* x1 clock mode */ 108#define X16CLK 0x40 /* x16 clock mode */ 109#define X32CLK 0x80 /* x32 clock mode */ 110#define X64CLK 0xC0 /* x64 clock mode */ 111#define XCLK_MASK 0xC0 112 113/* Write Register 5 */ 114 115#define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 116#define RTS 0x2 /* RTS */ 117#define SDLC_CRC 0x4 /* SDLC/CRC-16 */ 118#define TxENAB 0x8 /* Tx Enable */ 119#define SND_BRK 0x10 /* Send Break */ 120#define Tx5 0x0 /* Tx 5 bits (or less)/character */ 121#define Tx7 0x20 /* Tx 7 bits/character */ 122#define Tx6 0x40 /* Tx 6 bits/character */ 123#define Tx8 0x60 /* Tx 8 bits/character */ 124#define TxN_MASK 0x60 125#define DTR 0x80 /* DTR */ 126 127/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ 128 129/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ 130 131/* Write Register 7' (ESCC Only) */ 132#define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */ 133#define AUTO_EOM_RST 2 /* Automatic EOM Reset */ 134#define AUTOnRTS 4 /* Automatic /RTS pin deactivation */ 135#define RxFIFO_LVL 8 /* Receive FIFO interrupt level */ 136#define nDTRnREQ 0x10 /* /DTR/REQ timing */ 137#define TxFIFO_LVL 0x20 /* Transmit FIFO interrupt level */ 138#define EXT_RD_EN 0x40 /* Extended read register enable */ 139 140/* Write Register 8 (transmit buffer) */ 141 142/* Write Register 9 (Master interrupt control) */ 143#define VIS 1 /* Vector Includes Status */ 144#define NV 2 /* No Vector */ 145#define DLC 4 /* Disable Lower Chain */ 146#define MIE 8 /* Master Interrupt Enable */ 147#define STATHI 0x10 /* Status high */ 148#define SWIACK 0x20 /* Software Interrupt Ack (not on NMOS) */ 149#define NORESET 0 /* No reset on write to R9 */ 150#define CHRB 0x40 /* Reset channel B */ 151#define CHRA 0x80 /* Reset channel A */ 152#define FHWRES 0xc0 /* Force hardware reset */ 153 154/* Write Register 10 (misc control bits) */ 155#define BIT6 1 /* 6 bit/8bit sync */ 156#define LOOPMODE 2 /* SDLC Loop mode */ 157#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ 158#define MARKIDLE 8 /* Mark/flag on idle */ 159#define GAOP 0x10 /* Go active on poll */ 160#define NRZ 0 /* NRZ mode */ 161#define NRZI 0x20 /* NRZI mode */ 162#define FM1 0x40 /* FM1 (transition = 1) */ 163#define FM0 0x60 /* FM0 (transition = 0) */ 164#define CRCPS 0x80 /* CRC Preset I/O */ 165 166/* Write Register 11 (Clock Mode control) */ 167#define TRxCXT 0 /* TRxC = Xtal output */ 168#define TRxCTC 1 /* TRxC = Transmit clock */ 169#define TRxCBR 2 /* TRxC = BR Generator Output */ 170#define TRxCDP 3 /* TRxC = DPLL output */ 171#define TRxCOI 4 /* TRxC O/I */ 172#define TCRTxCP 0 /* Transmit clock = RTxC pin */ 173#define TCTRxCP 8 /* Transmit clock = TRxC pin */ 174#define TCBR 0x10 /* Transmit clock = BR Generator output */ 175#define TCDPLL 0x18 /* Transmit clock = DPLL output */ 176#define RCRTxCP 0 /* Receive clock = RTxC pin */ 177#define RCTRxCP 0x20 /* Receive clock = TRxC pin */ 178#define RCBR 0x40 /* Receive clock = BR Generator output */ 179#define RCDPLL 0x60 /* Receive clock = DPLL output */ 180#define RTxCX 0x80 /* RTxC Xtal/No Xtal */ 181 182/* Write Register 12 (lower byte of baud rate generator time constant) */ 183 184/* Write Register 13 (upper byte of baud rate generator time constant) */ 185 186/* Write Register 14 (Misc control bits) */ 187#define BRENAB 1 /* Baud rate generator enable */ 188#define BRSRC 2 /* Baud rate generator source */ 189#define DTRREQ 4 /* DTR/Request function */ 190#define AUTOECHO 8 /* Auto Echo */ 191#define LOOPBAK 0x10 /* Local loopback */ 192#define SEARCH 0x20 /* Enter search mode */ 193#define RMC 0x40 /* Reset missing clock */ 194#define DISDPLL 0x60 /* Disable DPLL */ 195#define SSBR 0x80 /* Set DPLL source = BR generator */ 196#define SSRTxC 0xa0 /* Set DPLL source = RTxC */ 197#define SFMM 0xc0 /* Set FM mode */ 198#define SNRZI 0xe0 /* Set NRZI mode */ 199 200/* Write Register 15 (external/status interrupt control) */ 201#define WR7pEN 1 /* WR7' Enable (ESCC only) */ 202#define ZCIE 2 /* Zero count IE */ 203#define FIFOEN 4 /* FIFO Enable (ESCC only) */ 204#define DCDIE 8 /* DCD IE */ 205#define SYNCIE 0x10 /* Sync/hunt IE */ 206#define CTSIE 0x20 /* CTS IE */ 207#define TxUIE 0x40 /* Tx Underrun/EOM IE */ 208#define BRKIE 0x80 /* Break/Abort IE */ 209 210 211/* Read Register 0 */ 212#define Rx_CH_AV 0x1 /* Rx Character Available */ 213#define ZCOUNT 0x2 /* Zero count */ 214#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ 215#define DCD 0x8 /* DCD */ 216#define SYNC 0x10 /* Sync/hunt */ 217#define CTS 0x20 /* CTS */ 218#define TxEOM 0x40 /* Tx underrun */ 219#define BRK_ABRT 0x80 /* Break/Abort */ 220 221/* Read Register 1 */ 222#define ALL_SNT 0x1 /* All sent */ 223/* Residue Data for 8 Rx bits/char programmed */ 224#define RES3 0x8 /* 0/3 */ 225#define RES4 0x4 /* 0/4 */ 226#define RES5 0xc /* 0/5 */ 227#define RES6 0x2 /* 0/6 */ 228#define RES7 0xa /* 0/7 */ 229#define RES8 0x6 /* 0/8 */ 230#define RES18 0xe /* 1/8 */ 231#define RES28 0x0 /* 2/8 */ 232/* Special Rx Condition Interrupts */ 233#define PAR_ERR 0x10 /* Parity error */ 234#define Rx_OVR 0x20 /* Rx Overrun Error */ 235#define CRC_ERR 0x40 /* CRC/Framing Error */ 236#define END_FR 0x80 /* End of Frame (SDLC) */ 237 238/* Read Register 2 (channel b only) - Interrupt vector */ 239#define CHB_Tx_EMPTY 0x00 240#define CHB_EXT_STAT 0x02 241#define CHB_Rx_AVAIL 0x04 242#define CHB_SPECIAL 0x06 243#define CHA_Tx_EMPTY 0x08 244#define CHA_EXT_STAT 0x0a 245#define CHA_Rx_AVAIL 0x0c 246#define CHA_SPECIAL 0x0e 247#define STATUS_MASK 0x0e 248 249/* Read Register 3 (interrupt pending register) ch a only */ 250#define CHBEXT 0x1 /* Channel B Ext/Stat IP */ 251#define CHBTxIP 0x2 /* Channel B Tx IP */ 252#define CHBRxIP 0x4 /* Channel B Rx IP */ 253#define CHAEXT 0x8 /* Channel A Ext/Stat IP */ 254#define CHATxIP 0x10 /* Channel A Tx IP */ 255#define CHARxIP 0x20 /* Channel A Rx IP */ 256 257/* Read Register 6 (LSB frame byte count [Not on NMOS]) */ 258 259/* Read Register 7 (MSB frame byte count and FIFO status [Not on NMOS]) */ 260 261/* Read Register 8 (receive data register) */ 262 263/* Read Register 10 (misc status bits) */ 264#define ONLOOP 2 /* On loop */ 265#define LOOPSEND 0x10 /* Loop sending */ 266#define CLK2MIS 0x40 /* Two clocks missing */ 267#define CLK1MIS 0x80 /* One clock missing */ 268 269/* Read Register 12 (lower byte of baud rate generator constant) */ 270 271/* Read Register 13 (upper byte of baud rate generator constant) */ 272 273/* Read Register 15 (value of WR 15) */ 274 275/* Misc macros */ 276#define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \ 277 udelay(5); } while(0) 278 279#define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \ 280 udelay(5); } while(0) 281 282#define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \ 283 udelay(2); \ 284 sbus_readb(&channel->data); \ 285 udelay(2); \ 286 sbus_readb(&channel->data); \ 287 udelay(2); } while(0) 288 289#endif /* _SUNZILOG_H */ 290