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11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/init.h>
15#include <linux/list.h>
16#include <linux/gpio.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20
21#include <asm/cacheflush.h>
22
23#include "musb_core.h"
24#include "musbhsdma.h"
25#include "blackfin.h"
26
27struct bfin_glue {
28 struct device *dev;
29 struct platform_device *musb;
30};
31#define glue_to_musb(g) platform_get_drvdata(g->musb)
32
33
34
35
36void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
37{
38 struct musb *musb = hw_ep->musb;
39 void __iomem *fifo = hw_ep->fifo;
40 void __iomem *epio = hw_ep->regs;
41 u8 epnum = hw_ep->epnum;
42
43 prefetch((u8 *)src);
44
45 musb_writew(epio, MUSB_TXCOUNT, len);
46
47 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
48 hw_ep->epnum, fifo, len, src, epio);
49
50 dump_fifo_data(src, len);
51
52 if (!ANOMALY_05000380 && epnum != 0) {
53 u16 dma_reg;
54
55 flush_dcache_range((unsigned long)src,
56 (unsigned long)(src + len));
57
58
59 dma_reg = (u32)src;
60 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
61 SSYNC();
62
63 dma_reg = (u32)src >> 16;
64 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
65 SSYNC();
66
67
68 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
69 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
70 SSYNC();
71
72
73 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
74 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
75 SSYNC();
76
77
78 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
79 cpu_relax();
80
81
82 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
83 SSYNC();
84
85
86 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
87 SSYNC();
88 } else {
89 SSYNC();
90
91 if (unlikely((unsigned long)src & 0x01))
92 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
93 else
94 outsw((unsigned long)fifo, src, (len + 1) >> 1);
95 }
96}
97
98
99
100void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
101{
102 struct musb *musb = hw_ep->musb;
103 void __iomem *fifo = hw_ep->fifo;
104 u8 epnum = hw_ep->epnum;
105
106 if (ANOMALY_05000467 && epnum != 0) {
107 u16 dma_reg;
108
109 invalidate_dcache_range((unsigned long)dst,
110 (unsigned long)(dst + len));
111
112
113 dma_reg = (u32)dst;
114 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
115 SSYNC();
116
117 dma_reg = (u32)dst >> 16;
118 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
119 SSYNC();
120
121
122 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
123 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
124 SSYNC();
125
126
127 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
128 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
129 SSYNC();
130
131
132 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
133 cpu_relax();
134
135
136 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
137 SSYNC();
138
139
140 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
141 SSYNC();
142 } else {
143 SSYNC();
144
145
146
147 if (len == 1)
148 *dst = (u8)inw((unsigned long)fifo + 4);
149 else {
150 if (unlikely((unsigned long)dst & 0x01))
151 insw_8((unsigned long)fifo, dst, len >> 1);
152 else
153 insw((unsigned long)fifo, dst, len >> 1);
154
155 if (len & 0x01)
156 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
157 }
158 }
159 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
160 'R', hw_ep->epnum, fifo, len, dst);
161
162 dump_fifo_data(dst, len);
163}
164
165static irqreturn_t blackfin_interrupt(int irq, void *__hci)
166{
167 unsigned long flags;
168 irqreturn_t retval = IRQ_NONE;
169 struct musb *musb = __hci;
170
171 spin_lock_irqsave(&musb->lock, flags);
172
173 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
174 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
175 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
176
177 if (musb->int_usb || musb->int_tx || musb->int_rx) {
178 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
179 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
180 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
181 retval = musb_interrupt(musb);
182 }
183
184
185 if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
186 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) ||
187 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
188 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
189 musb->a_wait_bcon = TIMER_DELAY;
190 }
191
192 spin_unlock_irqrestore(&musb->lock, flags);
193
194 return retval;
195}
196
197static void musb_conn_timer_handler(unsigned long _musb)
198{
199 struct musb *musb = (void *)_musb;
200 unsigned long flags;
201 u16 val;
202 static u8 toggle;
203
204 spin_lock_irqsave(&musb->lock, flags);
205 switch (musb->xceiv->state) {
206 case OTG_STATE_A_IDLE:
207 case OTG_STATE_A_WAIT_BCON:
208
209 val = musb_readw(musb->mregs, MUSB_DEVCTL);
210 val &= ~MUSB_DEVCTL_SESSION;
211 musb_writew(musb->mregs, MUSB_DEVCTL, val);
212 val |= MUSB_DEVCTL_SESSION;
213 musb_writew(musb->mregs, MUSB_DEVCTL, val);
214
215 val = musb_readw(musb->mregs, MUSB_DEVCTL);
216
217 if (!(val & MUSB_DEVCTL_BDEVICE)) {
218 gpio_set_value(musb->config->gpio_vrsel, 1);
219 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
220 } else {
221 gpio_set_value(musb->config->gpio_vrsel, 0);
222
223 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
224 val &= ~MUSB_INTR_VBUSERROR;
225 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
226
227 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
228 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
229 if (is_otg_enabled(musb))
230 musb->xceiv->state = OTG_STATE_B_IDLE;
231 else
232 musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
233 }
234 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
235 break;
236 case OTG_STATE_B_IDLE:
237
238 if (!is_peripheral_enabled(musb))
239 break;
240
241
242
243 val = musb_readw(musb->mregs, MUSB_DEVCTL);
244 val |= MUSB_DEVCTL_SESSION;
245 musb_writew(musb->mregs, MUSB_DEVCTL, val);
246 val = musb_readw(musb->mregs, MUSB_DEVCTL);
247
248 if (!(val & MUSB_DEVCTL_BDEVICE)) {
249 gpio_set_value(musb->config->gpio_vrsel, 1);
250 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
251 } else {
252 gpio_set_value(musb->config->gpio_vrsel, 0);
253
254
255 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
256 val &= ~MUSB_INTR_VBUSERROR;
257 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
258
259 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
260 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
261
262
263
264
265 if (toggle) {
266 val = musb_readb(musb->mregs, MUSB_POWER);
267 val &= ~MUSB_POWER_SOFTCONN;
268 musb_writeb(musb->mregs, MUSB_POWER, val);
269 toggle = 0;
270 } else {
271 val = musb_readb(musb->mregs, MUSB_POWER);
272 val |= MUSB_POWER_SOFTCONN;
273 musb_writeb(musb->mregs, MUSB_POWER, val);
274 toggle = 1;
275 }
276
277
278
279
280 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
281 }
282 break;
283 default:
284 dev_dbg(musb->controller, "%s state not handled\n",
285 otg_state_string(musb->xceiv->state));
286 break;
287 }
288 spin_unlock_irqrestore(&musb->lock, flags);
289
290 dev_dbg(musb->controller, "state is %s\n",
291 otg_state_string(musb->xceiv->state));
292}
293
294static void bfin_musb_enable(struct musb *musb)
295{
296 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
297 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
298 musb->a_wait_bcon = TIMER_DELAY;
299 }
300}
301
302static void bfin_musb_disable(struct musb *musb)
303{
304}
305
306static void bfin_musb_set_vbus(struct musb *musb, int is_on)
307{
308 int value = musb->config->gpio_vrsel_active;
309 if (!is_on)
310 value = !value;
311 gpio_set_value(musb->config->gpio_vrsel, value);
312
313 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
314 "\n",
315 otg_state_string(musb->xceiv->state),
316 musb_readb(musb->mregs, MUSB_DEVCTL));
317}
318
319static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
320{
321 return 0;
322}
323
324static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
325{
326 if (!is_otg_enabled(musb) && is_host_enabled(musb))
327 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
328}
329
330static int bfin_musb_vbus_status(struct musb *musb)
331{
332 return 0;
333}
334
335static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
336{
337 return -EIO;
338}
339
340static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
341 u16 packet_sz, u8 *mode,
342 dma_addr_t *dma_addr, u32 *len)
343{
344 struct musb_dma_channel *musb_channel = channel->private_data;
345
346
347
348
349
350
351
352
353 if (ANOMALY_05000450) {
354 if (musb_channel->transmit && *mode == 1)
355 *len = *len - (*len % packet_sz);
356 }
357
358 return 0;
359}
360
361static void bfin_musb_reg_init(struct musb *musb)
362{
363 if (ANOMALY_05000346) {
364 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
365 SSYNC();
366 }
367
368 if (ANOMALY_05000347) {
369 bfin_write_USB_APHY_CNTRL(0x0);
370 SSYNC();
371 }
372
373
374 bfin_write_USB_PLLOSC_CTRL(0x3080 |
375 ((480/musb->config->clkin) << 1));
376 SSYNC();
377
378 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
379 SSYNC();
380
381 bfin_write_USB_EP_NI0_RXMAXP(64);
382 SSYNC();
383
384 bfin_write_USB_EP_NI0_TXMAXP(64);
385 SSYNC();
386
387
388 bfin_write_USB_GLOBINTR(0x7);
389 SSYNC();
390
391 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
392 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
393 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
394 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
395 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
396 SSYNC();
397}
398
399static int bfin_musb_init(struct musb *musb)
400{
401
402
403
404
405
406
407
408
409 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
410 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
411 musb->config->gpio_vrsel);
412 return -ENODEV;
413 }
414 gpio_direction_output(musb->config->gpio_vrsel, 0);
415
416 usb_nop_xceiv_register();
417 musb->xceiv = otg_get_transceiver();
418 if (!musb->xceiv) {
419 gpio_free(musb->config->gpio_vrsel);
420 return -ENODEV;
421 }
422
423 bfin_musb_reg_init(musb);
424
425 if (is_host_enabled(musb)) {
426 setup_timer(&musb_conn_timer,
427 musb_conn_timer_handler, (unsigned long) musb);
428 }
429 if (is_peripheral_enabled(musb))
430 musb->xceiv->set_power = bfin_musb_set_power;
431
432 musb->isr = blackfin_interrupt;
433 musb->double_buffer_not_ok = true;
434
435 return 0;
436}
437
438static int bfin_musb_exit(struct musb *musb)
439{
440 gpio_free(musb->config->gpio_vrsel);
441
442 otg_put_transceiver(musb->xceiv);
443 usb_nop_xceiv_unregister();
444 return 0;
445}
446
447static const struct musb_platform_ops bfin_ops = {
448 .init = bfin_musb_init,
449 .exit = bfin_musb_exit,
450
451 .enable = bfin_musb_enable,
452 .disable = bfin_musb_disable,
453
454 .set_mode = bfin_musb_set_mode,
455 .try_idle = bfin_musb_try_idle,
456
457 .vbus_status = bfin_musb_vbus_status,
458 .set_vbus = bfin_musb_set_vbus,
459
460 .adjust_channel_params = bfin_musb_adjust_channel_params,
461};
462
463static u64 bfin_dmamask = DMA_BIT_MASK(32);
464
465static int __init bfin_probe(struct platform_device *pdev)
466{
467 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
468 struct platform_device *musb;
469 struct bfin_glue *glue;
470
471 int ret = -ENOMEM;
472
473 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
474 if (!glue) {
475 dev_err(&pdev->dev, "failed to allocate glue context\n");
476 goto err0;
477 }
478
479 musb = platform_device_alloc("musb-hdrc", -1);
480 if (!musb) {
481 dev_err(&pdev->dev, "failed to allocate musb device\n");
482 goto err1;
483 }
484
485 musb->dev.parent = &pdev->dev;
486 musb->dev.dma_mask = &bfin_dmamask;
487 musb->dev.coherent_dma_mask = bfin_dmamask;
488
489 glue->dev = &pdev->dev;
490 glue->musb = musb;
491
492 pdata->platform_ops = &bfin_ops;
493
494 platform_set_drvdata(pdev, glue);
495
496 ret = platform_device_add_resources(musb, pdev->resource,
497 pdev->num_resources);
498 if (ret) {
499 dev_err(&pdev->dev, "failed to add resources\n");
500 goto err2;
501 }
502
503 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
504 if (ret) {
505 dev_err(&pdev->dev, "failed to add platform_data\n");
506 goto err2;
507 }
508
509 ret = platform_device_add(musb);
510 if (ret) {
511 dev_err(&pdev->dev, "failed to register musb device\n");
512 goto err2;
513 }
514
515 return 0;
516
517err2:
518 platform_device_put(musb);
519
520err1:
521 kfree(glue);
522
523err0:
524 return ret;
525}
526
527static int __exit bfin_remove(struct platform_device *pdev)
528{
529 struct bfin_glue *glue = platform_get_drvdata(pdev);
530
531 platform_device_del(glue->musb);
532 platform_device_put(glue->musb);
533 kfree(glue);
534
535 return 0;
536}
537
538#ifdef CONFIG_PM
539static int bfin_suspend(struct device *dev)
540{
541 struct bfin_glue *glue = dev_get_drvdata(dev);
542 struct musb *musb = glue_to_musb(glue);
543
544 if (is_host_active(musb))
545
546
547
548
549
550
551 gpio_set_value(musb->config->gpio_vrsel, 0);
552
553 return 0;
554}
555
556static int bfin_resume(struct device *dev)
557{
558 struct bfin_glue *glue = dev_get_drvdata(dev);
559 struct musb *musb = glue_to_musb(glue);
560
561 bfin_musb_reg_init(musb);
562
563 return 0;
564}
565
566static struct dev_pm_ops bfin_pm_ops = {
567 .suspend = bfin_suspend,
568 .resume = bfin_resume,
569};
570
571#define DEV_PM_OPS &bfin_pm_ops
572#else
573#define DEV_PM_OPS NULL
574#endif
575
576static struct platform_driver bfin_driver = {
577 .remove = __exit_p(bfin_remove),
578 .driver = {
579 .name = "musb-blackfin",
580 .pm = DEV_PM_OPS,
581 },
582};
583
584MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
585MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
586MODULE_LICENSE("GPL v2");
587
588static int __init bfin_init(void)
589{
590 return platform_driver_probe(&bfin_driver, bfin_probe);
591}
592subsys_initcall(bfin_init);
593
594static void __exit bfin_exit(void)
595{
596 platform_driver_unregister(&bfin_driver);
597}
598module_exit(bfin_exit);
599
