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102#include <linux/version.h>
103
104#include "matroxfb_base.h"
105#include "matroxfb_misc.h"
106#include "matroxfb_accel.h"
107#include "matroxfb_DAC1064.h"
108#include "matroxfb_Ti3026.h"
109#include "matroxfb_maven.h"
110#include "matroxfb_crtc2.h"
111#include "matroxfb_g450.h"
112#include <linux/matroxfb.h>
113#include <linux/interrupt.h>
114#include <linux/slab.h>
115#include <linux/uaccess.h>
116
117#ifdef CONFIG_PPC_PMAC
118#include <asm/machdep.h>
119unsigned char nvram_read_byte(int);
120static int default_vmode = VMODE_NVRAM;
121static int default_cmode = CMODE_NVRAM;
122#endif
123
124static void matroxfb_unregister_device(struct matrox_fb_info* minfo);
125
126
127
128
129
130
131
132
133
134static struct fb_var_screeninfo vesafb_defined = {
135 640,480,640,480,
136 0,0,
137 8,
138 0,
139 {0,0,0},
140 {0,0,0},
141 {0,0,0},
142 {0,0,0},
143 0,
144 FB_ACTIVATE_NOW,
145 -1,-1,
146 FB_ACCELF_TEXT,
147 39721L,48L,16L,33L,10L,
148 96L,2L,~0,
149 FB_VMODE_NONINTERLACED,
150 0, {0,0,0,0,0}
151};
152
153
154
155
156static void update_crtc2(struct matrox_fb_info *minfo, unsigned int pos)
157{
158 struct matroxfb_dh_fb_info *info = minfo->crtc2.info;
159
160
161 if (info && (info->fbcon.var.bits_per_pixel == minfo->fbcon.var.bits_per_pixel)
162 && (info->fbcon.var.xres_virtual == minfo->fbcon.var.xres_virtual)
163 && (info->fbcon.var.green.length == minfo->fbcon.var.green.length)
164 ) {
165 switch (minfo->fbcon.var.bits_per_pixel) {
166 case 16:
167 case 32:
168 pos = pos * 8;
169 if (info->interlaced) {
170 mga_outl(0x3C2C, pos);
171 mga_outl(0x3C28, pos + minfo->fbcon.var.xres_virtual * minfo->fbcon.var.bits_per_pixel / 8);
172 } else {
173 mga_outl(0x3C28, pos);
174 }
175 break;
176 }
177 }
178}
179
180static void matroxfb_crtc1_panpos(struct matrox_fb_info *minfo)
181{
182 if (minfo->crtc1.panpos >= 0) {
183 unsigned long flags;
184 int panpos;
185
186 matroxfb_DAC_lock_irqsave(flags);
187 panpos = minfo->crtc1.panpos;
188 if (panpos >= 0) {
189 unsigned int extvga_reg;
190
191 minfo->crtc1.panpos = -1;
192 extvga_reg = mga_inb(M_EXTVGA_INDEX);
193 mga_setr(M_EXTVGA_INDEX, 0x00, panpos);
194 if (extvga_reg != 0x00) {
195 mga_outb(M_EXTVGA_INDEX, extvga_reg);
196 }
197 }
198 matroxfb_DAC_unlock_irqrestore(flags);
199 }
200}
201
202static irqreturn_t matrox_irq(int irq, void *dev_id)
203{
204 u_int32_t status;
205 int handled = 0;
206 struct matrox_fb_info *minfo = dev_id;
207
208 status = mga_inl(M_STATUS);
209
210 if (status & 0x20) {
211 mga_outl(M_ICLEAR, 0x20);
212 minfo->crtc1.vsync.cnt++;
213 matroxfb_crtc1_panpos(minfo);
214 wake_up_interruptible(&minfo->crtc1.vsync.wait);
215 handled = 1;
216 }
217 if (status & 0x200) {
218 mga_outl(M_ICLEAR, 0x200);
219 minfo->crtc2.vsync.cnt++;
220 wake_up_interruptible(&minfo->crtc2.vsync.wait);
221 handled = 1;
222 }
223 return IRQ_RETVAL(handled);
224}
225
226int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable)
227{
228 u_int32_t bm;
229
230 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
231 bm = 0x220;
232 else
233 bm = 0x020;
234
235 if (!test_and_set_bit(0, &minfo->irq_flags)) {
236 if (request_irq(minfo->pcidev->irq, matrox_irq,
237 IRQF_SHARED, "matroxfb", minfo)) {
238 clear_bit(0, &minfo->irq_flags);
239 return -EINVAL;
240 }
241
242 mga_outl(M_ICLEAR, bm);
243 mga_outl(M_IEN, mga_inl(M_IEN) | bm);
244 } else if (reenable) {
245 u_int32_t ien;
246
247 ien = mga_inl(M_IEN);
248 if ((ien & bm) != bm) {
249 printk(KERN_DEBUG "matroxfb: someone disabled IRQ [%08X]\n", ien);
250 mga_outl(M_IEN, ien | bm);
251 }
252 }
253 return 0;
254}
255
256static void matroxfb_disable_irq(struct matrox_fb_info *minfo)
257{
258 if (test_and_clear_bit(0, &minfo->irq_flags)) {
259
260 matroxfb_crtc1_panpos(minfo);
261 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
262 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x220);
263 else
264 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x20);
265 free_irq(minfo->pcidev->irq, minfo);
266 }
267}
268
269int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc)
270{
271 struct matrox_vsync *vs;
272 unsigned int cnt;
273 int ret;
274
275 switch (crtc) {
276 case 0:
277 vs = &minfo->crtc1.vsync;
278 break;
279 case 1:
280 if (minfo->devflags.accelerator != FB_ACCEL_MATROX_MGAG400) {
281 return -ENODEV;
282 }
283 vs = &minfo->crtc2.vsync;
284 break;
285 default:
286 return -ENODEV;
287 }
288 ret = matroxfb_enable_irq(minfo, 0);
289 if (ret) {
290 return ret;
291 }
292
293 cnt = vs->cnt;
294 ret = wait_event_interruptible_timeout(vs->wait, cnt != vs->cnt, HZ/10);
295 if (ret < 0) {
296 return ret;
297 }
298 if (ret == 0) {
299 matroxfb_enable_irq(minfo, 1);
300 return -ETIMEDOUT;
301 }
302 return 0;
303}
304
305
306
307static void matrox_pan_var(struct matrox_fb_info *minfo,
308 struct fb_var_screeninfo *var)
309{
310 unsigned int pos;
311 unsigned short p0, p1, p2;
312 unsigned int p3;
313 int vbl;
314 unsigned long flags;
315
316 CRITFLAGS
317
318 DBG(__func__)
319
320 if (minfo->dead)
321 return;
322
323 minfo->fbcon.var.xoffset = var->xoffset;
324 minfo->fbcon.var.yoffset = var->yoffset;
325 pos = (minfo->fbcon.var.yoffset * minfo->fbcon.var.xres_virtual + minfo->fbcon.var.xoffset) * minfo->curr.final_bppShift / 32;
326 pos += minfo->curr.ydstorg.chunks;
327 p0 = minfo->hw.CRTC[0x0D] = pos & 0xFF;
328 p1 = minfo->hw.CRTC[0x0C] = (pos & 0xFF00) >> 8;
329 p2 = minfo->hw.CRTCEXT[0] = (minfo->hw.CRTCEXT[0] & 0xB0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
330 p3 = minfo->hw.CRTCEXT[8] = pos >> 21;
331
332
333 vbl = (var->activate & FB_ACTIVATE_VBL) && (matroxfb_enable_irq(minfo, 0) == 0);
334
335 CRITBEGIN
336
337 matroxfb_DAC_lock_irqsave(flags);
338 mga_setr(M_CRTC_INDEX, 0x0D, p0);
339 mga_setr(M_CRTC_INDEX, 0x0C, p1);
340 if (minfo->devflags.support32MB)
341 mga_setr(M_EXTVGA_INDEX, 0x08, p3);
342 if (vbl) {
343 minfo->crtc1.panpos = p2;
344 } else {
345
346 minfo->crtc1.panpos = -1;
347 mga_setr(M_EXTVGA_INDEX, 0x00, p2);
348 }
349 matroxfb_DAC_unlock_irqrestore(flags);
350
351 update_crtc2(minfo, pos);
352
353 CRITEND
354}
355
356static void matroxfb_remove(struct matrox_fb_info *minfo, int dummy)
357{
358
359
360
361
362
363
364
365
366 minfo->dead = 1;
367 if (minfo->usecount) {
368
369 return;
370 }
371 matroxfb_unregister_device(minfo);
372 unregister_framebuffer(&minfo->fbcon);
373 matroxfb_g450_shutdown(minfo);
374#ifdef CONFIG_MTRR
375 if (minfo->mtrr.vram_valid)
376 mtrr_del(minfo->mtrr.vram, minfo->video.base, minfo->video.len);
377#endif
378 mga_iounmap(minfo->mmio.vbase);
379 mga_iounmap(minfo->video.vbase);
380 release_mem_region(minfo->video.base, minfo->video.len_maximum);
381 release_mem_region(minfo->mmio.base, 16384);
382 kfree(minfo);
383}
384
385
386
387
388
389static int matroxfb_open(struct fb_info *info, int user)
390{
391 struct matrox_fb_info *minfo = info2minfo(info);
392
393 DBG_LOOP(__func__)
394
395 if (minfo->dead) {
396 return -ENXIO;
397 }
398 minfo->usecount++;
399 if (user) {
400 minfo->userusecount++;
401 }
402 return(0);
403}
404
405static int matroxfb_release(struct fb_info *info, int user)
406{
407 struct matrox_fb_info *minfo = info2minfo(info);
408
409 DBG_LOOP(__func__)
410
411 if (user) {
412 if (0 == --minfo->userusecount) {
413 matroxfb_disable_irq(minfo);
414 }
415 }
416 if (!(--minfo->usecount) && minfo->dead) {
417 matroxfb_remove(minfo, 0);
418 }
419 return(0);
420}
421
422static int matroxfb_pan_display(struct fb_var_screeninfo *var,
423 struct fb_info* info) {
424 struct matrox_fb_info *minfo = info2minfo(info);
425
426 DBG(__func__)
427
428 matrox_pan_var(minfo, var);
429 return 0;
430}
431
432static int matroxfb_get_final_bppShift(const struct matrox_fb_info *minfo,
433 int bpp)
434{
435 int bppshft2;
436
437 DBG(__func__)
438
439 bppshft2 = bpp;
440 if (!bppshft2) {
441 return 8;
442 }
443 if (isInterleave(minfo))
444 bppshft2 >>= 1;
445 if (minfo->devflags.video64bits)
446 bppshft2 >>= 1;
447 return bppshft2;
448}
449
450static int matroxfb_test_and_set_rounding(const struct matrox_fb_info *minfo,
451 int xres, int bpp)
452{
453 int over;
454 int rounding;
455
456 DBG(__func__)
457
458 switch (bpp) {
459 case 0: return xres;
460 case 4: rounding = 128;
461 break;
462 case 8: rounding = 64;
463 break;
464 case 16: rounding = 32;
465 break;
466 case 24: rounding = 64;
467 break;
468 default: rounding = 16;
469
470 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
471 rounding = 32;
472 break;
473 }
474 if (isInterleave(minfo)) {
475 rounding *= 2;
476 }
477 over = xres % rounding;
478 if (over)
479 xres += rounding-over;
480 return xres;
481}
482
483static int matroxfb_pitch_adjust(const struct matrox_fb_info *minfo, int xres,
484 int bpp)
485{
486 const int* width;
487 int xres_new;
488
489 DBG(__func__)
490
491 if (!bpp) return xres;
492
493 width = minfo->capable.vxres;
494
495 if (minfo->devflags.precise_width) {
496 while (*width) {
497 if ((*width >= xres) && (matroxfb_test_and_set_rounding(minfo, *width, bpp) == *width)) {
498 break;
499 }
500 width++;
501 }
502 xres_new = *width;
503 } else {
504 xres_new = matroxfb_test_and_set_rounding(minfo, xres, bpp);
505 }
506 return xres_new;
507}
508
509static int matroxfb_get_cmap_len(struct fb_var_screeninfo *var) {
510
511 DBG(__func__)
512
513 switch (var->bits_per_pixel) {
514 case 4:
515 return 16;
516 case 8:
517 return 256;
518 case 16:
519 return 16;
520
521 case 24:
522 return 16;
523
524 case 32:
525 return 16;
526
527 }
528 return 16;
529}
530
531static int matroxfb_decode_var(const struct matrox_fb_info *minfo,
532 struct fb_var_screeninfo *var, int *visual,
533 int *video_cmap_len, unsigned int* ydstorg)
534{
535 struct RGBT {
536 unsigned char bpp;
537 struct {
538 unsigned char offset,
539 length;
540 } red,
541 green,
542 blue,
543 transp;
544 signed char visual;
545 };
546 static const struct RGBT table[]= {
547 { 8,{ 0,8},{0,8},{0,8},{ 0,0},MX_VISUAL_PSEUDOCOLOR},
548 {15,{10,5},{5,5},{0,5},{15,1},MX_VISUAL_DIRECTCOLOR},
549 {16,{11,5},{5,6},{0,5},{ 0,0},MX_VISUAL_DIRECTCOLOR},
550 {24,{16,8},{8,8},{0,8},{ 0,0},MX_VISUAL_DIRECTCOLOR},
551 {32,{16,8},{8,8},{0,8},{24,8},MX_VISUAL_DIRECTCOLOR}
552 };
553 struct RGBT const *rgbt;
554 unsigned int bpp = var->bits_per_pixel;
555 unsigned int vramlen;
556 unsigned int memlen;
557
558 DBG(__func__)
559
560 switch (bpp) {
561 case 4: if (!minfo->capable.cfb4) return -EINVAL;
562 break;
563 case 8: break;
564 case 16: break;
565 case 24: break;
566 case 32: break;
567 default: return -EINVAL;
568 }
569 *ydstorg = 0;
570 vramlen = minfo->video.len_usable;
571 if (var->yres_virtual < var->yres)
572 var->yres_virtual = var->yres;
573 if (var->xres_virtual < var->xres)
574 var->xres_virtual = var->xres;
575
576 var->xres_virtual = matroxfb_pitch_adjust(minfo, var->xres_virtual, bpp);
577 memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
578 if (memlen > vramlen) {
579 var->yres_virtual = vramlen * 8 / (var->xres_virtual * bpp);
580 memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
581 }
582
583
584
585 if (!minfo->capable.cross4MB && (memlen > 0x400000)) {
586 if (bpp == 24) {
587
588 } else {
589 unsigned int linelen;
590 unsigned int m1 = linelen = var->xres_virtual * bpp / 8;
591 unsigned int m2 = PAGE_SIZE;
592 unsigned int max_yres;
593
594 while (m1) {
595 int t;
596
597 while (m2 >= m1) m2 -= m1;
598 t = m1;
599 m1 = m2;
600 m2 = t;
601 }
602 m2 = linelen * PAGE_SIZE / m2;
603 *ydstorg = m2 = 0x400000 % m2;
604 max_yres = (vramlen - m2) / linelen;
605 if (var->yres_virtual > max_yres)
606 var->yres_virtual = max_yres;
607 }
608 }
609
610 if (var->yres_virtual > 32767)
611 var->yres_virtual = 32767;
612
613
614 if (var->yres_virtual < var->yres)
615 var->yres = var->yres_virtual;
616 if (var->xres_virtual < var->xres)
617 var->xres = var->xres_virtual;
618 if (var->xoffset + var->xres > var->xres_virtual)
619 var->xoffset = var->xres_virtual - var->xres;
620 if (var->yoffset + var->yres > var->yres_virtual)
621 var->yoffset = var->yres_virtual - var->yres;
622
623 if (bpp == 16 && var->green.length == 5) {
624 bpp--;
625 }
626
627 for (rgbt = table; rgbt->bpp < bpp; rgbt++);
628#define SETCLR(clr)\
629 var->clr.offset = rgbt->clr.offset;\
630 var->clr.length = rgbt->clr.length
631 SETCLR(red);
632 SETCLR(green);
633 SETCLR(blue);
634 SETCLR(transp);
635#undef SETCLR
636 *visual = rgbt->visual;
637
638 if (bpp > 8)
639 dprintk("matroxfb: truecolor: "
640 "size=%d:%d:%d:%d, shift=%d:%d:%d:%d\n",
641 var->transp.length, var->red.length, var->green.length, var->blue.length,
642 var->transp.offset, var->red.offset, var->green.offset, var->blue.offset);
643
644 *video_cmap_len = matroxfb_get_cmap_len(var);
645 dprintk(KERN_INFO "requested %d*%d/%dbpp (%d*%d)\n", var->xres, var->yres, var->bits_per_pixel,
646 var->xres_virtual, var->yres_virtual);
647 return 0;
648}
649
650static int matroxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
651 unsigned blue, unsigned transp,
652 struct fb_info *fb_info)
653{
654 struct matrox_fb_info* minfo = container_of(fb_info, struct matrox_fb_info, fbcon);
655
656 DBG(__func__)
657
658
659
660
661
662
663
664
665 if (regno >= minfo->curr.cmap_len)
666 return 1;
667
668 if (minfo->fbcon.var.grayscale) {
669
670 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
671 }
672
673 red = CNVT_TOHW(red, minfo->fbcon.var.red.length);
674 green = CNVT_TOHW(green, minfo->fbcon.var.green.length);
675 blue = CNVT_TOHW(blue, minfo->fbcon.var.blue.length);
676 transp = CNVT_TOHW(transp, minfo->fbcon.var.transp.length);
677
678 switch (minfo->fbcon.var.bits_per_pixel) {
679 case 4:
680 case 8:
681 mga_outb(M_DAC_REG, regno);
682 mga_outb(M_DAC_VAL, red);
683 mga_outb(M_DAC_VAL, green);
684 mga_outb(M_DAC_VAL, blue);
685 break;
686 case 16:
687 if (regno >= 16)
688 break;
689 {
690 u_int16_t col =
691 (red << minfo->fbcon.var.red.offset) |
692 (green << minfo->fbcon.var.green.offset) |
693 (blue << minfo->fbcon.var.blue.offset) |
694 (transp << minfo->fbcon.var.transp.offset);
695 minfo->cmap[regno] = col | (col << 16);
696 }
697 break;
698 case 24:
699 case 32:
700 if (regno >= 16)
701 break;
702 minfo->cmap[regno] =
703 (red << minfo->fbcon.var.red.offset) |
704 (green << minfo->fbcon.var.green.offset) |
705 (blue << minfo->fbcon.var.blue.offset) |
706 (transp << minfo->fbcon.var.transp.offset);
707 break;
708 }
709 return 0;
710}
711
712static void matroxfb_init_fix(struct matrox_fb_info *minfo)
713{
714 struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
715 DBG(__func__)
716
717 strcpy(fix->id,"MATROX");
718
719 fix->xpanstep = 8;
720 fix->ypanstep = 1;
721 fix->ywrapstep = 0;
722 fix->mmio_start = minfo->mmio.base;
723 fix->mmio_len = minfo->mmio.len;
724 fix->accel = minfo->devflags.accelerator;
725}
726
727static void matroxfb_update_fix(struct matrox_fb_info *minfo)
728{
729 struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
730 DBG(__func__)
731
732 mutex_lock(&minfo->fbcon.mm_lock);
733 fix->smem_start = minfo->video.base + minfo->curr.ydstorg.bytes;
734 fix->smem_len = minfo->video.len_usable - minfo->curr.ydstorg.bytes;
735 mutex_unlock(&minfo->fbcon.mm_lock);
736}
737
738static int matroxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
739{
740 int err;
741 int visual;
742 int cmap_len;
743 unsigned int ydstorg;
744 struct matrox_fb_info *minfo = info2minfo(info);
745
746 if (minfo->dead) {
747 return -ENXIO;
748 }
749 if ((err = matroxfb_decode_var(minfo, var, &visual, &cmap_len, &ydstorg)) != 0)
750 return err;
751 return 0;
752}
753
754static int matroxfb_set_par(struct fb_info *info)
755{
756 int err;
757 int visual;
758 int cmap_len;
759 unsigned int ydstorg;
760 struct fb_var_screeninfo *var;
761 struct matrox_fb_info *minfo = info2minfo(info);
762
763 DBG(__func__)
764
765 if (minfo->dead) {
766 return -ENXIO;
767 }
768
769 var = &info->var;
770 if ((err = matroxfb_decode_var(minfo, var, &visual, &cmap_len, &ydstorg)) != 0)
771 return err;
772 minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase) + ydstorg;
773 matroxfb_update_fix(minfo);
774 minfo->fbcon.fix.visual = visual;
775 minfo->fbcon.fix.type = FB_TYPE_PACKED_PIXELS;
776 minfo->fbcon.fix.type_aux = 0;
777 minfo->fbcon.fix.line_length = (var->xres_virtual * var->bits_per_pixel) >> 3;
778 {
779 unsigned int pos;
780
781 minfo->curr.cmap_len = cmap_len;
782 ydstorg += minfo->devflags.ydstorg;
783 minfo->curr.ydstorg.bytes = ydstorg;
784 minfo->curr.ydstorg.chunks = ydstorg >> (isInterleave(minfo) ? 3 : 2);
785 if (var->bits_per_pixel == 4)
786 minfo->curr.ydstorg.pixels = ydstorg;
787 else
788 minfo->curr.ydstorg.pixels = (ydstorg * 8) / var->bits_per_pixel;
789 minfo->curr.final_bppShift = matroxfb_get_final_bppShift(minfo, var->bits_per_pixel);
790 { struct my_timming mt;
791 struct matrox_hw_state* hw;
792 int out;
793
794 matroxfb_var2my(var, &mt);
795 mt.crtc = MATROXFB_SRC_CRTC1;
796
797 switch (var->bits_per_pixel) {
798 case 0: mt.delay = 31 + 0; break;
799 case 16: mt.delay = 21 + 8; break;
800 case 24: mt.delay = 17 + 8; break;
801 case 32: mt.delay = 16 + 8; break;
802 default: mt.delay = 31 + 8; break;
803 }
804
805 hw = &minfo->hw;
806
807 down_read(&minfo->altout.lock);
808 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
809 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
810 minfo->outputs[out].output->compute) {
811 minfo->outputs[out].output->compute(minfo->outputs[out].data, &mt);
812 }
813 }
814 up_read(&minfo->altout.lock);
815 minfo->crtc1.pixclock = mt.pixclock;
816 minfo->crtc1.mnp = mt.mnp;
817 minfo->hw_switch->init(minfo, &mt);
818 pos = (var->yoffset * var->xres_virtual + var->xoffset) * minfo->curr.final_bppShift / 32;
819 pos += minfo->curr.ydstorg.chunks;
820
821 hw->CRTC[0x0D] = pos & 0xFF;
822 hw->CRTC[0x0C] = (pos & 0xFF00) >> 8;
823 hw->CRTCEXT[0] = (hw->CRTCEXT[0] & 0xF0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
824 hw->CRTCEXT[8] = pos >> 21;
825 minfo->hw_switch->restore(minfo);
826 update_crtc2(minfo, pos);
827 down_read(&minfo->altout.lock);
828 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
829 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
830 minfo->outputs[out].output->program) {
831 minfo->outputs[out].output->program(minfo->outputs[out].data);
832 }
833 }
834 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
835 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
836 minfo->outputs[out].output->start) {
837 minfo->outputs[out].output->start(minfo->outputs[out].data);
838 }
839 }
840 up_read(&minfo->altout.lock);
841 matrox_cfbX_init(minfo);
842 }
843 }
844 minfo->initialized = 1;
845 return 0;
846}
847
848static int matroxfb_get_vblank(struct matrox_fb_info *minfo,
849 struct fb_vblank *vblank)
850{
851 unsigned int sts1;
852
853 matroxfb_enable_irq(minfo, 0);
854 memset(vblank, 0, sizeof(*vblank));
855 vblank->flags = FB_VBLANK_HAVE_VCOUNT | FB_VBLANK_HAVE_VSYNC |
856 FB_VBLANK_HAVE_VBLANK | FB_VBLANK_HAVE_HBLANK;
857 sts1 = mga_inb(M_INSTS1);
858 vblank->vcount = mga_inl(M_VCOUNT);
859
860
861
862 if (sts1 & 1)
863 vblank->flags |= FB_VBLANK_HBLANKING;
864 if (sts1 & 8)
865 vblank->flags |= FB_VBLANK_VSYNCING;
866 if (vblank->vcount >= minfo->fbcon.var.yres)
867 vblank->flags |= FB_VBLANK_VBLANKING;
868 if (test_bit(0, &minfo->irq_flags)) {
869 vblank->flags |= FB_VBLANK_HAVE_COUNT;
870
871
872 vblank->count = minfo->crtc1.vsync.cnt;
873 }
874 return 0;
875}
876
877static struct matrox_altout panellink_output = {
878 .name = "Panellink output",
879};
880
881static int matroxfb_ioctl(struct fb_info *info,
882 unsigned int cmd, unsigned long arg)
883{
884 void __user *argp = (void __user *)arg;
885 struct matrox_fb_info *minfo = info2minfo(info);
886
887 DBG(__func__)
888
889 if (minfo->dead) {
890 return -ENXIO;
891 }
892
893 switch (cmd) {
894 case FBIOGET_VBLANK:
895 {
896 struct fb_vblank vblank;
897 int err;
898
899 err = matroxfb_get_vblank(minfo, &vblank);
900 if (err)
901 return err;
902 if (copy_to_user(argp, &vblank, sizeof(vblank)))
903 return -EFAULT;
904 return 0;
905 }
906 case FBIO_WAITFORVSYNC:
907 {
908 u_int32_t crt;
909
910 if (get_user(crt, (u_int32_t __user *)arg))
911 return -EFAULT;
912
913 return matroxfb_wait_for_sync(minfo, crt);
914 }
915 case MATROXFB_SET_OUTPUT_MODE:
916 {
917 struct matroxioc_output_mode mom;
918 struct matrox_altout *oproc;
919 int val;
920
921 if (copy_from_user(&mom, argp, sizeof(mom)))
922 return -EFAULT;
923 if (mom.output >= MATROXFB_MAX_OUTPUTS)
924 return -ENXIO;
925 down_read(&minfo->altout.lock);
926 oproc = minfo->outputs[mom.output].output;
927 if (!oproc) {
928 val = -ENXIO;
929 } else if (!oproc->verifymode) {
930 if (mom.mode == MATROXFB_OUTPUT_MODE_MONITOR) {
931 val = 0;
932 } else {
933 val = -EINVAL;
934 }
935 } else {
936 val = oproc->verifymode(minfo->outputs[mom.output].data, mom.mode);
937 }
938 if (!val) {
939 if (minfo->outputs[mom.output].mode != mom.mode) {
940 minfo->outputs[mom.output].mode = mom.mode;
941 val = 1;
942 }
943 }
944 up_read(&minfo->altout.lock);
945 if (val != 1)
946 return val;
947 switch (minfo->outputs[mom.output].src) {
948 case MATROXFB_SRC_CRTC1:
949 matroxfb_set_par(info);
950 break;
951 case MATROXFB_SRC_CRTC2:
952 {
953 struct matroxfb_dh_fb_info* crtc2;
954
955 down_read(&minfo->crtc2.lock);
956 crtc2 = minfo->crtc2.info;
957 if (crtc2)
958 crtc2->fbcon.fbops->fb_set_par(&crtc2->fbcon);
959 up_read(&minfo->crtc2.lock);
960 }
961 break;
962 }
963 return 0;
964 }
965 case MATROXFB_GET_OUTPUT_MODE:
966 {
967 struct matroxioc_output_mode mom;
968 struct matrox_altout *oproc;
969 int val;
970
971 if (copy_from_user(&mom, argp, sizeof(mom)))
972 return -EFAULT;
973 if (mom.output >= MATROXFB_MAX_OUTPUTS)
974 return -ENXIO;
975 down_read(&minfo->altout.lock);
976 oproc = minfo->outputs[mom.output].output;
977 if (!oproc) {
978 val = -ENXIO;
979 } else {
980 mom.mode = minfo->outputs[mom.output].mode;
981 val = 0;
982 }
983 up_read(&minfo->altout.lock);
984 if (val)
985 return val;
986 if (copy_to_user(argp, &mom, sizeof(mom)))
987 return -EFAULT;
988 return 0;
989 }
990 case MATROXFB_SET_OUTPUT_CONNECTION:
991 {
992 u_int32_t tmp;
993 int i;
994 int changes;
995
996 if (copy_from_user(&tmp, argp, sizeof(tmp)))
997 return -EFAULT;
998 for (i = 0; i < 32; i++) {
999 if (tmp & (1 << i)) {
1000 if (i >= MATROXFB_MAX_OUTPUTS)
1001 return -ENXIO;
1002 if (!minfo->outputs[i].output)
1003 return -ENXIO;
1004 switch (minfo->outputs[i].src) {
1005 case MATROXFB_SRC_NONE:
1006 case MATROXFB_SRC_CRTC1:
1007 break;
1008 default:
1009 return -EBUSY;
1010 }
1011 }
1012 }
1013 if (minfo->devflags.panellink) {
1014 if (tmp & MATROXFB_OUTPUT_CONN_DFP) {
1015 if (tmp & MATROXFB_OUTPUT_CONN_SECONDARY)
1016 return -EINVAL;
1017 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1018 if (minfo->outputs[i].src == MATROXFB_SRC_CRTC2) {
1019 return -EBUSY;
1020 }
1021 }
1022 }
1023 }
1024 changes = 0;
1025 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1026 if (tmp & (1 << i)) {
1027 if (minfo->outputs[i].src != MATROXFB_SRC_CRTC1) {
1028 changes = 1;
1029 minfo->outputs[i].src = MATROXFB_SRC_CRTC1;
1030 }
1031 } else if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
1032 changes = 1;
1033 minfo->outputs[i].src = MATROXFB_SRC_NONE;
1034 }
1035 }
1036 if (!changes)
1037 return 0;
1038 matroxfb_set_par(info);
1039 return 0;
1040 }
1041 case MATROXFB_GET_OUTPUT_CONNECTION:
1042 {
1043 u_int32_t conn = 0;
1044 int i;
1045
1046 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1047 if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
1048 conn |= 1 << i;
1049 }
1050 }
1051 if (put_user(conn, (u_int32_t __user *)arg))
1052 return -EFAULT;
1053 return 0;
1054 }
1055 case MATROXFB_GET_AVAILABLE_OUTPUTS:
1056 {
1057 u_int32_t conn = 0;
1058 int i;
1059
1060 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1061 if (minfo->outputs[i].output) {
1062 switch (minfo->outputs[i].src) {
1063 case MATROXFB_SRC_NONE:
1064 case MATROXFB_SRC_CRTC1:
1065 conn |= 1 << i;
1066 break;
1067 }
1068 }
1069 }
1070 if (minfo->devflags.panellink) {
1071 if (conn & MATROXFB_OUTPUT_CONN_DFP)
1072 conn &= ~MATROXFB_OUTPUT_CONN_SECONDARY;
1073 if (conn & MATROXFB_OUTPUT_CONN_SECONDARY)
1074 conn &= ~MATROXFB_OUTPUT_CONN_DFP;
1075 }
1076 if (put_user(conn, (u_int32_t __user *)arg))
1077 return -EFAULT;
1078 return 0;
1079 }
1080 case MATROXFB_GET_ALL_OUTPUTS:
1081 {
1082 u_int32_t conn = 0;
1083 int i;
1084
1085 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1086 if (minfo->outputs[i].output) {
1087 conn |= 1 << i;
1088 }
1089 }
1090 if (put_user(conn, (u_int32_t __user *)arg))
1091 return -EFAULT;
1092 return 0;
1093 }
1094 case VIDIOC_QUERYCAP:
1095 {
1096 struct v4l2_capability r;
1097
1098 memset(&r, 0, sizeof(r));
1099 strcpy(r.driver, "matroxfb");
1100 strcpy(r.card, "Matrox");
1101 sprintf(r.bus_info, "PCI:%s", pci_name(minfo->pcidev));
1102 r.version = KERNEL_VERSION(1,0,0);
1103 r.capabilities = V4L2_CAP_VIDEO_OUTPUT;
1104 if (copy_to_user(argp, &r, sizeof(r)))
1105 return -EFAULT;
1106 return 0;
1107
1108 }
1109 case VIDIOC_QUERYCTRL:
1110 {
1111 struct v4l2_queryctrl qctrl;
1112 int err;
1113
1114 if (copy_from_user(&qctrl, argp, sizeof(qctrl)))
1115 return -EFAULT;
1116
1117 down_read(&minfo->altout.lock);
1118 if (!minfo->outputs[1].output) {
1119 err = -ENXIO;
1120 } else if (minfo->outputs[1].output->getqueryctrl) {
1121 err = minfo->outputs[1].output->getqueryctrl(minfo->outputs[1].data, &qctrl);
1122 } else {
1123 err = -EINVAL;
1124 }
1125 up_read(&minfo->altout.lock);
1126 if (err >= 0 &&
1127 copy_to_user(argp, &qctrl, sizeof(qctrl)))
1128 return -EFAULT;
1129 return err;
1130 }
1131 case VIDIOC_G_CTRL:
1132 {
1133 struct v4l2_control ctrl;
1134 int err;
1135
1136 if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
1137 return -EFAULT;
1138
1139 down_read(&minfo->altout.lock);
1140 if (!minfo->outputs[1].output) {
1141 err = -ENXIO;
1142 } else if (minfo->outputs[1].output->getctrl) {
1143 err = minfo->outputs[1].output->getctrl(minfo->outputs[1].data, &ctrl);
1144 } else {
1145 err = -EINVAL;
1146 }
1147 up_read(&minfo->altout.lock);
1148 if (err >= 0 &&
1149 copy_to_user(argp, &ctrl, sizeof(ctrl)))
1150 return -EFAULT;
1151 return err;
1152 }
1153 case VIDIOC_S_CTRL:
1154 {
1155 struct v4l2_control ctrl;
1156 int err;
1157
1158 if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
1159 return -EFAULT;
1160
1161 down_read(&minfo->altout.lock);
1162 if (!minfo->outputs[1].output) {
1163 err = -ENXIO;
1164 } else if (minfo->outputs[1].output->setctrl) {
1165 err = minfo->outputs[1].output->setctrl(minfo->outputs[1].data, &ctrl);
1166 } else {
1167 err = -EINVAL;
1168 }
1169 up_read(&minfo->altout.lock);
1170 return err;
1171 }
1172 }
1173 return -ENOTTY;
1174}
1175
1176
1177
1178static int matroxfb_blank(int blank, struct fb_info *info)
1179{
1180 int seq;
1181 int crtc;
1182 CRITFLAGS
1183 struct matrox_fb_info *minfo = info2minfo(info);
1184
1185 DBG(__func__)
1186
1187 if (minfo->dead)
1188 return 1;
1189
1190 switch (blank) {
1191 case FB_BLANK_NORMAL: seq = 0x20; crtc = 0x00; break;
1192 case FB_BLANK_VSYNC_SUSPEND: seq = 0x20; crtc = 0x10; break;
1193 case FB_BLANK_HSYNC_SUSPEND: seq = 0x20; crtc = 0x20; break;
1194 case FB_BLANK_POWERDOWN: seq = 0x20; crtc = 0x30; break;
1195 default: seq = 0x00; crtc = 0x00; break;
1196 }
1197
1198 CRITBEGIN
1199
1200 mga_outb(M_SEQ_INDEX, 1);
1201 mga_outb(M_SEQ_DATA, (mga_inb(M_SEQ_DATA) & ~0x20) | seq);
1202 mga_outb(M_EXTVGA_INDEX, 1);
1203 mga_outb(M_EXTVGA_DATA, (mga_inb(M_EXTVGA_DATA) & ~0x30) | crtc);
1204
1205 CRITEND
1206 return 0;
1207}
1208
1209static struct fb_ops matroxfb_ops = {
1210 .owner = THIS_MODULE,
1211 .fb_open = matroxfb_open,
1212 .fb_release = matroxfb_release,
1213 .fb_check_var = matroxfb_check_var,
1214 .fb_set_par = matroxfb_set_par,
1215 .fb_setcolreg = matroxfb_setcolreg,
1216 .fb_pan_display =matroxfb_pan_display,
1217 .fb_blank = matroxfb_blank,
1218 .fb_ioctl = matroxfb_ioctl,
1219
1220
1221
1222
1223};
1224
1225#define RSDepth(X) (((X) >> 8) & 0x0F)
1226#define RS8bpp 0x1
1227#define RS15bpp 0x2
1228#define RS16bpp 0x3
1229#define RS32bpp 0x4
1230#define RS4bpp 0x5
1231#define RS24bpp 0x6
1232#define RSText 0x7
1233#define RSText8 0x8
1234
1235static struct { struct fb_bitfield red, green, blue, transp; int bits_per_pixel; } colors[] = {
1236 { { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 8 },
1237 { { 10, 5, 0}, { 5, 5, 0}, { 0, 5, 0}, { 15, 1, 0}, 16 },
1238 { { 11, 5, 0}, { 5, 6, 0}, { 0, 5, 0}, { 0, 0, 0}, 16 },
1239 { { 16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 24, 8, 0}, 32 },
1240 { { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 4 },
1241 { { 16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 24 },
1242 { { 0, 6, 0}, { 0, 6, 0}, { 0, 6, 0}, { 0, 0, 0}, 0 },
1243 { { 0, 6, 0}, { 0, 6, 0}, { 0, 6, 0}, { 0, 0, 0}, 0 },
1244};
1245
1246
1247static unsigned int mem;
1248static int option_precise_width = 1;
1249static int inv24;
1250static int cross4MB = -1;
1251static int disabled;
1252static int noaccel;
1253static int nopan;
1254static int no_pci_retry;
1255static int novga;
1256static int nobios;
1257static int noinit = 1;
1258static int inverse;
1259static int sgram;
1260#ifdef CONFIG_MTRR
1261static int mtrr = 1;
1262#endif
1263static int grayscale;
1264static int dev = -1;
1265static unsigned int vesa = ~0;
1266static int depth = -1;
1267static unsigned int xres;
1268static unsigned int yres;
1269static unsigned int upper = ~0;
1270static unsigned int lower = ~0;
1271static unsigned int vslen;
1272static unsigned int left = ~0;
1273static unsigned int right = ~0;
1274static unsigned int hslen;
1275static unsigned int pixclock;
1276static int sync = -1;
1277static unsigned int fv;
1278static unsigned int fh;
1279static unsigned int maxclk;
1280static int dfp;
1281static int dfp_type = -1;
1282static int memtype = -1;
1283static char outputs[8];
1284
1285#ifndef MODULE
1286static char videomode[64];
1287#endif
1288
1289static int matroxfb_getmemory(struct matrox_fb_info *minfo,
1290 unsigned int maxSize, unsigned int *realSize)
1291{
1292 vaddr_t vm;
1293 unsigned int offs;
1294 unsigned int offs2;
1295 unsigned char orig;
1296 unsigned char bytes[32];
1297 unsigned char* tmp;
1298
1299 DBG(__func__)
1300
1301 vm = minfo->video.vbase;
1302 maxSize &= ~0x1FFFFF;
1303
1304 if (maxSize < 0x0200000) return 0;
1305 if (maxSize > 0x2000000) maxSize = 0x2000000;
1306
1307 mga_outb(M_EXTVGA_INDEX, 0x03);
1308 orig = mga_inb(M_EXTVGA_DATA);
1309 mga_outb(M_EXTVGA_DATA, orig | 0x80);
1310
1311 tmp = bytes;
1312 for (offs = 0x100000; offs < maxSize; offs += 0x200000)
1313 *tmp++ = mga_readb(vm, offs);
1314 for (offs = 0x100000; offs < maxSize; offs += 0x200000)
1315 mga_writeb(vm, offs, 0x02);
1316 mga_outb(M_CACHEFLUSH, 0x00);
1317 for (offs = 0x100000; offs < maxSize; offs += 0x200000) {
1318 if (mga_readb(vm, offs) != 0x02)
1319 break;
1320 mga_writeb(vm, offs, mga_readb(vm, offs) - 0x02);
1321 if (mga_readb(vm, offs))
1322 break;
1323 }
1324 tmp = bytes;
1325 for (offs2 = 0x100000; offs2 < maxSize; offs2 += 0x200000)
1326 mga_writeb(vm, offs2, *tmp++);
1327
1328 mga_outb(M_EXTVGA_INDEX, 0x03);
1329 mga_outb(M_EXTVGA_DATA, orig);
1330
1331 *realSize = offs - 0x100000;
1332#ifdef CONFIG_FB_MATROX_MILLENIUM
1333 minfo->interleave = !(!isMillenium(minfo) || ((offs - 0x100000) & 0x3FFFFF));
1334#endif
1335 return 1;
1336}
1337
1338struct video_board {
1339 int maxvram;
1340 int maxdisplayable;
1341 int accelID;
1342 struct matrox_switch* lowlevel;
1343 };
1344#ifdef CONFIG_FB_MATROX_MILLENIUM
1345static struct video_board vbMillennium = {0x0800000, 0x0800000, FB_ACCEL_MATROX_MGA2064W, &matrox_millennium};
1346static struct video_board vbMillennium2 = {0x1000000, 0x0800000, FB_ACCEL_MATROX_MGA2164W, &matrox_millennium};
1347static struct video_board vbMillennium2A = {0x1000000, 0x0800000, FB_ACCEL_MATROX_MGA2164W_AGP, &matrox_millennium};
1348#endif
1349#ifdef CONFIG_FB_MATROX_MYSTIQUE
1350static struct video_board vbMystique = {0x0800000, 0x0800000, FB_ACCEL_MATROX_MGA1064SG, &matrox_mystique};
1351#endif
1352#ifdef CONFIG_FB_MATROX_G
1353static struct video_board vbG100 = {0x0800000, 0x0800000, FB_ACCEL_MATROX_MGAG100, &matrox_G100};
1354static struct video_board vbG200 = {0x1000000, 0x1000000, FB_ACCEL_MATROX_MGAG200, &matrox_G100};
1355
1356
1357static struct video_board vbG400 = {0x2000000, 0x1000000, FB_ACCEL_MATROX_MGAG400, &matrox_G100};
1358#endif
1359
1360#define DEVF_VIDEO64BIT 0x0001
1361#define DEVF_SWAPS 0x0002
1362#define DEVF_SRCORG 0x0004
1363#define DEVF_DUALHEAD 0x0008
1364#define DEVF_CROSS4MB 0x0010
1365#define DEVF_TEXT4B 0x0020
1366
1367
1368#define DEVF_SUPPORT32MB 0x0100
1369#define DEVF_ANY_VXRES 0x0200
1370#define DEVF_TEXT16B 0x0400
1371#define DEVF_CRTC2 0x0800
1372#define DEVF_MAVEN_CAPABLE 0x1000
1373#define DEVF_PANELLINK_CAPABLE 0x2000
1374#define DEVF_G450DAC 0x4000
1375
1376#define DEVF_GCORE (DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB)
1377#define DEVF_G2CORE (DEVF_GCORE | DEVF_ANY_VXRES | DEVF_MAVEN_CAPABLE | DEVF_PANELLINK_CAPABLE | DEVF_SRCORG | DEVF_DUALHEAD)
1378#define DEVF_G100 (DEVF_GCORE)
1379#define DEVF_G200 (DEVF_G2CORE)
1380#define DEVF_G400 (DEVF_G2CORE | DEVF_SUPPORT32MB | DEVF_TEXT16B | DEVF_CRTC2)
1381
1382#define DEVF_G450 (DEVF_GCORE | DEVF_ANY_VXRES | DEVF_SUPPORT32MB | DEVF_TEXT16B | DEVF_CRTC2 | DEVF_G450DAC | DEVF_SRCORG | DEVF_DUALHEAD)
1383#define DEVF_G550 (DEVF_G450)
1384
1385static struct board {
1386 unsigned short vendor, device, rev, svid, sid;
1387 unsigned int flags;
1388 unsigned int maxclk;
1389 enum mga_chip chip;
1390 struct video_board* base;
1391 const char* name;
1392 } dev_list[] = {
1393#ifdef CONFIG_FB_MATROX_MILLENIUM
1394 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL, 0xFF,
1395 0, 0,
1396 DEVF_TEXT4B,
1397 230000,
1398 MGA_2064,
1399 &vbMillennium,
1400 "Millennium (PCI)"},
1401 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2, 0xFF,
1402 0, 0,
1403 DEVF_SWAPS,
1404 220000,
1405 MGA_2164,
1406 &vbMillennium2,
1407 "Millennium II (PCI)"},
1408 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2_AGP, 0xFF,
1409 0, 0,
1410 DEVF_SWAPS,
1411 250000,
1412 MGA_2164,
1413 &vbMillennium2A,
1414 "Millennium II (AGP)"},
1415#endif
1416#ifdef CONFIG_FB_MATROX_MYSTIQUE
1417 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0x02,
1418 0, 0,
1419 DEVF_VIDEO64BIT | DEVF_CROSS4MB,
1420 180000,
1421 MGA_1064,
1422 &vbMystique,
1423 "Mystique (PCI)"},
1424 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0xFF,
1425 0, 0,
1426 DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB,
1427 220000,
1428 MGA_1164,
1429 &vbMystique,
1430 "Mystique 220 (PCI)"},
1431 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS_AGP, 0x02,
1432 0, 0,
1433 DEVF_VIDEO64BIT | DEVF_CROSS4MB,
1434 180000,
1435 MGA_1064,
1436 &vbMystique,
1437 "Mystique (AGP)"},
1438 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS_AGP, 0xFF,
1439 0, 0,
1440 DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB,
1441 220000,
1442 MGA_1164,
1443 &vbMystique,
1444 "Mystique 220 (AGP)"},
1445#endif
1446#ifdef CONFIG_FB_MATROX_G
1447 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_MM, 0xFF,
1448 0, 0,
1449 DEVF_G100,
1450 230000,
1451 MGA_G100,
1452 &vbG100,
1453 "MGA-G100 (PCI)"},
1454 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_AGP, 0xFF,
1455 0, 0,
1456 DEVF_G100,
1457 230000,
1458 MGA_G100,
1459 &vbG100,
1460 "MGA-G100 (AGP)"},
1461 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, 0xFF,
1462 0, 0,
1463 DEVF_G200,
1464 250000,
1465 MGA_G200,
1466 &vbG200,
1467 "MGA-G200 (PCI)"},
1468 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1469 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_GENERIC,
1470 DEVF_G200,
1471 220000,
1472 MGA_G200,
1473 &vbG200,
1474 "MGA-G200 (AGP)"},
1475 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1476 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP,
1477 DEVF_G200,
1478 230000,
1479 MGA_G200,
1480 &vbG200,
1481 "Mystique G200 (AGP)"},
1482 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1483 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MILLENIUM_G200_AGP,
1484 DEVF_G200,
1485 250000,
1486 MGA_G200,
1487 &vbG200,
1488 "Millennium G200 (AGP)"},
1489 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1490 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MARVEL_G200_AGP,
1491 DEVF_G200,
1492 230000,
1493 MGA_G200,
1494 &vbG200,
1495 "Marvel G200 (AGP)"},
1496 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1497 PCI_SS_VENDOR_ID_SIEMENS_NIXDORF, PCI_SS_ID_SIEMENS_MGA_G200_AGP,
1498 DEVF_G200,
1499 230000,
1500 MGA_G200,
1501 &vbG200,
1502 "MGA-G200 (AGP)"},
1503 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1504 0, 0,
1505 DEVF_G200,
1506 230000,
1507 MGA_G200,
1508 &vbG200,
1509 "G200 (AGP)"},
1510 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0x80,
1511 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP,
1512 DEVF_G400,
1513 360000,
1514 MGA_G400,
1515 &vbG400,
1516 "Millennium G400 MAX (AGP)"},
1517 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0x80,
1518 0, 0,
1519 DEVF_G400,
1520 300000,
1521 MGA_G400,
1522 &vbG400,
1523 "G400 (AGP)"},
1524 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0xFF,
1525 0, 0,
1526 DEVF_G450,
1527 360000,
1528 MGA_G450,
1529 &vbG400,
1530 "G450"},
1531 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550, 0xFF,
1532 0, 0,
1533 DEVF_G550,
1534 360000,
1535 MGA_G550,
1536 &vbG400,
1537 "G550"},
1538#endif
1539 {0, 0, 0xFF,
1540 0, 0,
1541 0,
1542 0,
1543 0,
1544 NULL,
1545 NULL}};
1546
1547#ifndef MODULE
1548static struct fb_videomode defaultmode = {
1549
1550 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
1551 0, FB_VMODE_NONINTERLACED
1552};
1553#endif
1554
1555static int hotplug = 0;
1556
1557static void setDefaultOutputs(struct matrox_fb_info *minfo)
1558{
1559 unsigned int i;
1560 const char* ptr;
1561
1562 minfo->outputs[0].default_src = MATROXFB_SRC_CRTC1;
1563 if (minfo->devflags.g450dac) {
1564 minfo->outputs[1].default_src = MATROXFB_SRC_CRTC1;
1565 minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
1566 } else if (dfp) {
1567 minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
1568 }
1569 ptr = outputs;
1570 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1571 char c = *ptr++;
1572
1573 if (c == 0) {
1574 break;
1575 }
1576 if (c == '0') {
1577 minfo->outputs[i].default_src = MATROXFB_SRC_NONE;
1578 } else if (c == '1') {
1579 minfo->outputs[i].default_src = MATROXFB_SRC_CRTC1;
1580 } else if (c == '2' && minfo->devflags.crtc2) {
1581 minfo->outputs[i].default_src = MATROXFB_SRC_CRTC2;
1582 } else {
1583 printk(KERN_ERR "matroxfb: Unknown outputs setting\n");
1584 break;
1585 }
1586 }
1587
1588 outputs[0] = 0;
1589}
1590
1591static int initMatrox2(struct matrox_fb_info *minfo, struct board *b)
1592{
1593 unsigned long ctrlptr_phys = 0;
1594 unsigned long video_base_phys = 0;
1595 unsigned int memsize;
1596 int err;
1597
1598 static struct pci_device_id intel_82437[] = {
1599 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437) },
1600 { },
1601 };
1602
1603 DBG(__func__)
1604
1605
1606 vesafb_defined.accel_flags = FB_ACCELF_TEXT;
1607
1608 minfo->hw_switch = b->base->lowlevel;
1609 minfo->devflags.accelerator = b->base->accelID;
1610 minfo->max_pixel_clock = b->maxclk;
1611
1612 printk(KERN_INFO "matroxfb: Matrox %s detected\n", b->name);
1613 minfo->capable.plnwt = 1;
1614 minfo->chip = b->chip;
1615 minfo->capable.srcorg = b->flags & DEVF_SRCORG;
1616 minfo->devflags.video64bits = b->flags & DEVF_VIDEO64BIT;
1617 if (b->flags & DEVF_TEXT4B) {
1618 minfo->devflags.vgastep = 4;
1619 minfo->devflags.textmode = 4;
1620 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
1621 } else if (b->flags & DEVF_TEXT16B) {
1622 minfo->devflags.vgastep = 16;
1623 minfo->devflags.textmode = 1;
1624 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
1625 } else {
1626 minfo->devflags.vgastep = 8;
1627 minfo->devflags.textmode = 1;
1628 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP8;
1629 }
1630 minfo->devflags.support32MB = (b->flags & DEVF_SUPPORT32MB) != 0;
1631 minfo->devflags.precise_width = !(b->flags & DEVF_ANY_VXRES);
1632 minfo->devflags.crtc2 = (b->flags & DEVF_CRTC2) != 0;
1633 minfo->devflags.maven_capable = (b->flags & DEVF_MAVEN_CAPABLE) != 0;
1634 minfo->devflags.dualhead = (b->flags & DEVF_DUALHEAD) != 0;
1635 minfo->devflags.dfp_type = dfp_type;
1636 minfo->devflags.g450dac = (b->flags & DEVF_G450DAC) != 0;
1637 minfo->devflags.textstep = minfo->devflags.vgastep * minfo->devflags.textmode;
1638 minfo->devflags.textvram = 65536 / minfo->devflags.textmode;
1639 setDefaultOutputs(minfo);
1640 if (b->flags & DEVF_PANELLINK_CAPABLE) {
1641 minfo->outputs[2].data = minfo;
1642 minfo->outputs[2].output = &panellink_output;
1643 minfo->outputs[2].src = minfo->outputs[2].default_src;
1644 minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
1645 minfo->devflags.panellink = 1;
1646 }
1647
1648 if (minfo->capable.cross4MB < 0)
1649 minfo->capable.cross4MB = b->flags & DEVF_CROSS4MB;
1650 if (b->flags & DEVF_SWAPS) {
1651 ctrlptr_phys = pci_resource_start(minfo->pcidev, 1);
1652 video_base_phys = pci_resource_start(minfo->pcidev, 0);
1653 minfo->devflags.fbResource = PCI_BASE_ADDRESS_0;
1654 } else {
1655 ctrlptr_phys = pci_resource_start(minfo->pcidev, 0);
1656 video_base_phys = pci_resource_start(minfo->pcidev, 1);
1657 minfo->devflags.fbResource = PCI_BASE_ADDRESS_1;
1658 }
1659 err = -EINVAL;
1660 if (!ctrlptr_phys) {
1661 printk(KERN_ERR "matroxfb: control registers are not available, matroxfb disabled\n");
1662 goto fail;
1663 }
1664 if (!video_base_phys) {
1665 printk(KERN_ERR "matroxfb: video RAM is not available in PCI address space, matroxfb disabled\n");
1666 goto fail;
1667 }
1668 memsize = b->base->maxvram;
1669 if (!request_mem_region(ctrlptr_phys, 16384, "matroxfb MMIO")) {
1670 goto fail;
1671 }
1672 if (!request_mem_region(video_base_phys, memsize, "matroxfb FB")) {
1673 goto failCtrlMR;
1674 }
1675 minfo->video.len_maximum = memsize;
1676
1677 if (mem < 1024) mem *= 1024;
1678 if (mem < 0x00100000) mem *= 1024;
1679
1680 if (mem && (mem < memsize))
1681 memsize = mem;
1682 err = -ENOMEM;
1683 if (mga_ioremap(ctrlptr_phys, 16384, MGA_IOREMAP_MMIO, &minfo->mmio.vbase)) {
1684 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, 16384), matroxfb disabled\n", ctrlptr_phys);
1685 goto failVideoMR;
1686 }
1687 minfo->mmio.base = ctrlptr_phys;
1688 minfo->mmio.len = 16384;
1689 minfo->video.base = video_base_phys;
1690 if (mga_ioremap(video_base_phys, memsize, MGA_IOREMAP_FB, &minfo->video.vbase)) {
1691 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, %d), matroxfb disabled\n",
1692 video_base_phys, memsize);
1693 goto failCtrlIO;
1694 }
1695 {
1696 u_int32_t cmd;
1697 u_int32_t mga_option;
1698
1699 pci_read_config_dword(minfo->pcidev, PCI_OPTION_REG, &mga_option);
1700 pci_read_config_dword(minfo->pcidev, PCI_COMMAND, &cmd);
1701 mga_option &= 0x7FFFFFFF;
1702 mga_option |= MX_OPTION_BSWAP;
1703
1704 cmd &= ~PCI_COMMAND_VGA_PALETTE;
1705 if (pci_dev_present(intel_82437)) {
1706 if (!(mga_option & 0x20000000) && !minfo->devflags.nopciretry) {
1707 printk(KERN_WARNING "matroxfb: Disabling PCI retries due to i82437 present\n");
1708 }
1709 mga_option |= 0x20000000;
1710 minfo->devflags.nopciretry = 1;
1711 }
1712 pci_write_config_dword(minfo->pcidev, PCI_COMMAND, cmd);
1713 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mga_option);
1714 minfo->hw.MXoptionReg = mga_option;
1715
1716
1717
1718 pci_write_config_dword(minfo->pcidev, PCI_MGA_INDEX, 0x00003C00);
1719 }
1720
1721 err = -ENXIO;
1722 matroxfb_read_pins(minfo);
1723 if (minfo->hw_switch->preinit(minfo)) {
1724 goto failVideoIO;
1725 }
1726
1727 err = -ENOMEM;
1728 if (!matroxfb_getmemory(minfo, memsize, &minfo->video.len) || !minfo->video.len) {
1729 printk(KERN_ERR "matroxfb: cannot determine memory size\n");
1730 goto failVideoIO;
1731 }
1732 minfo->devflags.ydstorg = 0;
1733
1734 minfo->video.base = video_base_phys;
1735 minfo->video.len_usable = minfo->video.len;
1736 if (minfo->video.len_usable > b->base->maxdisplayable)
1737 minfo->video.len_usable = b->base->maxdisplayable;
1738#ifdef CONFIG_MTRR
1739 if (mtrr) {
1740 minfo->mtrr.vram = mtrr_add(video_base_phys, minfo->video.len, MTRR_TYPE_WRCOMB, 1);
1741 minfo->mtrr.vram_valid = 1;
1742 printk(KERN_INFO "matroxfb: MTRR's turned on\n");
1743 }
1744#endif
1745
1746 if (!minfo->devflags.novga)
1747 request_region(0x3C0, 32, "matrox");
1748 matroxfb_g450_connect(minfo);
1749 minfo->hw_switch->reset(minfo);
1750
1751 minfo->fbcon.monspecs.hfmin = 0;
1752 minfo->fbcon.monspecs.hfmax = fh;
1753 minfo->fbcon.monspecs.vfmin = 0;
1754 minfo->fbcon.monspecs.vfmax = fv;
1755 minfo->fbcon.monspecs.dpms = 0;
1756
1757
1758 vesafb_defined.red = colors[depth-1].red;
1759 vesafb_defined.green = colors[depth-1].green;
1760 vesafb_defined.blue = colors[depth-1].blue;
1761 vesafb_defined.bits_per_pixel = colors[depth-1].bits_per_pixel;
1762 vesafb_defined.grayscale = grayscale;
1763 vesafb_defined.vmode = 0;
1764 if (noaccel)
1765 vesafb_defined.accel_flags &= ~FB_ACCELF_TEXT;
1766
1767 minfo->fbops = matroxfb_ops;
1768 minfo->fbcon.fbops = &minfo->fbops;
1769 minfo->fbcon.pseudo_palette = minfo->cmap;
1770
1771 minfo->fbcon.flags = hotplug ? FBINFO_FLAG_MODULE : FBINFO_FLAG_DEFAULT;
1772 minfo->fbcon.flags |= FBINFO_PARTIAL_PAN_OK |
1773 FBINFO_HWACCEL_COPYAREA |
1774 FBINFO_HWACCEL_FILLRECT |
1775 FBINFO_HWACCEL_IMAGEBLIT |
1776 FBINFO_HWACCEL_XPAN |
1777 FBINFO_HWACCEL_YPAN;
1778 minfo->video.len_usable &= PAGE_MASK;
1779 fb_alloc_cmap(&minfo->fbcon.cmap, 256, 1);
1780
1781#ifndef MODULE
1782
1783 if (!hotplug) {
1784 fb_find_mode(&vesafb_defined, &minfo->fbcon, videomode[0] ? videomode : NULL,
1785 NULL, 0, &defaultmode, vesafb_defined.bits_per_pixel);
1786 }
1787#endif
1788
1789
1790 if (hslen)
1791 vesafb_defined.hsync_len = hslen;
1792 if (vslen)
1793 vesafb_defined.vsync_len = vslen;
1794 if (left != ~0)
1795 vesafb_defined.left_margin = left;
1796 if (right != ~0)
1797 vesafb_defined.right_margin = right;
1798 if (upper != ~0)
1799 vesafb_defined.upper_margin = upper;
1800 if (lower != ~0)
1801 vesafb_defined.lower_margin = lower;
1802 if (xres)
1803 vesafb_defined.xres = xres;
1804 if (yres)
1805 vesafb_defined.yres = yres;
1806 if (sync != -1)
1807 vesafb_defined.sync = sync;
1808 else if (vesafb_defined.sync == ~0) {
1809 vesafb_defined.sync = 0;
1810 if (yres < 400)
1811 vesafb_defined.sync |= FB_SYNC_HOR_HIGH_ACT;
1812 else if (yres < 480)
1813 vesafb_defined.sync |= FB_SYNC_VERT_HIGH_ACT;
1814 }
1815
1816
1817 {
1818 unsigned int tmp;
1819
1820 if (fv) {
1821 tmp = fv * (vesafb_defined.upper_margin + vesafb_defined.yres
1822 + vesafb_defined.lower_margin + vesafb_defined.vsync_len);
1823 if ((tmp < fh) || (fh == 0)) fh = tmp;
1824 }
1825 if (fh) {
1826 tmp = fh * (vesafb_defined.left_margin + vesafb_defined.xres
1827 + vesafb_defined.right_margin + vesafb_defined.hsync_len);
1828 if ((tmp < maxclk) || (maxclk == 0)) maxclk = tmp;
1829 }
1830 tmp = (maxclk + 499) / 500;
1831 if (tmp) {
1832 tmp = (2000000000 + tmp) / tmp;
1833 if (tmp > pixclock) pixclock = tmp;
1834 }
1835 }
1836 if (pixclock) {
1837 if (pixclock < 2000)
1838 pixclock = 4000;
1839 if (pixclock > 1000000)
1840 pixclock = 1000000;
1841 vesafb_defined.pixclock = pixclock;
1842 }
1843
1844
1845#if defined(CONFIG_PPC_PMAC)
1846#ifndef MODULE
1847 if (machine_is(powermac)) {
1848 struct fb_var_screeninfo var;
1849 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1850 default_vmode = VMODE_640_480_60;
1851#ifdef CONFIG_NVRAM
1852 if (default_cmode == CMODE_NVRAM)
1853 default_cmode = nvram_read_byte(NV_CMODE);
1854#endif
1855 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
1856 default_cmode = CMODE_8;
1857 if (!mac_vmode_to_var(default_vmode, default_cmode, &var)) {
1858 var.accel_flags = vesafb_defined.accel_flags;
1859 var.xoffset = var.yoffset = 0;
1860
1861 vesafb_defined = var;
1862 }
1863 }
1864#endif
1865#endif
1866 vesafb_defined.xres_virtual = vesafb_defined.xres;
1867 if (nopan) {
1868 vesafb_defined.yres_virtual = vesafb_defined.yres;
1869 } else {
1870 vesafb_defined.yres_virtual = 65536;
1871
1872 }
1873 matroxfb_init_fix(minfo);
1874 minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase);
1875
1876 matroxfb_check_var(&vesafb_defined, &minfo->fbcon);
1877
1878
1879
1880
1881 minfo->fbcon.var = vesafb_defined;
1882 err = -EINVAL;
1883
1884 printk(KERN_INFO "matroxfb: %dx%dx%dbpp (virtual: %dx%d)\n",
1885 vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel,
1886 vesafb_defined.xres_virtual, vesafb_defined.yres_virtual);
1887 printk(KERN_INFO "matroxfb: framebuffer at 0x%lX, mapped to 0x%p, size %d\n",
1888 minfo->video.base, vaddr_va(minfo->video.vbase), minfo->video.len);
1889
1890
1891
1892
1893 minfo->fbcon.device = &minfo->pcidev->dev;
1894 if (register_framebuffer(&minfo->fbcon) < 0) {
1895 goto failVideoIO;
1896 }
1897 printk("fb%d: %s frame buffer device\n",
1898 minfo->fbcon.node, minfo->fbcon.fix.id);
1899
1900
1901
1902 if (!minfo->initialized) {
1903 printk(KERN_INFO "fb%d: initializing hardware\n",
1904 minfo->fbcon.node);
1905
1906
1907 vesafb_defined.activate |= FB_ACTIVATE_FORCE;
1908 fb_set_var(&minfo->fbcon, &vesafb_defined);
1909 }
1910
1911 return 0;
1912failVideoIO:;
1913 matroxfb_g450_shutdown(minfo);
1914 mga_iounmap(minfo->video.vbase);
1915failCtrlIO:;
1916 mga_iounmap(minfo->mmio.vbase);
1917failVideoMR:;
1918 release_mem_region(video_base_phys, minfo->video.len_maximum);
1919failCtrlMR:;
1920 release_mem_region(ctrlptr_phys, 16384);
1921fail:;
1922 return err;
1923}
1924
1925static LIST_HEAD(matroxfb_list);
1926static LIST_HEAD(matroxfb_driver_list);
1927
1928#define matroxfb_l(x) list_entry(x, struct matrox_fb_info, next_fb)
1929#define matroxfb_driver_l(x) list_entry(x, struct matroxfb_driver, node)
1930int matroxfb_register_driver(struct matroxfb_driver* drv) {
1931 struct matrox_fb_info* minfo;
1932
1933 list_add(&drv->node, &matroxfb_driver_list);
1934 for (minfo = matroxfb_l(matroxfb_list.next);
1935 minfo != matroxfb_l(&matroxfb_list);
1936 minfo = matroxfb_l(minfo->next_fb.next)) {
1937 void* p;
1938
1939 if (minfo->drivers_count == MATROXFB_MAX_FB_DRIVERS)
1940 continue;
1941 p = drv->probe(minfo);
1942 if (p) {
1943 minfo->drivers_data[minfo->drivers_count] = p;
1944 minfo->drivers[minfo->drivers_count++] = drv;
1945 }
1946 }
1947 return 0;
1948}
1949
1950void matroxfb_unregister_driver(struct matroxfb_driver* drv) {
1951 struct matrox_fb_info* minfo;
1952
1953 list_del(&drv->node);
1954 for (minfo = matroxfb_l(matroxfb_list.next);
1955 minfo != matroxfb_l(&matroxfb_list);
1956 minfo = matroxfb_l(minfo->next_fb.next)) {
1957 int i;
1958
1959 for (i = 0; i < minfo->drivers_count; ) {
1960 if (minfo->drivers[i] == drv) {
1961 if (drv && drv->remove)
1962 drv->remove(minfo, minfo->drivers_data[i]);
1963 minfo->drivers[i] = minfo->drivers[--minfo->drivers_count];
1964 minfo->drivers_data[i] = minfo->drivers_data[minfo->drivers_count];
1965 } else
1966 i++;
1967 }
1968 }
1969}
1970
1971static void matroxfb_register_device(struct matrox_fb_info* minfo) {
1972 struct matroxfb_driver* drv;
1973 int i = 0;
1974 list_add(&minfo->next_fb, &matroxfb_list);
1975 for (drv = matroxfb_driver_l(matroxfb_driver_list.next);
1976 drv != matroxfb_driver_l(&matroxfb_driver_list);
1977 drv = matroxfb_driver_l(drv->node.next)) {
1978 if (drv && drv->probe) {
1979 void *p = drv->probe(minfo);
1980 if (p) {
1981 minfo->drivers_data[i] = p;
1982 minfo->drivers[i++] = drv;
1983 if (i == MATROXFB_MAX_FB_DRIVERS)
1984 break;
1985 }
1986 }
1987 }
1988 minfo->drivers_count = i;
1989}
1990
1991static void matroxfb_unregister_device(struct matrox_fb_info* minfo) {
1992 int i;
1993
1994 list_del(&minfo->next_fb);
1995 for (i = 0; i < minfo->drivers_count; i++) {
1996 struct matroxfb_driver* drv = minfo->drivers[i];
1997
1998 if (drv && drv->remove)
1999 drv->remove(minfo, minfo->drivers_data[i]);
2000 }
2001}
2002
2003static int matroxfb_probe(struct pci_dev* pdev, const struct pci_device_id* dummy) {
2004 struct board* b;
2005 u_int16_t svid;
2006 u_int16_t sid;
2007 struct matrox_fb_info* minfo;
2008 int err;
2009 u_int32_t cmd;
2010 DBG(__func__)
2011
2012 svid = pdev->subsystem_vendor;
2013 sid = pdev->subsystem_device;
2014 for (b = dev_list; b->vendor; b++) {
2015 if ((b->vendor != pdev->vendor) || (b->device != pdev->device) || (b->rev < pdev->revision)) continue;
2016 if (b->svid)
2017 if ((b->svid != svid) || (b->sid != sid)) continue;
2018 break;
2019 }
2020
2021 if (!b->vendor)
2022 return -ENODEV;
2023 if (dev > 0) {
2024
2025 dev--;
2026 return -ENODEV;
2027 }
2028 pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
2029 if (pci_enable_device(pdev)) {
2030 return -1;
2031 }
2032
2033 minfo = kmalloc(sizeof(*minfo), GFP_KERNEL);
2034 if (!minfo)
2035 return -1;
2036 memset(minfo, 0, sizeof(*minfo));
2037
2038 minfo->pcidev = pdev;
2039 minfo->dead = 0;
2040 minfo->usecount = 0;
2041 minfo->userusecount = 0;
2042
2043 pci_set_drvdata(pdev, minfo);
2044
2045 minfo->devflags.memtype = memtype;
2046 if (memtype != -1)
2047 noinit = 0;
2048 if (cmd & PCI_COMMAND_MEMORY) {
2049 minfo->devflags.novga = novga;
2050 minfo->devflags.nobios = nobios;
2051 minfo->devflags.noinit = noinit;
2052
2053 novga = 1;
2054 nobios = 1;
2055 noinit = 0;
2056 } else {
2057 minfo->devflags.novga = 1;
2058 minfo->devflags.nobios = 1;
2059 minfo->devflags.noinit = 0;
2060 }
2061
2062 minfo->devflags.nopciretry = no_pci_retry;
2063 minfo->devflags.mga_24bpp_fix = inv24;
2064 minfo->devflags.precise_width = option_precise_width;
2065 minfo->devflags.sgram = sgram;
2066 minfo->capable.cross4MB = cross4MB;
2067
2068 spin_lock_init(&minfo->lock.DAC);
2069 spin_lock_init(&minfo->lock.accel);
2070 init_rwsem(&minfo->crtc2.lock);
2071 init_rwsem(&minfo->altout.lock);
2072 mutex_init(&minfo->fbcon.mm_lock);
2073 minfo->irq_flags = 0;
2074 init_waitqueue_head(&minfo->crtc1.vsync.wait);
2075 init_waitqueue_head(&minfo->crtc2.vsync.wait);
2076 minfo->crtc1.panpos = -1;
2077
2078 err = initMatrox2(minfo, b);
2079 if (!err) {
2080 matroxfb_register_device(minfo);
2081 return 0;
2082 }
2083 kfree(minfo);
2084 return -1;
2085}
2086
2087static void pci_remove_matrox(struct pci_dev* pdev) {
2088 struct matrox_fb_info* minfo;
2089
2090 minfo = pci_get_drvdata(pdev);
2091 matroxfb_remove(minfo, 1);
2092}
2093
2094static struct pci_device_id matroxfb_devices[] = {
2095#ifdef CONFIG_FB_MATROX_MILLENIUM
2096 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL,
2097 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2098 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2,
2099 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2100 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2_AGP,
2101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2102#endif
2103#ifdef CONFIG_FB_MATROX_MYSTIQUE
2104 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS,
2105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2106#endif
2107#ifdef CONFIG_FB_MATROX_G
2108 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_MM,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2110 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_AGP,
2111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2112 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI,
2113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2114 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP,
2115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2116 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400,
2117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2118 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550,
2119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2120#endif
2121 {0, 0,
2122 0, 0, 0, 0, 0}
2123};
2124
2125MODULE_DEVICE_TABLE(pci, matroxfb_devices);
2126
2127
2128static struct pci_driver matroxfb_driver = {
2129 .name = "matroxfb",
2130 .id_table = matroxfb_devices,
2131 .probe = matroxfb_probe,
2132 .remove = pci_remove_matrox,
2133};
2134
2135
2136
2137#define RSResolution(X) ((X) & 0x0F)
2138#define RS640x400 1
2139#define RS640x480 2
2140#define RS800x600 3
2141#define RS1024x768 4
2142#define RS1280x1024 5
2143#define RS1600x1200 6
2144#define RS768x576 7
2145#define RS960x720 8
2146#define RS1152x864 9
2147#define RS1408x1056 10
2148#define RS640x350 11
2149#define RS1056x344 12
2150#define RS1056x400 13
2151#define RS1056x480 14
2152#define RSNoxNo 15
2153
2154static struct { int xres, yres, left, right, upper, lower, hslen, vslen, vfreq; } timmings[] __initdata = {
2155 { 640, 400, 48, 16, 39, 8, 96, 2, 70 },
2156 { 640, 480, 48, 16, 33, 10, 96, 2, 60 },
2157 { 800, 600, 144, 24, 28, 8, 112, 6, 60 },
2158 { 1024, 768, 160, 32, 30, 4, 128, 4, 60 },
2159 { 1280, 1024, 224, 32, 32, 4, 136, 4, 60 },
2160 { 1600, 1200, 272, 48, 32, 5, 152, 5, 60 },
2161 { 768, 576, 144, 16, 28, 6, 112, 4, 60 },
2162 { 960, 720, 144, 24, 28, 8, 112, 4, 60 },
2163 { 1152, 864, 192, 32, 30, 4, 128, 4, 60 },
2164 { 1408, 1056, 256, 40, 32, 5, 144, 5, 60 },
2165 { 640, 350, 48, 16, 39, 8, 96, 2, 70 },
2166 { 1056, 344, 96, 24, 59, 44, 160, 2, 70 },
2167 { 1056, 400, 96, 24, 39, 8, 160, 2, 70 },
2168 { 1056, 480, 96, 24, 36, 12, 160, 3, 60 },
2169 { 0, 0, ~0, ~0, ~0, ~0, 0, 0, 0 }
2170};
2171
2172#define RSCreate(X,Y) ((X) | ((Y) << 8))
2173static struct { unsigned int vesa; unsigned int info; } *RSptr, vesamap[] __initdata = {
2174
2175 { ~0, RSCreate(RSNoxNo, RS8bpp ) },
2176 { 0x101, RSCreate(RS640x480, RS8bpp ) },
2177 { 0x100, RSCreate(RS640x400, RS8bpp ) },
2178 { 0x180, RSCreate(RS768x576, RS8bpp ) },
2179 { 0x103, RSCreate(RS800x600, RS8bpp ) },
2180 { 0x188, RSCreate(RS960x720, RS8bpp ) },
2181 { 0x105, RSCreate(RS1024x768, RS8bpp ) },
2182 { 0x190, RSCreate(RS1152x864, RS8bpp ) },
2183 { 0x107, RSCreate(RS1280x1024, RS8bpp ) },
2184 { 0x198, RSCreate(RS1408x1056, RS8bpp ) },
2185 { 0x11C, RSCreate(RS1600x1200, RS8bpp ) },
2186 { 0x110, RSCreate(RS640x480, RS15bpp) },
2187 { 0x181, RSCreate(RS768x576, RS15bpp) },
2188 { 0x113, RSCreate(RS800x600, RS15bpp) },
2189 { 0x189, RSCreate(RS960x720, RS15bpp) },
2190 { 0x116, RSCreate(RS1024x768, RS15bpp) },
2191 { 0x191, RSCreate(RS1152x864, RS15bpp) },
2192 { 0x119, RSCreate(RS1280x1024, RS15bpp) },
2193 { 0x199, RSCreate(RS1408x1056, RS15bpp) },
2194 { 0x11D, RSCreate(RS1600x1200, RS15bpp) },
2195 { 0x111, RSCreate(RS640x480, RS16bpp) },
2196 { 0x182, RSCreate(RS768x576, RS16bpp) },
2197 { 0x114, RSCreate(RS800x600, RS16bpp) },
2198 { 0x18A, RSCreate(RS960x720, RS16bpp) },
2199 { 0x117, RSCreate(RS1024x768, RS16bpp) },
2200 { 0x192, RSCreate(RS1152x864, RS16bpp) },
2201 { 0x11A, RSCreate(RS1280x1024, RS16bpp) },
2202 { 0x19A, RSCreate(RS1408x1056, RS16bpp) },
2203 { 0x11E, RSCreate(RS1600x1200, RS16bpp) },
2204 { 0x1B2, RSCreate(RS640x480, RS24bpp) },
2205 { 0x184, RSCreate(RS768x576, RS24bpp) },
2206 { 0x1B5, RSCreate(RS800x600, RS24bpp) },
2207 { 0x18C, RSCreate(RS960x720, RS24bpp) },
2208 { 0x1B8, RSCreate(RS1024x768, RS24bpp) },
2209 { 0x194, RSCreate(RS1152x864, RS24bpp) },
2210 { 0x1BB, RSCreate(RS1280x1024, RS24bpp) },
2211 { 0x19C, RSCreate(RS1408x1056, RS24bpp) },
2212 { 0x1BF, RSCreate(RS1600x1200, RS24bpp) },
2213 { 0x112, RSCreate(RS640x480, RS32bpp) },
2214 { 0x183, RSCreate(RS768x576, RS32bpp) },
2215 { 0x115, RSCreate(RS800x600, RS32bpp) },
2216 { 0x18B, RSCreate(RS960x720, RS32bpp) },
2217 { 0x118, RSCreate(RS1024x768, RS32bpp) },
2218 { 0x193, RSCreate(RS1152x864, RS32bpp) },
2219 { 0x11B, RSCreate(RS1280x1024, RS32bpp) },
2220 { 0x19B, RSCreate(RS1408x1056, RS32bpp) },
2221 { 0x11F, RSCreate(RS1600x1200, RS32bpp) },
2222 { 0x010, RSCreate(RS640x350, RS4bpp ) },
2223 { 0x012, RSCreate(RS640x480, RS4bpp ) },
2224 { 0x102, RSCreate(RS800x600, RS4bpp ) },
2225 { 0x104, RSCreate(RS1024x768, RS4bpp ) },
2226 { 0x106, RSCreate(RS1280x1024, RS4bpp ) },
2227 { 0, 0 }};
2228
2229static void __init matroxfb_init_params(void) {
2230
2231 if (fh < 1000)
2232 fh *= 1000;
2233
2234 if (maxclk < 1000) maxclk *= 1000;
2235 if (maxclk < 1000000) maxclk *= 1000;
2236
2237 if (vesa != ~0)
2238 vesa &= 0x1DFF;
2239
2240
2241 for (RSptr = vesamap; RSptr->vesa; RSptr++) {
2242 if (RSptr->vesa == vesa) break;
2243 }
2244 if (!RSptr->vesa) {
2245 printk(KERN_ERR "Invalid vesa mode 0x%04X\n", vesa);
2246 RSptr = vesamap;
2247 }
2248 {
2249 int res = RSResolution(RSptr->info)-1;
2250 if (left == ~0)
2251 left = timmings[res].left;
2252 if (!xres)
2253 xres = timmings[res].xres;
2254 if (right == ~0)
2255 right = timmings[res].right;
2256 if (!hslen)
2257 hslen = timmings[res].hslen;
2258 if (upper == ~0)
2259 upper = timmings[res].upper;
2260 if (!yres)
2261 yres = timmings[res].yres;
2262 if (lower == ~0)
2263 lower = timmings[res].lower;
2264 if (!vslen)
2265 vslen = timmings[res].vslen;
2266 if (!(fv||fh||maxclk||pixclock))
2267 fv = timmings[res].vfreq;
2268 if (depth == -1)
2269 depth = RSDepth(RSptr->info);
2270 }
2271}
2272
2273static int __init matrox_init(void) {
2274 int err;
2275
2276 matroxfb_init_params();
2277 err = pci_register_driver(&matroxfb_driver);
2278 dev = -1;
2279 return err;
2280}
2281
2282
2283
2284static void __exit matrox_done(void) {
2285 pci_unregister_driver(&matroxfb_driver);
2286}
2287
2288#ifndef MODULE
2289
2290
2291
2292static int __init matroxfb_setup(char *options) {
2293 char *this_opt;
2294
2295 DBG(__func__)
2296
2297 if (!options || !*options)
2298 return 0;
2299
2300 while ((this_opt = strsep(&options, ",")) != NULL) {
2301 if (!*this_opt) continue;
2302
2303 dprintk("matroxfb_setup: option %s\n", this_opt);
2304
2305 if (!strncmp(this_opt, "dev:", 4))
2306 dev = simple_strtoul(this_opt+4, NULL, 0);
2307 else if (!strncmp(this_opt, "depth:", 6)) {
2308 switch (simple_strtoul(this_opt+6, NULL, 0)) {
2309 case 0: depth = RSText; break;
2310 case 4: depth = RS4bpp; break;
2311 case 8: depth = RS8bpp; break;
2312 case 15:depth = RS15bpp; break;
2313 case 16:depth = RS16bpp; break;
2314 case 24:depth = RS24bpp; break;
2315 case 32:depth = RS32bpp; break;
2316 default:
2317 printk(KERN_ERR "matroxfb: unsupported color depth\n");
2318 }
2319 } else if (!strncmp(this_opt, "xres:", 5))
2320 xres = simple_strtoul(this_opt+5, NULL, 0);
2321 else if (!strncmp(this_opt, "yres:", 5))
2322 yres = simple_strtoul(this_opt+5, NULL, 0);
2323 else if (!strncmp(this_opt, "vslen:", 6))
2324 vslen = simple_strtoul(this_opt+6, NULL, 0);
2325 else if (!strncmp(this_opt, "hslen:", 6))
2326 hslen = simple_strtoul(this_opt+6, NULL, 0);
2327 else if (!strncmp(this_opt, "left:", 5))
2328 left = simple_strtoul(this_opt+5, NULL, 0);
2329 else if (!strncmp(this_opt, "right:", 6))
2330 right = simple_strtoul(this_opt+6, NULL, 0);
2331 else if (!strncmp(this_opt, "upper:", 6))
2332 upper = simple_strtoul(this_opt+6, NULL, 0);
2333 else if (!strncmp(this_opt, "lower:", 6))
2334 lower = simple_strtoul(this_opt+6, NULL, 0);
2335 else if (!strncmp(this_opt, "pixclock:", 9))
2336 pixclock = simple_strtoul(this_opt+9, NULL, 0);
2337 else if (!strncmp(this_opt, "sync:", 5))
2338 sync = simple_strtoul(this_opt+5, NULL, 0);
2339 else if (!strncmp(this_opt, "vesa:", 5))
2340 vesa = simple_strtoul(this_opt+5, NULL, 0);
2341 else if (!strncmp(this_opt, "maxclk:", 7))
2342 maxclk = simple_strtoul(this_opt+7, NULL, 0);
2343 else if (!strncmp(this_opt, "fh:", 3))
2344 fh = simple_strtoul(this_opt+3, NULL, 0);
2345 else if (!strncmp(this_opt, "fv:", 3))
2346 fv = simple_strtoul(this_opt+3, NULL, 0);
2347 else if (!strncmp(this_opt, "mem:", 4))
2348 mem = simple_strtoul(this_opt+4, NULL, 0);
2349 else if (!strncmp(this_opt, "mode:", 5))
2350 strlcpy(videomode, this_opt+5, sizeof(videomode));
2351 else if (!strncmp(this_opt, "outputs:", 8))
2352 strlcpy(outputs, this_opt+8, sizeof(outputs));
2353 else if (!strncmp(this_opt, "dfp:", 4)) {
2354 dfp_type = simple_strtoul(this_opt+4, NULL, 0);
2355 dfp = 1;
2356 }
2357#ifdef CONFIG_PPC_PMAC
2358 else if (!strncmp(this_opt, "vmode:", 6)) {
2359 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
2360 if (vmode > 0 && vmode <= VMODE_MAX)
2361 default_vmode = vmode;
2362 } else if (!strncmp(this_opt, "cmode:", 6)) {
2363 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
2364 switch (cmode) {
2365 case 0:
2366 case 8:
2367 default_cmode = CMODE_8;
2368 break;
2369 case 15:
2370 case 16:
2371 default_cmode = CMODE_16;
2372 break;
2373 case 24:
2374 case 32:
2375 default_cmode = CMODE_32;
2376 break;
2377 }
2378 }
2379#endif
2380 else if (!strcmp(this_opt, "disabled"))
2381 disabled = 1;
2382 else if (!strcmp(this_opt, "enabled"))
2383 disabled = 0;
2384 else if (!strcmp(this_opt, "sgram"))
2385 sgram = 1;
2386 else if (!strcmp(this_opt, "sdram"))
2387 sgram = 0;
2388 else if (!strncmp(this_opt, "memtype:", 8))
2389 memtype = simple_strtoul(this_opt+8, NULL, 0);
2390 else {
2391 int value = 1;
2392
2393 if (!strncmp(this_opt, "no", 2)) {
2394 value = 0;
2395 this_opt += 2;
2396 }
2397 if (! strcmp(this_opt, "inverse"))
2398 inverse = value;
2399 else if (!strcmp(this_opt, "accel"))
2400 noaccel = !value;
2401 else if (!strcmp(this_opt, "pan"))
2402 nopan = !value;
2403 else if (!strcmp(this_opt, "pciretry"))
2404 no_pci_retry = !value;
2405 else if (!strcmp(this_opt, "vga"))
2406 novga = !value;
2407 else if (!strcmp(this_opt, "bios"))
2408 nobios = !value;
2409 else if (!strcmp(this_opt, "init"))
2410 noinit = !value;
2411#ifdef CONFIG_MTRR
2412 else if (!strcmp(this_opt, "mtrr"))
2413 mtrr = value;
2414#endif
2415 else if (!strcmp(this_opt, "inv24"))
2416 inv24 = value;
2417 else if (!strcmp(this_opt, "cross4MB"))
2418 cross4MB = value;
2419 else if (!strcmp(this_opt, "grayscale"))
2420 grayscale = value;
2421 else if (!strcmp(this_opt, "dfp"))
2422 dfp = value;
2423 else {
2424 strlcpy(videomode, this_opt, sizeof(videomode));
2425 }
2426 }
2427 }
2428 return 0;
2429}
2430
2431static int __initdata initialized = 0;
2432
2433static int __init matroxfb_init(void)
2434{
2435 char *option = NULL;
2436 int err = 0;
2437
2438 DBG(__func__)
2439
2440 if (fb_get_options("matroxfb", &option))
2441 return -ENODEV;
2442 matroxfb_setup(option);
2443
2444 if (disabled)
2445 return -ENXIO;
2446 if (!initialized) {
2447 initialized = 1;
2448 err = matrox_init();
2449 }
2450 hotplug = 1;
2451
2452 return err;
2453}
2454
2455module_init(matroxfb_init);
2456
2457#else
2458
2459
2460
2461MODULE_AUTHOR("(c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
2462MODULE_DESCRIPTION("Accelerated FBDev driver for Matrox Millennium/Mystique/G100/G200/G400/G450/G550");
2463MODULE_LICENSE("GPL");
2464
2465module_param(mem, int, 0);
2466MODULE_PARM_DESC(mem, "Size of available memory in MB, KB or B (2,4,8,12,16MB, default=autodetect)");
2467module_param(disabled, int, 0);
2468MODULE_PARM_DESC(disabled, "Disabled (0 or 1=disabled) (default=0)");
2469module_param(noaccel, int, 0);
2470MODULE_PARM_DESC(noaccel, "Do not use accelerating engine (0 or 1=disabled) (default=0)");
2471module_param(nopan, int, 0);
2472MODULE_PARM_DESC(nopan, "Disable pan on startup (0 or 1=disabled) (default=0)");
2473module_param(no_pci_retry, int, 0);
2474MODULE_PARM_DESC(no_pci_retry, "PCI retries enabled (0 or 1=disabled) (default=0)");
2475module_param(novga, int, 0);
2476MODULE_PARM_DESC(novga, "VGA I/O (0x3C0-0x3DF) disabled (0 or 1=disabled) (default=0)");
2477module_param(nobios, int, 0);
2478MODULE_PARM_DESC(nobios, "Disables ROM BIOS (0 or 1=disabled) (default=do not change BIOS state)");
2479module_param(noinit, int, 0);
2480MODULE_PARM_DESC(noinit, "Disables W/SG/SD-RAM and bus interface initialization (0 or 1=do not initialize) (default=0)");
2481module_param(memtype, int, 0);
2482MODULE_PARM_DESC(memtype, "Memory type for G200/G400 (see Documentation/fb/matroxfb.txt for explanation) (default=3 for G200, 0 for G400)");
2483#ifdef CONFIG_MTRR
2484module_param(mtrr, int, 0);
2485MODULE_PARM_DESC(mtrr, "This speeds up video memory accesses (0=disabled or 1) (default=1)");
2486#endif
2487module_param(sgram, int, 0);
2488MODULE_PARM_DESC(sgram, "Indicates that G100/G200/G400 has SGRAM memory (0=SDRAM, 1=SGRAM) (default=0)");
2489module_param(inv24, int, 0);
2490MODULE_PARM_DESC(inv24, "Inverts clock polarity for 24bpp and loop frequency > 100MHz (default=do not invert polarity)");
2491module_param(inverse, int, 0);
2492MODULE_PARM_DESC(inverse, "Inverse (0 or 1) (default=0)");
2493module_param(dev, int, 0);
2494MODULE_PARM_DESC(dev, "Multihead support, attach to device ID (0..N) (default=all working)");
2495module_param(vesa, int, 0);
2496MODULE_PARM_DESC(vesa, "Startup videomode (0x000-0x1FF) (default=0x101)");
2497module_param(xres, int, 0);
2498MODULE_PARM_DESC(xres, "Horizontal resolution (px), overrides xres from vesa (default=vesa)");
2499module_param(yres, int, 0);
2500MODULE_PARM_DESC(yres, "Vertical resolution (scans), overrides yres from vesa (default=vesa)");
2501module_param(upper, int, 0);
2502MODULE_PARM_DESC(upper, "Upper blank space (scans), overrides upper from vesa (default=vesa)");
2503module_param(lower, int, 0);
2504MODULE_PARM_DESC(lower, "Lower blank space (scans), overrides lower from vesa (default=vesa)");
2505module_param(vslen, int, 0);
2506MODULE_PARM_DESC(vslen, "Vertical sync length (scans), overrides lower from vesa (default=vesa)");
2507module_param(left, int, 0);
2508MODULE_PARM_DESC(left, "Left blank space (px), overrides left from vesa (default=vesa)");
2509module_param(right, int, 0);
2510MODULE_PARM_DESC(right, "Right blank space (px), overrides right from vesa (default=vesa)");
2511module_param(hslen, int, 0);
2512MODULE_PARM_DESC(hslen, "Horizontal sync length (px), overrides hslen from vesa (default=vesa)");
2513module_param(pixclock, int, 0);
2514MODULE_PARM_DESC(pixclock, "Pixelclock (ns), overrides pixclock from vesa (default=vesa)");
2515module_param(sync, int, 0);
2516MODULE_PARM_DESC(sync, "Sync polarity, overrides sync from vesa (default=vesa)");
2517module_param(depth, int, 0);
2518MODULE_PARM_DESC(depth, "Color depth (0=text,8,15,16,24,32) (default=vesa)");
2519module_param(maxclk, int, 0);
2520MODULE_PARM_DESC(maxclk, "Startup maximal clock, 0-999MHz, 1000-999999kHz, 1000000-INF Hz");
2521module_param(fh, int, 0);
2522MODULE_PARM_DESC(fh, "Startup horizontal frequency, 0-999kHz, 1000-INF Hz");
2523module_param(fv, int, 0);
2524MODULE_PARM_DESC(fv, "Startup vertical frequency, 0-INF Hz\n"
2525"You should specify \"fv:max_monitor_vsync,fh:max_monitor_hsync,maxclk:max_monitor_dotclock\"");
2526module_param(grayscale, int, 0);
2527MODULE_PARM_DESC(grayscale, "Sets display into grayscale. Works perfectly with paletized videomode (4, 8bpp), some limitations apply to 16, 24 and 32bpp videomodes (default=nograyscale)");
2528module_param(cross4MB, int, 0);
2529MODULE_PARM_DESC(cross4MB, "Specifies that 4MB boundary can be in middle of line. (default=autodetected)");
2530module_param(dfp, int, 0);
2531MODULE_PARM_DESC(dfp, "Specifies whether to use digital flat panel interface of G200/G400 (0 or 1) (default=0)");
2532module_param(dfp_type, int, 0);
2533MODULE_PARM_DESC(dfp_type, "Specifies DFP interface type (0 to 255) (default=read from hardware)");
2534module_param_string(outputs, outputs, sizeof(outputs), 0);
2535MODULE_PARM_DESC(outputs, "Specifies which CRTC is mapped to which output (string of up to three letters, consisting of 0 (disabled), 1 (CRTC1), 2 (CRTC2)) (default=111 for Gx50, 101 for G200/G400 with DFP, and 100 for all other devices)");
2536#ifdef CONFIG_PPC_PMAC
2537module_param_named(vmode, default_vmode, int, 0);
2538MODULE_PARM_DESC(vmode, "Specify the vmode mode number that should be used (640x480 default)");
2539module_param_named(cmode, default_cmode, int, 0);
2540MODULE_PARM_DESC(cmode, "Specify the video depth that should be used (8bit default)");
2541#endif
2542
2543int __init init_module(void){
2544
2545 DBG(__func__)
2546
2547 if (disabled)
2548 return -ENXIO;
2549
2550 if (depth == 0)
2551 depth = RSText;
2552 else if (depth == 4)
2553 depth = RS4bpp;
2554 else if (depth == 8)
2555 depth = RS8bpp;
2556 else if (depth == 15)
2557 depth = RS15bpp;
2558 else if (depth == 16)
2559 depth = RS16bpp;
2560 else if (depth == 24)
2561 depth = RS24bpp;
2562 else if (depth == 32)
2563 depth = RS32bpp;
2564 else if (depth != -1) {
2565 printk(KERN_ERR "matroxfb: depth %d is not supported, using default\n", depth);
2566 depth = -1;
2567 }
2568 matrox_init();
2569
2570 return 0;
2571}
2572#endif
2573
2574module_exit(matrox_done);
2575EXPORT_SYMBOL(matroxfb_register_driver);
2576EXPORT_SYMBOL(matroxfb_unregister_driver);
2577EXPORT_SYMBOL(matroxfb_wait_for_sync);
2578EXPORT_SYMBOL(matroxfb_enable_irq);
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