LXR linux/include/drm/drm

   1/*
   2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
   3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
   4 * Copyright (c) 2008 Red Hat Inc.
   5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
   6 * Copyright (c) 2007-2008 Intel Corporation
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a
   9 * copy of this software and associated documentation files (the "Software"),
  10 * to deal in the Software without restriction, including without limitation
  11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12 * and/or sell copies of the Software, and to permit persons to whom the
  13 * Software is furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  24 * IN THE SOFTWARE.
  25 */
  26
  27#ifndef _DRM_MODE_H
  28#define _DRM_MODE_H
  29
  30#define DRM_DISPLAY_INFO_LEN    32
  31#define DRM_CONNECTOR_NAME_LEN  32
  32#define DRM_DISPLAY_MODE_LEN    32
  33#define DRM_PROP_NAME_LEN       32
  34
  35#define DRM_MODE_TYPE_BUILTIN   (1<<0)
  36#define DRM_MODE_TYPE_CLOCK_C   ((1<<1) | DRM_MODE_TYPE_BUILTIN)
  37#define DRM_MODE_TYPE_CRTC_C    ((1<<2) | DRM_MODE_TYPE_BUILTIN)
  38#define DRM_MODE_TYPE_PREFERRED (1<<3)
  39#define DRM_MODE_TYPE_DEFAULT   (1<<4)
  40#define DRM_MODE_TYPE_USERDEF   (1<<5)
  41#define DRM_MODE_TYPE_DRIVER    (1<<6)
  42
  43/* Video mode flags */
  44/* bit compatible with the xorg definitions. */
  45#define DRM_MODE_FLAG_PHSYNC    (1<<0)
  46#define DRM_MODE_FLAG_NHSYNC    (1<<1)
  47#define DRM_MODE_FLAG_PVSYNC    (1<<2)
  48#define DRM_MODE_FLAG_NVSYNC    (1<<3)
  49#define DRM_MODE_FLAG_INTERLACE (1<<4)
  50#define DRM_MODE_FLAG_DBLSCAN   (1<<5)
  51#define DRM_MODE_FLAG_CSYNC     (1<<6)
  52#define DRM_MODE_FLAG_PCSYNC    (1<<7)
  53#define DRM_MODE_FLAG_NCSYNC    (1<<8)
  54#define DRM_MODE_FLAG_HSKEW     (1<<9) /* hskew provided */
  55#define DRM_MODE_FLAG_BCAST     (1<<10)
  56#define DRM_MODE_FLAG_PIXMUX    (1<<11)
  57#define DRM_MODE_FLAG_DBLCLK    (1<<12)
  58#define DRM_MODE_FLAG_CLKDIV2   (1<<13)
  59
  60/* DPMS flags */
  61/* bit compatible with the xorg definitions. */
  62#define DRM_MODE_DPMS_ON        0
  63#define DRM_MODE_DPMS_STANDBY   1
  64#define DRM_MODE_DPMS_SUSPEND   2
  65#define DRM_MODE_DPMS_OFF       3
  66
  67/* Scaling mode options */
  68#define DRM_MODE_SCALE_NONE             0 /* Unmodified timing (display or
  69                                             software can still scale) */
  70#define DRM_MODE_SCALE_FULLSCREEN       1 /* Full screen, ignore aspect */
  71#define DRM_MODE_SCALE_CENTER           2 /* Centered, no scaling */
  72#define DRM_MODE_SCALE_ASPECT           3 /* Full screen, preserve aspect */
  73
  74/* Dithering mode options */
  75#define DRM_MODE_DITHERING_OFF  0
  76#define DRM_MODE_DITHERING_ON   1
  77#define DRM_MODE_DITHERING_AUTO 2
  78
  79/* Dirty info options */
  80#define DRM_MODE_DIRTY_OFF      0
  81#define DRM_MODE_DIRTY_ON       1
  82#define DRM_MODE_DIRTY_ANNOTATE 2
  83
  84struct drm_mode_modeinfo {
  85        __u32 clock;
  86        __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
  87        __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
  88
  89        __u32 vrefresh;
  90
  91        __u32 flags;
  92        __u32 type;
  93        char name[DRM_DISPLAY_MODE_LEN];
  94};
  95
  96struct drm_mode_card_res {
  97        __u64 fb_id_ptr;
  98        __u64 crtc_id_ptr;
  99        __u64 connector_id_ptr;
 100        __u64 encoder_id_ptr;
 101        __u32 count_fbs;
 102        __u32 count_crtcs;
 103        __u32 count_connectors;
 104        __u32 count_encoders;
 105        __u32 min_width, max_width;
 106        __u32 min_height, max_height;
 107};
 108
 109struct drm_mode_crtc {
 110        __u64 set_connectors_ptr;
 111        __u32 count_connectors;
 112
 113        __u32 crtc_id; /**< Id */
 114        __u32 fb_id; /**< Id of framebuffer */
 115
 116        __u32 x, y; /**< Position on the frameuffer */
 117
 118        __u32 gamma_size;
 119        __u32 mode_valid;
 120        struct drm_mode_modeinfo mode;
 121};
 122
 123#define DRM_MODE_ENCODER_NONE   0
 124#define DRM_MODE_ENCODER_DAC    1
 125#define DRM_MODE_ENCODER_TMDS   2
 126#define DRM_MODE_ENCODER_LVDS   3
 127#define DRM_MODE_ENCODER_TVDAC  4
 128
 129struct drm_mode_get_encoder {
 130        __u32 encoder_id;
 131        __u32 encoder_type;
 132
 133        __u32 crtc_id; /**< Id of crtc */
 134
 135        __u32 possible_crtcs;
 136        __u32 possible_clones;
 137};
 138
 139/* This is for connectors with multiple signal types. */
 140/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
 141#define DRM_MODE_SUBCONNECTOR_Automatic 0
 142#define DRM_MODE_SUBCONNECTOR_Unknown   0
 143#define DRM_MODE_SUBCONNECTOR_DVID      3
 144#define DRM_MODE_SUBCONNECTOR_DVIA      4
 145#define DRM_MODE_SUBCONNECTOR_Composite 5
 146#define DRM_MODE_SUBCONNECTOR_SVIDEO    6
 147#define DRM_MODE_SUBCONNECTOR_Component 8
 148#define DRM_MODE_SUBCONNECTOR_SCART     9
 149
 150#define DRM_MODE_CONNECTOR_Unknown      0
 151#define DRM_MODE_CONNECTOR_VGA          1
 152#define DRM_MODE_CONNECTOR_DVII         2
 153#define DRM_MODE_CONNECTOR_DVID         3
 154#define DRM_MODE_CONNECTOR_DVIA         4
 155#define DRM_MODE_CONNECTOR_Composite    5
 156#define DRM_MODE_CONNECTOR_SVIDEO       6
 157#define DRM_MODE_CONNECTOR_LVDS         7
 158#define DRM_MODE_CONNECTOR_Component    8
 159#define DRM_MODE_CONNECTOR_9PinDIN      9
 160#define DRM_MODE_CONNECTOR_DisplayPort  10
 161#define DRM_MODE_CONNECTOR_HDMIA        11
 162#define DRM_MODE_CONNECTOR_HDMIB        12
 163#define DRM_MODE_CONNECTOR_TV           13
 164#define DRM_MODE_CONNECTOR_eDP          14
 165
 166struct drm_mode_get_connector {
 167
 168        __u64 encoders_ptr;
 169        __u64 modes_ptr;
 170        __u64 props_ptr;
 171        __u64 prop_values_ptr;
 172
 173        __u32 count_modes;
 174        __u32 count_props;
 175        __u32 count_encoders;
 176
 177        __u32 encoder_id; /**< Current Encoder */
 178        __u32 connector_id; /**< Id */
 179        __u32 connector_type;
 180        __u32 connector_type_id;
 181
 182        __u32 connection;
 183        __u32 mm_width, mm_height; /**< HxW in millimeters */
 184        __u32 subpixel;
 185};
 186
 187#define DRM_MODE_PROP_PENDING   (1<<0)
 188#define DRM_MODE_PROP_RANGE     (1<<1)
 189#define DRM_MODE_PROP_IMMUTABLE (1<<2)
 190#define DRM_MODE_PROP_ENUM      (1<<3) /* enumerated type with text strings */
 191#define DRM_MODE_PROP_BLOB      (1<<4)
 192
 193struct drm_mode_property_enum {
 194        __u64 value;
 195        char name[DRM_PROP_NAME_LEN];
 196};
 197
 198struct drm_mode_get_property {
 199        __u64 values_ptr; /* values and blob lengths */
 200        __u64 enum_blob_ptr; /* enum and blob id ptrs */
 201
 202        __u32 prop_id;
 203        __u32 flags;
 204        char name[DRM_PROP_NAME_LEN];
 205
 206        __u32 count_values;
 207        __u32 count_enum_blobs;
 208};
 209
 210struct drm_mode_connector_set_property {
 211        __u64 value;
 212        __u32 prop_id;
 213        __u32 connector_id;
 214};
 215
 216struct drm_mode_get_blob {
 217        __u32 blob_id;
 218        __u32 length;
 219        __u64 data;
 220};
 221
 222struct drm_mode_fb_cmd {
 223        __u32 fb_id;
 224        __u32 width, height;
 225        __u32 pitch;
 226        __u32 bpp;
 227        __u32 depth;
 228        /* driver specific handle */
 229        __u32 handle;
 230};
 231
 232#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
 233#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
 234#define DRM_MODE_FB_DIRTY_FLAGS         0x03
 235
 236/*
 237 * Mark a region of a framebuffer as dirty.
 238 *
 239 * Some hardware does not automatically update display contents
 240 * as a hardware or software draw to a framebuffer. This ioctl
 241 * allows userspace to tell the kernel and the hardware what
 242 * regions of the framebuffer have changed.
 243 *
 244 * The kernel or hardware is free to update more then just the
 245 * region specified by the clip rects. The kernel or hardware
 246 * may also delay and/or coalesce several calls to dirty into a
 247 * single update.
 248 *
 249 * Userspace may annotate the updates, the annotates are a
 250 * promise made by the caller that the change is either a copy
 251 * of pixels or a fill of a single color in the region specified.
 252 *
 253 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
 254 * the number of updated regions are half of num_clips given,
 255 * where the clip rects are paired in src and dst. The width and
 256 * height of each one of the pairs must match.
 257 *
 258 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
 259 * promises that the region specified of the clip rects is filled
 260 * completely with a single color as given in the color argument.
 261 */
 262
 263struct drm_mode_fb_dirty_cmd {
 264        __u32 fb_id;
 265        __u32 flags;
 266        __u32 color;
 267        __u32 num_clips;
 268        __u64 clips_ptr;
 269};
 270
 271struct drm_mode_mode_cmd {
 272        __u32 connector_id;
 273        struct drm_mode_modeinfo mode;
 274};
 275
 276#define DRM_MODE_CURSOR_BO      (1<<0)
 277#define DRM_MODE_CURSOR_MOVE    (1<<1)
 278
 279/*
 280 * depending on the value in flags different members are used.
 281 *
 282 * CURSOR_BO uses
 283 *    crtc
 284 *    width
 285 *    height
 286 *    handle - if 0 turns the cursor of
 287 *
 288 * CURSOR_MOVE uses
 289 *    crtc
 290 *    x
 291 *    y
 292 */
 293struct drm_mode_cursor {
 294        __u32 flags;
 295        __u32 crtc_id;
 296        __s32 x;
 297        __s32 y;
 298        __u32 width;
 299        __u32 height;
 300        /* driver specific handle */
 301        __u32 handle;
 302};
 303
 304struct drm_mode_crtc_lut {
 305        __u32 crtc_id;
 306        __u32 gamma_size;
 307
 308        /* pointers to arrays */
 309        __u64 red;
 310        __u64 green;
 311        __u64 blue;
 312};
 313
 314#define DRM_MODE_PAGE_FLIP_EVENT 0x01
 315#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
 316
 317/*
 318 * Request a page flip on the specified crtc.
 319 *
 320 * This ioctl will ask KMS to schedule a page flip for the specified
 321 * crtc.  Once any pending rendering targeting the specified fb (as of
 322 * ioctl time) has completed, the crtc will be reprogrammed to display
 323 * that fb after the next vertical refresh.  The ioctl returns
 324 * immediately, but subsequent rendering to the current fb will block
 325 * in the execbuffer ioctl until the page flip happens.  If a page
 326 * flip is already pending as the ioctl is called, EBUSY will be
 327 * returned.
 328 *
 329 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
 330 * request that drm sends back a vblank event (see drm.h: struct
 331 * drm_event_vblank) when the page flip is done.  The user_data field
 332 * passed in with this ioctl will be returned as the user_data field
 333 * in the vblank event struct.
 334 *
 335 * The reserved field must be zero until we figure out something
 336 * clever to use it for.
 337 */
 338
 339struct drm_mode_crtc_page_flip {
 340        __u32 crtc_id;
 341        __u32 fb_id;
 342        __u32 flags;
 343        __u32 reserved;
 344        __u64 user_data;
 345};
 346
 347/* create a dumb scanout buffer */
 348struct drm_mode_create_dumb {
 349        uint32_t height;
 350        uint32_t width;
 351        uint32_t bpp;
 352        uint32_t flags;
 353        /* handle, pitch, size will be returned */
 354        uint32_t handle;
 355        uint32_t pitch;
 356        uint64_t size;
 357};
 358
 359/* set up for mmap of a dumb scanout buffer */
 360struct drm_mode_map_dumb {
 361        /** Handle for the object being mapped. */
 362        __u32 handle;
 363        __u32 pad;
 364        /**
 365         * Fake offset to use for subsequent mmap call
 366         *
 367         * This is a fixed-size type for 32/64 compatibility.
 368         */
 369        __u64 offset;
 370};
 371
 372struct drm_mode_destroy_dumb {
 373        uint32_t handle;
 374};
 375
 376#endif
 377