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20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/mutex.h>
23#include <linux/pci.h>
24#include <linux/slab.h>
25#include <sound/ac97_codec.h>
26#include <sound/asoundef.h>
27#include <sound/core.h>
28#include <sound/info.h>
29#include <sound/mpu401.h>
30#include <sound/pcm.h>
31#include "oxygen.h"
32#include "cm9780.h"
33
34MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
35MODULE_DESCRIPTION("C-Media CMI8788 helper library");
36MODULE_LICENSE("GPL v2");
37
38#define DRIVER "oxygen"
39
40static inline int oxygen_uart_input_ready(struct oxygen *chip)
41{
42 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
43}
44
45static void oxygen_read_uart(struct oxygen *chip)
46{
47 if (unlikely(!oxygen_uart_input_ready(chip))) {
48
49 oxygen_read8(chip, OXYGEN_MPU401);
50 return;
51 }
52 do {
53 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
54 if (data == MPU401_ACK)
55 continue;
56 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
57 chip->uart_input_count = 0;
58 chip->uart_input[chip->uart_input_count++] = data;
59 } while (oxygen_uart_input_ready(chip));
60 if (chip->model.uart_input)
61 chip->model.uart_input(chip);
62}
63
64static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
65{
66 struct oxygen *chip = dev_id;
67 unsigned int status, clear, elapsed_streams, i;
68
69 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
70 if (!status)
71 return IRQ_NONE;
72
73 spin_lock(&chip->reg_lock);
74
75 clear = status & (OXYGEN_CHANNEL_A |
76 OXYGEN_CHANNEL_B |
77 OXYGEN_CHANNEL_C |
78 OXYGEN_CHANNEL_SPDIF |
79 OXYGEN_CHANNEL_MULTICH |
80 OXYGEN_CHANNEL_AC97 |
81 OXYGEN_INT_SPDIF_IN_DETECT |
82 OXYGEN_INT_GPIO |
83 OXYGEN_INT_AC97);
84 if (clear) {
85 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
86 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
87 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
88 chip->interrupt_mask & ~clear);
89 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
90 chip->interrupt_mask);
91 }
92
93 elapsed_streams = status & chip->pcm_running;
94
95 spin_unlock(&chip->reg_lock);
96
97 for (i = 0; i < PCM_COUNT; ++i)
98 if ((elapsed_streams & (1 << i)) && chip->streams[i])
99 snd_pcm_period_elapsed(chip->streams[i]);
100
101 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
102 spin_lock(&chip->reg_lock);
103 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
104 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
105 OXYGEN_SPDIF_RATE_INT)) {
106
107 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
108 schedule_work(&chip->spdif_input_bits_work);
109 }
110 spin_unlock(&chip->reg_lock);
111 }
112
113 if (status & OXYGEN_INT_GPIO)
114 schedule_work(&chip->gpio_work);
115
116 if (status & OXYGEN_INT_MIDI) {
117 if (chip->midi)
118 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
119 else
120 oxygen_read_uart(chip);
121 }
122
123 if (status & OXYGEN_INT_AC97)
124 wake_up(&chip->ac97_waitqueue);
125
126 return IRQ_HANDLED;
127}
128
129static void oxygen_spdif_input_bits_changed(struct work_struct *work)
130{
131 struct oxygen *chip = container_of(work, struct oxygen,
132 spdif_input_bits_work);
133 u32 reg;
134
135
136
137
138
139
140 msleep(1);
141 spin_lock_irq(&chip->reg_lock);
142 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
143 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
144 OXYGEN_SPDIF_LOCK_STATUS))
145 == OXYGEN_SPDIF_SENSE_STATUS) {
146
147
148
149
150 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
151 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
152 spin_unlock_irq(&chip->reg_lock);
153 msleep(1);
154 spin_lock_irq(&chip->reg_lock);
155 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
156 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
157 OXYGEN_SPDIF_LOCK_STATUS))
158 == OXYGEN_SPDIF_SENSE_STATUS) {
159
160 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
161 == OXYGEN_SPDIF_IN_CLOCK_192) {
162
163
164
165
166 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
167 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
168 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
169 }
170 }
171 }
172 spin_unlock_irq(&chip->reg_lock);
173
174 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
175 spin_lock_irq(&chip->reg_lock);
176 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
177 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
178 chip->interrupt_mask);
179 spin_unlock_irq(&chip->reg_lock);
180
181
182
183
184
185 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
186 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
187 }
188}
189
190static void oxygen_gpio_changed(struct work_struct *work)
191{
192 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
193
194 if (chip->model.gpio_changed)
195 chip->model.gpio_changed(chip);
196}
197
198#ifdef CONFIG_PROC_FS
199static void oxygen_proc_read(struct snd_info_entry *entry,
200 struct snd_info_buffer *buffer)
201{
202 struct oxygen *chip = entry->private_data;
203 int i, j;
204
205 switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
206 case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
207 case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
208 case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
209 default: i = '?'; break;
210 }
211 snd_iprintf(buffer, "CMI878%c:\n", i);
212 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
213 snd_iprintf(buffer, "%02x:", i);
214 for (j = 0; j < 0x10; ++j)
215 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
216 snd_iprintf(buffer, "\n");
217 }
218 if (mutex_lock_interruptible(&chip->mutex) < 0)
219 return;
220 if (chip->has_ac97_0) {
221 snd_iprintf(buffer, "\nAC97:\n");
222 for (i = 0; i < 0x80; i += 0x10) {
223 snd_iprintf(buffer, "%02x:", i);
224 for (j = 0; j < 0x10; j += 2)
225 snd_iprintf(buffer, " %04x",
226 oxygen_read_ac97(chip, 0, i + j));
227 snd_iprintf(buffer, "\n");
228 }
229 }
230 if (chip->has_ac97_1) {
231 snd_iprintf(buffer, "\nAC97 2:\n");
232 for (i = 0; i < 0x80; i += 0x10) {
233 snd_iprintf(buffer, "%02x:", i);
234 for (j = 0; j < 0x10; j += 2)
235 snd_iprintf(buffer, " %04x",
236 oxygen_read_ac97(chip, 1, i + j));
237 snd_iprintf(buffer, "\n");
238 }
239 }
240 mutex_unlock(&chip->mutex);
241 if (chip->model.dump_registers)
242 chip->model.dump_registers(chip, buffer);
243}
244
245static void oxygen_proc_init(struct oxygen *chip)
246{
247 struct snd_info_entry *entry;
248
249 if (!snd_card_proc_new(chip->card, "oxygen", &entry))
250 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
251}
252#else
253#define oxygen_proc_init(chip)
254#endif
255
256static const struct pci_device_id *
257oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
258{
259 u16 subdevice;
260
261
262
263
264
265 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
266 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
267
268
269
270
271 subdevice = oxygen_read_eeprom(chip, 2);
272
273 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
274 subdevice = 0x8788;
275
276
277
278
279
280 for (; ids->vendor; ++ids)
281 if (ids->subdevice == subdevice &&
282 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
283 return ids;
284 return NULL;
285}
286
287static void oxygen_restore_eeprom(struct oxygen *chip,
288 const struct pci_device_id *id)
289{
290 u16 eeprom_id;
291
292 eeprom_id = oxygen_read_eeprom(chip, 0);
293 if (eeprom_id != OXYGEN_EEPROM_ID &&
294 (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
295
296
297
298
299
300
301
302
303 oxygen_write_eeprom(chip, 1, id->subvendor);
304 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
305
306 oxygen_set_bits8(chip, OXYGEN_MISC,
307 OXYGEN_MISC_WRITE_PCI_SUBID);
308 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
309 id->subvendor);
310 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
311 id->subdevice);
312 oxygen_clear_bits8(chip, OXYGEN_MISC,
313 OXYGEN_MISC_WRITE_PCI_SUBID);
314
315 snd_printk(KERN_INFO "EEPROM ID restored\n");
316 }
317}
318
319static void configure_pcie_bridge(struct pci_dev *pci)
320{
321 enum { PEX811X, PI7C9X110 };
322 static const struct pci_device_id bridge_ids[] = {
323 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
324 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
325 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
326 { }
327 };
328 struct pci_dev *bridge;
329 const struct pci_device_id *id;
330 u32 tmp;
331
332 if (!pci->bus || !pci->bus->self)
333 return;
334 bridge = pci->bus->self;
335
336 id = pci_match_id(bridge_ids, bridge);
337 if (!id)
338 return;
339
340 switch (id->driver_data) {
341 case PEX811X:
342 pci_read_config_dword(bridge, 0x48, &tmp);
343 tmp |= 1;
344 tmp |= 1 << 11;
345 pci_write_config_dword(bridge, 0x48, tmp);
346
347 pci_write_config_dword(bridge, 0x84, 0x0c);
348 pci_read_config_dword(bridge, 0x88, &tmp);
349 tmp &= ~(7 << 27);
350 tmp |= 2 << 27;
351 pci_write_config_dword(bridge, 0x88, tmp);
352 break;
353
354 case PI7C9X110:
355 pci_read_config_dword(bridge, 0x40, &tmp);
356 tmp |= 1;
357 pci_write_config_dword(bridge, 0x40, tmp);
358 break;
359 }
360}
361
362static void oxygen_init(struct oxygen *chip)
363{
364 unsigned int i;
365
366 chip->dac_routing = 1;
367 for (i = 0; i < 8; ++i)
368 chip->dac_volume[i] = chip->model.dac_volume_min;
369 chip->dac_mute = 1;
370 chip->spdif_playback_enable = 1;
371 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
372 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
373 chip->spdif_pcm_bits = chip->spdif_bits;
374
375 if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
376 oxygen_set_bits8(chip, OXYGEN_MISC,
377 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
378
379 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
380 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
381 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
382
383 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
384 OXYGEN_FUNCTION_RESET_CODEC |
385 chip->model.function_flags,
386 OXYGEN_FUNCTION_RESET_CODEC |
387 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
388 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
389 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
390 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
391 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
392 OXYGEN_PLAY_CHANNELS_2 |
393 OXYGEN_DMA_A_BURST_8 |
394 OXYGEN_DMA_MULTICH_BURST_8);
395 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
396 oxygen_write8_masked(chip, OXYGEN_MISC,
397 chip->model.misc_flags,
398 OXYGEN_MISC_WRITE_PCI_SUBID |
399 OXYGEN_MISC_REC_C_FROM_SPDIF |
400 OXYGEN_MISC_REC_B_FROM_AC97 |
401 OXYGEN_MISC_REC_A_FROM_MULTICH |
402 OXYGEN_MISC_MIDI);
403 oxygen_write8(chip, OXYGEN_REC_FORMAT,
404 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
405 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
406 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
407 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
408 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
409 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
410 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
411 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
412 OXYGEN_RATE_48000 |
413 chip->model.dac_i2s_format |
414 OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
415 OXYGEN_I2S_BITS_16 |
416 OXYGEN_I2S_MASTER |
417 OXYGEN_I2S_BCLK_64);
418 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
419 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
420 OXYGEN_RATE_48000 |
421 chip->model.adc_i2s_format |
422 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
423 OXYGEN_I2S_BITS_16 |
424 OXYGEN_I2S_MASTER |
425 OXYGEN_I2S_BCLK_64);
426 else
427 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
428 OXYGEN_I2S_MASTER |
429 OXYGEN_I2S_MUTE_MCLK);
430 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
431 CAPTURE_2_FROM_I2S_2))
432 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
433 OXYGEN_RATE_48000 |
434 chip->model.adc_i2s_format |
435 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
436 OXYGEN_I2S_BITS_16 |
437 OXYGEN_I2S_MASTER |
438 OXYGEN_I2S_BCLK_64);
439 else
440 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
441 OXYGEN_I2S_MASTER |
442 OXYGEN_I2S_MUTE_MCLK);
443 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
444 OXYGEN_I2S_MASTER |
445 OXYGEN_I2S_MUTE_MCLK);
446 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
447 OXYGEN_SPDIF_OUT_ENABLE |
448 OXYGEN_SPDIF_LOOPBACK);
449 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
450 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
451 OXYGEN_SPDIF_SENSE_MASK |
452 OXYGEN_SPDIF_LOCK_MASK |
453 OXYGEN_SPDIF_RATE_MASK |
454 OXYGEN_SPDIF_LOCK_PAR |
455 OXYGEN_SPDIF_IN_CLOCK_96,
456 OXYGEN_SPDIF_SENSE_MASK |
457 OXYGEN_SPDIF_LOCK_MASK |
458 OXYGEN_SPDIF_RATE_MASK |
459 OXYGEN_SPDIF_SENSE_PAR |
460 OXYGEN_SPDIF_LOCK_PAR |
461 OXYGEN_SPDIF_IN_CLOCK_MASK);
462 else
463 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
464 OXYGEN_SPDIF_SENSE_MASK |
465 OXYGEN_SPDIF_LOCK_MASK |
466 OXYGEN_SPDIF_RATE_MASK);
467 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
468 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
469 OXYGEN_2WIRE_LENGTH_8 |
470 OXYGEN_2WIRE_INTERRUPT_MASK |
471 OXYGEN_2WIRE_SPEED_STANDARD);
472 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
473 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
474 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
475 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
476 OXYGEN_PLAY_MULTICH_I2S_DAC |
477 OXYGEN_PLAY_SPDIF_SPDIF |
478 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
479 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
480 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
481 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
482 oxygen_write8(chip, OXYGEN_REC_ROUTING,
483 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
484 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
485 OXYGEN_REC_C_ROUTE_SPDIF);
486 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
487 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
488 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
489 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
490 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
491 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
492
493 if (chip->has_ac97_0 | chip->has_ac97_1)
494 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
495 OXYGEN_AC97_INT_READ_DONE |
496 OXYGEN_AC97_INT_WRITE_DONE);
497 else
498 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
499 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
500 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
501 if (!(chip->has_ac97_0 | chip->has_ac97_1))
502 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
503 OXYGEN_AC97_CLOCK_DISABLE);
504 if (!chip->has_ac97_0) {
505 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
506 OXYGEN_AC97_NO_CODEC_0);
507 } else {
508 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
509 msleep(1);
510 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
511 CM9780_GPIO0IO | CM9780_GPIO1IO);
512 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
513 CM9780_BSTSEL | CM9780_STRO_MIC |
514 CM9780_MIX2FR | CM9780_PCBSW);
515 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
516 CM9780_RSOE | CM9780_CBOE |
517 CM9780_SSOE | CM9780_FROE |
518 CM9780_MIC2MIC | CM9780_LI2LI);
519 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
520 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
521 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
522 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
523 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
524 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
525 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
526 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
527 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
528 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
529 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
530 CM9780_GPO0);
531
532 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
533 AC97_PD_PR0 | AC97_PD_PR1);
534 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
535 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
536 }
537 if (chip->has_ac97_1) {
538 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
539 OXYGEN_AC97_CODEC1_SLOT3 |
540 OXYGEN_AC97_CODEC1_SLOT4);
541 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
542 msleep(1);
543 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
544 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
545 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
546 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
547 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
548 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
549 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
550 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
551 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
552 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
553 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
554 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
555 }
556}
557
558static void oxygen_shutdown(struct oxygen *chip)
559{
560 spin_lock_irq(&chip->reg_lock);
561 chip->interrupt_mask = 0;
562 chip->pcm_running = 0;
563 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
564 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
565 spin_unlock_irq(&chip->reg_lock);
566}
567
568static void oxygen_card_free(struct snd_card *card)
569{
570 struct oxygen *chip = card->private_data;
571
572 oxygen_shutdown(chip);
573 if (chip->irq >= 0)
574 free_irq(chip->irq, chip);
575 flush_work_sync(&chip->spdif_input_bits_work);
576 flush_work_sync(&chip->gpio_work);
577 chip->model.cleanup(chip);
578 kfree(chip->model_data);
579 mutex_destroy(&chip->mutex);
580 pci_release_regions(chip->pci);
581 pci_disable_device(chip->pci);
582}
583
584int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
585 struct module *owner,
586 const struct pci_device_id *ids,
587 int (*get_model)(struct oxygen *chip,
588 const struct pci_device_id *id
589 )
590 )
591{
592 struct snd_card *card;
593 struct oxygen *chip;
594 const struct pci_device_id *pci_id;
595 int err;
596
597 err = snd_card_create(index, id, owner, sizeof(*chip), &card);
598 if (err < 0)
599 return err;
600
601 chip = card->private_data;
602 chip->card = card;
603 chip->pci = pci;
604 chip->irq = -1;
605 spin_lock_init(&chip->reg_lock);
606 mutex_init(&chip->mutex);
607 INIT_WORK(&chip->spdif_input_bits_work,
608 oxygen_spdif_input_bits_changed);
609 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
610 init_waitqueue_head(&chip->ac97_waitqueue);
611
612 err = pci_enable_device(pci);
613 if (err < 0)
614 goto err_card;
615
616 err = pci_request_regions(pci, DRIVER);
617 if (err < 0) {
618 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
619 goto err_pci_enable;
620 }
621
622 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
623 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
624 snd_printk(KERN_ERR "invalid PCI I/O range\n");
625 err = -ENXIO;
626 goto err_pci_regions;
627 }
628 chip->addr = pci_resource_start(pci, 0);
629
630 pci_id = oxygen_search_pci_id(chip, ids);
631 if (!pci_id) {
632 err = -ENODEV;
633 goto err_pci_regions;
634 }
635 oxygen_restore_eeprom(chip, pci_id);
636 err = get_model(chip, pci_id);
637 if (err < 0)
638 goto err_pci_regions;
639
640 if (chip->model.model_data_size) {
641 chip->model_data = kzalloc(chip->model.model_data_size,
642 GFP_KERNEL);
643 if (!chip->model_data) {
644 err = -ENOMEM;
645 goto err_pci_regions;
646 }
647 }
648
649 pci_set_master(pci);
650 snd_card_set_dev(card, &pci->dev);
651 card->private_free = oxygen_card_free;
652
653 configure_pcie_bridge(pci);
654 oxygen_init(chip);
655 chip->model.init(chip);
656
657 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
658 DRIVER, chip);
659 if (err < 0) {
660 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
661 goto err_card;
662 }
663 chip->irq = pci->irq;
664
665 strcpy(card->driver, chip->model.chip);
666 strcpy(card->shortname, chip->model.shortname);
667 sprintf(card->longname, "%s at %#lx, irq %i",
668 chip->model.longname, chip->addr, chip->irq);
669 strcpy(card->mixername, chip->model.chip);
670 snd_component_add(card, chip->model.chip);
671
672 err = oxygen_pcm_init(chip);
673 if (err < 0)
674 goto err_card;
675
676 err = oxygen_mixer_init(chip);
677 if (err < 0)
678 goto err_card;
679
680 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
681 unsigned int info_flags = MPU401_INFO_INTEGRATED;
682 if (chip->model.device_config & MIDI_OUTPUT)
683 info_flags |= MPU401_INFO_OUTPUT;
684 if (chip->model.device_config & MIDI_INPUT)
685 info_flags |= MPU401_INFO_INPUT;
686 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
687 chip->addr + OXYGEN_MPU401,
688 info_flags, 0, 0,
689 &chip->midi);
690 if (err < 0)
691 goto err_card;
692 }
693
694 oxygen_proc_init(chip);
695
696 spin_lock_irq(&chip->reg_lock);
697 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
698 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
699 if (chip->has_ac97_0 | chip->has_ac97_1)
700 chip->interrupt_mask |= OXYGEN_INT_AC97;
701 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
702 spin_unlock_irq(&chip->reg_lock);
703
704 err = snd_card_register(card);
705 if (err < 0)
706 goto err_card;
707
708 pci_set_drvdata(pci, card);
709 return 0;
710
711err_pci_regions:
712 pci_release_regions(pci);
713err_pci_enable:
714 pci_disable_device(pci);
715err_card:
716 snd_card_free(card);
717 return err;
718}
719EXPORT_SYMBOL(oxygen_pci_probe);
720
721void oxygen_pci_remove(struct pci_dev *pci)
722{
723 snd_card_free(pci_get_drvdata(pci));
724 pci_set_drvdata(pci, NULL);
725}
726EXPORT_SYMBOL(oxygen_pci_remove);
727
728#ifdef CONFIG_PM
729int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
730{
731 struct snd_card *card = pci_get_drvdata(pci);
732 struct oxygen *chip = card->private_data;
733 unsigned int i, saved_interrupt_mask;
734
735 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
736
737 for (i = 0; i < PCM_COUNT; ++i)
738 if (chip->streams[i])
739 snd_pcm_suspend(chip->streams[i]);
740
741 if (chip->model.suspend)
742 chip->model.suspend(chip);
743
744 spin_lock_irq(&chip->reg_lock);
745 saved_interrupt_mask = chip->interrupt_mask;
746 chip->interrupt_mask = 0;
747 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
748 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
749 spin_unlock_irq(&chip->reg_lock);
750
751 synchronize_irq(chip->irq);
752 flush_work_sync(&chip->spdif_input_bits_work);
753 flush_work_sync(&chip->gpio_work);
754 chip->interrupt_mask = saved_interrupt_mask;
755
756 pci_disable_device(pci);
757 pci_save_state(pci);
758 pci_set_power_state(pci, pci_choose_state(pci, state));
759 return 0;
760}
761EXPORT_SYMBOL(oxygen_pci_suspend);
762
763static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
764 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
765 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
766};
767static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
768 { 0x18284fa2, 0x03060000 },
769 { 0x00007fa6, 0x00200000 }
770};
771
772static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
773{
774 return bitmap[bit / 32] & (1 << (bit & 31));
775}
776
777static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
778{
779 unsigned int i;
780
781 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
782 msleep(1);
783 for (i = 1; i < 0x40; ++i)
784 if (is_bit_set(ac97_registers_to_restore[codec], i))
785 oxygen_write_ac97(chip, codec, i * 2,
786 chip->saved_ac97_registers[codec][i]);
787}
788
789int oxygen_pci_resume(struct pci_dev *pci)
790{
791 struct snd_card *card = pci_get_drvdata(pci);
792 struct oxygen *chip = card->private_data;
793 unsigned int i;
794
795 pci_set_power_state(pci, PCI_D0);
796 pci_restore_state(pci);
797 if (pci_enable_device(pci) < 0) {
798 snd_printk(KERN_ERR "cannot reenable device");
799 snd_card_disconnect(card);
800 return -EIO;
801 }
802 pci_set_master(pci);
803
804 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
805 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
806 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
807 if (is_bit_set(registers_to_restore, i))
808 oxygen_write8(chip, i, chip->saved_registers._8[i]);
809 if (chip->has_ac97_0)
810 oxygen_restore_ac97(chip, 0);
811 if (chip->has_ac97_1)
812 oxygen_restore_ac97(chip, 1);
813
814 if (chip->model.resume)
815 chip->model.resume(chip);
816
817 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
818
819 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
820 return 0;
821}
822EXPORT_SYMBOL(oxygen_pci_resume);
823#endif
824
825void oxygen_pci_shutdown(struct pci_dev *pci)
826{
827 struct snd_card *card = pci_get_drvdata(pci);
828 struct oxygen *chip = card->private_data;
829
830 oxygen_shutdown(chip);
831 chip->model.cleanup(chip);
832}
833EXPORT_SYMBOL(oxygen_pci_shutdown);
834
