LXR linux/arch/arm/mach-davinci/mux.c

   1/*
   2 * Utility to set the DAVINCI MUX register from a table in mux.h
   3 *
   4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
   5 *
   6 * Based on linux/arch/arm/plat-omap/mux.c:
   7 * Copyright (C) 2003 - 2005 Nokia Corporation
   8 *
   9 * Written by Tony Lindgren
  10 *
  11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
  12 * the terms of the GNU General Public License version 2. This program
  13 * is licensed "as is" without any warranty of any kind, whether express
  14 * or implied.
  15 *
  16 * Copyright (C) 2008 Texas Instruments.
  17 */
  18#include <linux/io.h>
  19#include <linux/module.h>
  20#include <linux/spinlock.h>
  21
  22#include <mach/mux.h>
  23#include <mach/common.h>
  24
  25static void __iomem *pinmux_base;
  26
  27/*
  28 * Sets the DAVINCI MUX register based on the table
  29 */
  30int __init_or_module davinci_cfg_reg(const unsigned long index)
  31{
  32        static DEFINE_SPINLOCK(mux_spin_lock);
  33        struct davinci_soc_info *soc_info = &davinci_soc_info;
  34        unsigned long flags;
  35        const struct mux_config *cfg;
  36        unsigned int reg_orig = 0, reg = 0;
  37        unsigned int mask, warn = 0;
  38
  39        if (WARN_ON(!soc_info->pinmux_pins))
  40                return -ENODEV;
  41
  42        if (!pinmux_base) {
  43                pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
  44                if (WARN_ON(!pinmux_base))
  45                        return -ENOMEM;
  46        }
  47
  48        if (index >= soc_info->pinmux_pins_num) {
  49                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
  50                       index, soc_info->pinmux_pins_num);
  51                dump_stack();
  52                return -ENODEV;
  53        }
  54
  55        cfg = &soc_info->pinmux_pins[index];
  56
  57        if (cfg->name == NULL) {
  58                printk(KERN_ERR "No entry for the specified index\n");
  59                return -ENODEV;
  60        }
  61
  62        /* Update the mux register in question */
  63        if (cfg->mask) {
  64                unsigned        tmp1, tmp2;
  65
  66                spin_lock_irqsave(&mux_spin_lock, flags);
  67                reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
  68
  69                mask = (cfg->mask << cfg->mask_offset);
  70                tmp1 = reg_orig & mask;
  71                reg = reg_orig & ~mask;
  72
  73                tmp2 = (cfg->mode << cfg->mask_offset);
  74                reg |= tmp2;
  75
  76                if (tmp1 != tmp2)
  77                        warn = 1;
  78
  79                __raw_writel(reg, pinmux_base + cfg->mux_reg);
  80                spin_unlock_irqrestore(&mux_spin_lock, flags);
  81        }
  82
  83        if (warn) {
  84#ifdef CONFIG_DAVINCI_MUX_WARNINGS
  85                printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
  86#endif
  87        }
  88
  89#ifdef CONFIG_DAVINCI_MUX_DEBUG
  90        if (cfg->debug || warn) {
  91                printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
  92                printk(KERN_WARNING "      %s (0x%08x) = 0x%08x -> 0x%08x\n",
  93                       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
  94        }
  95#endif
  96
  97        return 0;
  98}
  99EXPORT_SYMBOL(davinci_cfg_reg);
 100
 101int __init_or_module davinci_cfg_reg_list(const short pins[])
 102{
 103        int i, error = -EINVAL;
 104
 105        if (pins)
 106                for (i = 0; pins[i] >= 0; i++) {
 107                        error = davinci_cfg_reg(pins[i]);
 108                        if (error)
 109                                break;
 110                }
 111
 112        return error;
 113}
 114