LXR linux/arch/arm/mach-mv78xx0/addr-map.c

   1/*
   2 * arch/arm/mach-mv78xx0/addr-map.c
   3 *
   4 * Address map functions for Marvell MV78xx0 SoCs
   5 *
   6 * This file is licensed under the terms of the GNU General Public
   7 * License version 2.  This program is licensed "as is" without any
   8 * warranty of any kind, whether express or implied.
   9 */
  10
  11#include <linux/kernel.h>
  12#include <linux/init.h>
  13#include <linux/mbus.h>
  14#include <linux/io.h>
  15#include "common.h"
  16
  17/*
  18 * Generic Address Decode Windows bit settings
  19 */
  20#define TARGET_DDR              0
  21#define TARGET_DEV_BUS          1
  22#define TARGET_PCIE0            4
  23#define TARGET_PCIE1            8
  24#define TARGET_PCIE(i)          ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
  25#define ATTR_DEV_SPI_ROM        0x1f
  26#define ATTR_DEV_BOOT           0x2f
  27#define ATTR_DEV_CS3            0x37
  28#define ATTR_DEV_CS2            0x3b
  29#define ATTR_DEV_CS1            0x3d
  30#define ATTR_DEV_CS0            0x3e
  31#define ATTR_PCIE_IO(l)         (0xf0 & ~(0x10 << (l)))
  32#define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
  33
  34/*
  35 * Helpers to get DDR bank info
  36 */
  37#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
  38#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
  39
  40/*
  41 * CPU Address Decode Windows registers
  42 */
  43#define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
  44#define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
  45#define WIN_CTRL_OFF            0x0000
  46#define WIN_BASE_OFF            0x0004
  47#define WIN_REMAP_LO_OFF        0x0008
  48#define WIN_REMAP_HI_OFF        0x000c
  49
  50
  51struct mbus_dram_target_info mv78xx0_mbus_dram_info;
  52
  53static void __init __iomem *win_cfg_base(int win)
  54{
  55        /*
  56         * Find the control register base address for this window.
  57         *
  58         * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
  59         * MBUS bridge depending on which CPU core we're running on,
  60         * so we don't need to take that into account here.
  61         */
  62
  63        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
  64}
  65
  66static int __init cpu_win_can_remap(int win)
  67{
  68        if (win < 8)
  69                return 1;
  70
  71        return 0;
  72}
  73
  74static void __init setup_cpu_win(int win, u32 base, u32 size,
  75                                 u8 target, u8 attr, int remap)
  76{
  77        void __iomem *addr = win_cfg_base(win);
  78        u32 ctrl;
  79
  80        base &= 0xffff0000;
  81        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
  82
  83        writel(base, addr + WIN_BASE_OFF);
  84        writel(ctrl, addr + WIN_CTRL_OFF);
  85        if (cpu_win_can_remap(win)) {
  86                if (remap < 0)
  87                        remap = base;
  88
  89                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
  90                writel(0, addr + WIN_REMAP_HI_OFF);
  91        }
  92}
  93
  94void __init mv78xx0_setup_cpu_mbus(void)
  95{
  96        void __iomem *addr;
  97        int i;
  98        int cs;
  99
 100        /*
 101         * First, disable and clear windows.
 102         */
 103        for (i = 0; i < 14; i++) {
 104                addr = win_cfg_base(i);
 105
 106                writel(0, addr + WIN_BASE_OFF);
 107                writel(0, addr + WIN_CTRL_OFF);
 108                if (cpu_win_can_remap(i)) {
 109                        writel(0, addr + WIN_REMAP_LO_OFF);
 110                        writel(0, addr + WIN_REMAP_HI_OFF);
 111                }
 112        }
 113
 114        /*
 115         * Setup MBUS dram target info.
 116         */
 117        mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 118
 119        if (mv78xx0_core_index() == 0)
 120                addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
 121        else
 122                addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
 123
 124        for (i = 0, cs = 0; i < 4; i++) {
 125                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
 126                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
 127
 128                /*
 129                 * Chip select enabled?
 130                 */
 131                if (size & 1) {
 132                        struct mbus_dram_window *w;
 133
 134                        w = &mv78xx0_mbus_dram_info.cs[cs++];
 135                        w->cs_index = i;
 136                        w->mbus_attr = 0xf & ~(1 << i);
 137                        w->base = base & 0xffff0000;
 138                        w->size = (size | 0x0000ffff) + 1;
 139                }
 140        }
 141        mv78xx0_mbus_dram_info.num_cs = cs;
 142}
 143
 144void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
 145                                      int maj, int min)
 146{
 147        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
 148                      ATTR_PCIE_IO(min), -1);
 149}
 150
 151void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
 152                                       int maj, int min)
 153{
 154        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
 155                      ATTR_PCIE_MEM(min), -1);
 156}
 157