LXR linux/arch/arm/mach-orion5x/addr-map.c

   1/*
   2 * arch/arm/mach-orion5x/addr-map.c
   3 *
   4 * Address map functions for Marvell Orion 5x SoCs
   5 *
   6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7 *
   8 * This file is licensed under the terms of the GNU General Public
   9 * License version 2.  This program is licensed "as is" without any
  10 * warranty of any kind, whether express or implied.
  11 */
  12
  13#include <linux/kernel.h>
  14#include <linux/init.h>
  15#include <linux/mbus.h>
  16#include <linux/io.h>
  17#include <linux/errno.h>
  18#include <mach/hardware.h>
  19#include "common.h"
  20
  21/*
  22 * The Orion has fully programmable address map. There's a separate address
  23 * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
  24 * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
  25 * address decode windows that allow it to access any of the Orion resources.
  26 *
  27 * CPU address decoding --
  28 * Linux assumes that it is the boot loader that already setup the access to
  29 * DDR and internal registers.
  30 * Setup access to PCI and PCIe IO/MEM space is issued by this file.
  31 * Setup access to various devices located on the device bus interface (e.g.
  32 * flashes, RTC, etc) should be issued by machine-setup.c according to
  33 * specific board population (by using orion5x_setup_*_win()).
  34 *
  35 * Non-CPU Masters address decoding --
  36 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
  37 * banks only (the typical use case).
  38 * Setup access for each master to DDR is issued by platform device setup.
  39 */
  40
  41/*
  42 * Generic Address Decode Windows bit settings
  43 */
  44#define TARGET_DDR              0
  45#define TARGET_DEV_BUS          1
  46#define TARGET_PCI              3
  47#define TARGET_PCIE             4
  48#define TARGET_SRAM             9
  49#define ATTR_PCIE_MEM           0x59
  50#define ATTR_PCIE_IO            0x51
  51#define ATTR_PCIE_WA            0x79
  52#define ATTR_PCI_MEM            0x59
  53#define ATTR_PCI_IO             0x51
  54#define ATTR_DEV_CS0            0x1e
  55#define ATTR_DEV_CS1            0x1d
  56#define ATTR_DEV_CS2            0x1b
  57#define ATTR_DEV_BOOT           0xf
  58#define ATTR_SRAM               0x0
  59
  60/*
  61 * Helpers to get DDR bank info
  62 */
  63#define ORION5X_DDR_REG(x)      (ORION5X_DDR_VIRT_BASE | (x))
  64#define DDR_BASE_CS(n)          ORION5X_DDR_REG(0x1500 + ((n) << 3))
  65#define DDR_SIZE_CS(n)          ORION5X_DDR_REG(0x1504 + ((n) << 3))
  66
  67/*
  68 * CPU Address Decode Windows registers
  69 */
  70#define ORION5X_BRIDGE_REG(x)   (ORION5X_BRIDGE_VIRT_BASE | (x))
  71#define CPU_WIN_CTRL(n)         ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
  72#define CPU_WIN_BASE(n)         ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
  73#define CPU_WIN_REMAP_LO(n)     ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
  74#define CPU_WIN_REMAP_HI(n)     ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
  75
  76
  77struct mbus_dram_target_info orion5x_mbus_dram_info;
  78static int __initdata win_alloc_count;
  79
  80static int __init orion5x_cpu_win_can_remap(int win)
  81{
  82        u32 dev, rev;
  83
  84        orion5x_pcie_id(&dev, &rev);
  85        if ((dev == MV88F5281_DEV_ID && win < 4)
  86            || (dev == MV88F5182_DEV_ID && win < 2)
  87            || (dev == MV88F5181_DEV_ID && win < 2)
  88            || (dev == MV88F6183_DEV_ID && win < 4))
  89                return 1;
  90
  91        return 0;
  92}
  93
  94static int __init setup_cpu_win(int win, u32 base, u32 size,
  95                                 u8 target, u8 attr, int remap)
  96{
  97        if (win >= 8) {
  98                printk(KERN_ERR "setup_cpu_win: trying to allocate "
  99                                "window %d\n", win);
 100                return -ENOSPC;
 101        }
 102
 103        writel(base & 0xffff0000, CPU_WIN_BASE(win));
 104        writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
 105                CPU_WIN_CTRL(win));
 106
 107        if (orion5x_cpu_win_can_remap(win)) {
 108                if (remap < 0)
 109                        remap = base;
 110
 111                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
 112                writel(0, CPU_WIN_REMAP_HI(win));
 113        }
 114        return 0;
 115}
 116
 117void __init orion5x_setup_cpu_mbus_bridge(void)
 118{
 119        int i;
 120        int cs;
 121
 122        /*
 123         * First, disable and clear windows.
 124         */
 125        for (i = 0; i < 8; i++) {
 126                writel(0, CPU_WIN_BASE(i));
 127                writel(0, CPU_WIN_CTRL(i));
 128                if (orion5x_cpu_win_can_remap(i)) {
 129                        writel(0, CPU_WIN_REMAP_LO(i));
 130                        writel(0, CPU_WIN_REMAP_HI(i));
 131                }
 132        }
 133
 134        /*
 135         * Setup windows for PCI+PCIe IO+MEM space.
 136         */
 137        setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
 138                TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
 139        setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
 140                TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
 141        setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
 142                TARGET_PCIE, ATTR_PCIE_MEM, -1);
 143        setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
 144                TARGET_PCI, ATTR_PCI_MEM, -1);
 145        win_alloc_count = 4;
 146
 147        /*
 148         * Setup MBUS dram target info.
 149         */
 150        orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 151
 152        for (i = 0, cs = 0; i < 4; i++) {
 153                u32 base = readl(DDR_BASE_CS(i));
 154                u32 size = readl(DDR_SIZE_CS(i));
 155
 156                /*
 157                 * Chip select enabled?
 158                 */
 159                if (size & 1) {
 160                        struct mbus_dram_window *w;
 161
 162                        w = &orion5x_mbus_dram_info.cs[cs++];
 163                        w->cs_index = i;
 164                        w->mbus_attr = 0xf & ~(1 << i);
 165                        w->base = base & 0xffff0000;
 166                        w->size = (size | 0x0000ffff) + 1;
 167                }
 168        }
 169        orion5x_mbus_dram_info.num_cs = cs;
 170}
 171
 172void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 173{
 174        setup_cpu_win(win_alloc_count++, base, size,
 175                      TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 176}
 177
 178void __init orion5x_setup_dev0_win(u32 base, u32 size)
 179{
 180        setup_cpu_win(win_alloc_count++, base, size,
 181                      TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 182}
 183
 184void __init orion5x_setup_dev1_win(u32 base, u32 size)
 185{
 186        setup_cpu_win(win_alloc_count++, base, size,
 187                      TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 188}
 189
 190void __init orion5x_setup_dev2_win(u32 base, u32 size)
 191{
 192        setup_cpu_win(win_alloc_count++, base, size,
 193                      TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 194}
 195
 196void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 197{
 198        setup_cpu_win(win_alloc_count++, base, size,
 199                      TARGET_PCIE, ATTR_PCIE_WA, -1);
 200}
 201
 202int __init orion5x_setup_sram_win(void)
 203{
 204        return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE,
 205                        ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
 206}
 207