1/* 2 * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes 3 * 4 * Copyright (c) 2005-2008 Analog Devices Inc. 5 * Copyright (C) 2005 John DeHority 6 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) 7 * 8 * Licensed under the GPL-2. 9 */ 10 11#ifndef _BLACKFIN_TIMERS_H_ 12#define _BLACKFIN_TIMERS_H_ 13 14#include <linux/types.h> 15#include <asm/blackfin.h> 16 17/* 18 * BF51x/BF52x/BF537: 8 timers: 19 */ 20#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY) 21# define MAX_BLACKFIN_GPTIMERS 8 22# define TIMER0_GROUP_REG TIMER_ENABLE 23#endif 24/* 25 * BF54x: 11 timers (BF542: 8 timers): 26 */ 27#if defined(CONFIG_BF54x) 28# ifdef CONFIG_BF542 29# define MAX_BLACKFIN_GPTIMERS 8 30# else 31# define MAX_BLACKFIN_GPTIMERS 11 32# define TIMER8_GROUP_REG TIMER_ENABLE1 33# define TIMER_GROUP2 1 34# endif 35# define TIMER0_GROUP_REG TIMER_ENABLE0 36#endif 37/* 38 * BF561: 12 timers: 39 */ 40#if defined(CONFIG_BF561) 41# define MAX_BLACKFIN_GPTIMERS 12 42# define TIMER0_GROUP_REG TMRS8_ENABLE 43# define TIMER8_GROUP_REG TMRS4_ENABLE 44# define TIMER_GROUP2 1 45#endif 46/* 47 * All others: 3 timers: 48 */ 49#define TIMER_GROUP1 0 50#if !defined(MAX_BLACKFIN_GPTIMERS) 51# define MAX_BLACKFIN_GPTIMERS 3 52# define TIMER0_GROUP_REG TIMER_ENABLE 53#endif 54 55#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1) 56#define BFIN_TIMER_OCTET(x) ((x) >> 3) 57 58/* used in masks for timer_enable() and timer_disable() */ 59#define TIMER0bit 0x0001 /* 0001b */ 60#define TIMER1bit 0x0002 /* 0010b */ 61#define TIMER2bit 0x0004 /* 0100b */ 62#define TIMER3bit 0x0008 63#define TIMER4bit 0x0010 64#define TIMER5bit 0x0020 65#define TIMER6bit 0x0040 66#define TIMER7bit 0x0080 67#define TIMER8bit 0x0100 68#define TIMER9bit 0x0200 69#define TIMER10bit 0x0400 70#define TIMER11bit 0x0800 71 72#define TIMER0_id 0 73#define TIMER1_id 1 74#define TIMER2_id 2 75#define TIMER3_id 3 76#define TIMER4_id 4 77#define TIMER5_id 5 78#define TIMER6_id 6 79#define TIMER7_id 7 80#define TIMER8_id 8 81#define TIMER9_id 9 82#define TIMER10_id 10 83#define TIMER11_id 11 84 85/* associated timers for ppi framesync: */ 86 87#if defined(CONFIG_BF561) 88# define FS0_1_TIMER_ID TIMER8_id 89# define FS0_2_TIMER_ID TIMER9_id 90# define FS1_1_TIMER_ID TIMER10_id 91# define FS1_2_TIMER_ID TIMER11_id 92# define FS0_1_TIMER_BIT TIMER8bit 93# define FS0_2_TIMER_BIT TIMER9bit 94# define FS1_1_TIMER_BIT TIMER10bit 95# define FS1_2_TIMER_BIT TIMER11bit 96# undef FS1_TIMER_ID 97# undef FS2_TIMER_ID 98# undef FS1_TIMER_BIT 99# undef FS2_TIMER_BIT 100#else 101# define FS1_TIMER_ID TIMER0_id 102# define FS2_TIMER_ID TIMER1_id 103# define FS1_TIMER_BIT TIMER0bit 104# define FS2_TIMER_BIT TIMER1bit 105#endif 106 107/* 108 * Timer Configuration Register Bits 109 */ 110#define TIMER_ERR 0xC000 111#define TIMER_ERR_OVFL 0x4000 112#define TIMER_ERR_PROG_PER 0x8000 113#define TIMER_ERR_PROG_PW 0xC000 114#define TIMER_EMU_RUN 0x0200 115#define TIMER_TOGGLE_HI 0x0100 116#define TIMER_CLK_SEL 0x0080 117#define TIMER_OUT_DIS 0x0040 118#define TIMER_TIN_SEL 0x0020 119#define TIMER_IRQ_ENA 0x0010 120#define TIMER_PERIOD_CNT 0x0008 121#define TIMER_PULSE_HI 0x0004 122#define TIMER_MODE 0x0003 123#define TIMER_MODE_PWM 0x0001 124#define TIMER_MODE_WDTH 0x0002 125#define TIMER_MODE_EXT_CLK 0x0003 126 127/* 128 * Timer Status Register Bits 129 */ 130#define TIMER_STATUS_TIMIL0 0x0001 131#define TIMER_STATUS_TIMIL1 0x0002 132#define TIMER_STATUS_TIMIL2 0x0004 133#define TIMER_STATUS_TIMIL3 0x00000008 134#define TIMER_STATUS_TIMIL4 0x00010000 135#define TIMER_STATUS_TIMIL5 0x00020000 136#define TIMER_STATUS_TIMIL6 0x00040000 137#define TIMER_STATUS_TIMIL7 0x00080000 138#define TIMER_STATUS_TIMIL8 0x0001 139#define TIMER_STATUS_TIMIL9 0x0002 140#define TIMER_STATUS_TIMIL10 0x0004 141#define TIMER_STATUS_TIMIL11 0x0008 142 143#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ 144#define TIMER_STATUS_TOVF1 0x0020 145#define TIMER_STATUS_TOVF2 0x0040 146#define TIMER_STATUS_TOVF3 0x00000080 147#define TIMER_STATUS_TOVF4 0x00100000 148#define TIMER_STATUS_TOVF5 0x00200000 149#define TIMER_STATUS_TOVF6 0x00400000 150#define TIMER_STATUS_TOVF7 0x00800000 151#define TIMER_STATUS_TOVF8 0x0010 152#define TIMER_STATUS_TOVF9 0x0020 153#define TIMER_STATUS_TOVF10 0x0040 154#define TIMER_STATUS_TOVF11 0x0080 155 156/* 157 * Timer Slave Enable Status : write 1 to clear 158 */ 159#define TIMER_STATUS_TRUN0 0x1000 160#define TIMER_STATUS_TRUN1 0x2000 161#define TIMER_STATUS_TRUN2 0x4000 162#define TIMER_STATUS_TRUN3 0x00008000 163#define TIMER_STATUS_TRUN4 0x10000000 164#define TIMER_STATUS_TRUN5 0x20000000 165#define TIMER_STATUS_TRUN6 0x40000000 166#define TIMER_STATUS_TRUN7 0x80000000 167#define TIMER_STATUS_TRUN 0xF000F000 168#define TIMER_STATUS_TRUN8 0x1000 169#define TIMER_STATUS_TRUN9 0x2000 170#define TIMER_STATUS_TRUN10 0x4000 171#define TIMER_STATUS_TRUN11 0x8000 172 173/* The actual gptimer API */ 174 175void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); 176uint32_t get_gptimer_pwidth(unsigned int timer_id); 177void set_gptimer_period(unsigned int timer_id, uint32_t period); 178uint32_t get_gptimer_period(unsigned int timer_id); 179uint32_t get_gptimer_count(unsigned int timer_id); 180int get_gptimer_intr(unsigned int timer_id); 181void clear_gptimer_intr(unsigned int timer_id); 182int get_gptimer_over(unsigned int timer_id); 183void clear_gptimer_over(unsigned int timer_id); 184void set_gptimer_config(unsigned int timer_id, uint16_t config); 185uint16_t get_gptimer_config(unsigned int timer_id); 186int get_gptimer_run(unsigned int timer_id); 187void set_gptimer_pulse_hi(unsigned int timer_id); 188void clear_gptimer_pulse_hi(unsigned int timer_id); 189void enable_gptimers(uint16_t mask); 190void disable_gptimers(uint16_t mask); 191void disable_gptimers_sync(uint16_t mask); 192uint16_t get_enabled_gptimers(void); 193uint32_t get_gptimer_status(unsigned int group); 194void set_gptimer_status(unsigned int group, uint32_t value); 195 196static inline void enable_gptimer(unsigned int timer_id) 197{ 198 enable_gptimers(1 << timer_id); 199} 200 201static inline void disable_gptimer(unsigned int timer_id) 202{ 203 disable_gptimers(1 << timer_id); 204} 205 206/* 207 * All Blackfin system MMRs are padded to 32bits even if the register 208 * itself is only 16bits. So use a helper macro to streamline this. 209 */ 210#define __BFP(m) u16 m; u16 __pad_##m 211 212/* 213 * bfin timer registers layout 214 */ 215struct bfin_gptimer_regs { 216 __BFP(config); 217 u32 counter; 218 u32 period; 219 u32 width; 220}; 221 222/* 223 * bfin group timer registers layout 224 */ 225struct bfin_gptimer_group_regs { 226 __BFP(enable); 227 __BFP(disable); 228 u32 status; 229}; 230 231#undef __BFP 232 233#endif 234