LXR linux/arch/m68k/include/asm/traps.h

   1/*
   2 *  linux/include/asm/traps.h
   3 *
   4 *  Copyright (C) 1993        Hamish Macdonald
   5 *
   6 * This file is subject to the terms and conditions of the GNU General Public
   7 * License.  See the file COPYING in the main directory of this archive
   8 * for more details.
   9 */
  10
  11#ifndef _M68K_TRAPS_H
  12#define _M68K_TRAPS_H
  13
  14#ifndef __ASSEMBLY__
  15
  16#include <linux/linkage.h>
  17#include <asm/ptrace.h>
  18
  19typedef void (*e_vector)(void);
  20extern e_vector vectors[];
  21
  22asmlinkage void auto_inthandler(void);
  23asmlinkage void user_inthandler(void);
  24asmlinkage void bad_inthandler(void);
  25
  26#endif
  27
  28#define VEC_RESETSP (0)
  29#define VEC_RESETPC (1)
  30#define VEC_BUSERR  (2)
  31#define VEC_ADDRERR (3)
  32#define VEC_ILLEGAL (4)
  33#define VEC_ZERODIV (5)
  34#define VEC_CHK     (6)
  35#define VEC_TRAP    (7)
  36#define VEC_PRIV    (8)
  37#define VEC_TRACE   (9)
  38#define VEC_LINE10  (10)
  39#define VEC_LINE11  (11)
  40#define VEC_RESV12  (12)
  41#define VEC_COPROC  (13)
  42#define VEC_FORMAT  (14)
  43#define VEC_UNINT   (15)
  44#define VEC_RESV16  (16)
  45#define VEC_RESV17  (17)
  46#define VEC_RESV18  (18)
  47#define VEC_RESV19  (19)
  48#define VEC_RESV20  (20)
  49#define VEC_RESV21  (21)
  50#define VEC_RESV22  (22)
  51#define VEC_RESV23  (23)
  52#define VEC_SPUR    (24)
  53#define VEC_INT1    (25)
  54#define VEC_INT2    (26)
  55#define VEC_INT3    (27)
  56#define VEC_INT4    (28)
  57#define VEC_INT5    (29)
  58#define VEC_INT6    (30)
  59#define VEC_INT7    (31)
  60#define VEC_SYS     (32)
  61#define VEC_TRAP1   (33)
  62#define VEC_TRAP2   (34)
  63#define VEC_TRAP3   (35)
  64#define VEC_TRAP4   (36)
  65#define VEC_TRAP5   (37)
  66#define VEC_TRAP6   (38)
  67#define VEC_TRAP7   (39)
  68#define VEC_TRAP8   (40)
  69#define VEC_TRAP9   (41)
  70#define VEC_TRAP10  (42)
  71#define VEC_TRAP11  (43)
  72#define VEC_TRAP12  (44)
  73#define VEC_TRAP13  (45)
  74#define VEC_TRAP14  (46)
  75#define VEC_TRAP15  (47)
  76#define VEC_FPBRUC  (48)
  77#define VEC_FPIR    (49)
  78#define VEC_FPDIVZ  (50)
  79#define VEC_FPUNDER (51)
  80#define VEC_FPOE    (52)
  81#define VEC_FPOVER  (53)
  82#define VEC_FPNAN   (54)
  83#define VEC_FPUNSUP (55)
  84#define VEC_MMUCFG  (56)
  85#define VEC_MMUILL  (57)
  86#define VEC_MMUACC  (58)
  87#define VEC_RESV59  (59)
  88#define VEC_UNIMPEA (60)
  89#define VEC_UNIMPII (61)
  90#define VEC_RESV62  (62)
  91#define VEC_RESV63  (63)
  92#define VEC_USER    (64)
  93
  94#define VECOFF(vec) ((vec)<<2)
  95
  96#ifndef __ASSEMBLY__
  97
  98/* Status register bits */
  99#define PS_T  (0x8000)
 100#define PS_S  (0x2000)
 101#define PS_M  (0x1000)
 102#define PS_C  (0x0001)
 103
 104/* bits for 68020/68030 special status word */
 105
 106#define FC    (0x8000)
 107#define FB    (0x4000)
 108#define RC    (0x2000)
 109#define RB    (0x1000)
 110#define DF    (0x0100)
 111#define RM    (0x0080)
 112#define RW    (0x0040)
 113#define SZ    (0x0030)
 114#define DFC   (0x0007)
 115
 116/* bits for 68030 MMU status register (mmusr,psr) */
 117
 118#define MMU_B        (0x8000)    /* bus error */
 119#define MMU_L        (0x4000)    /* limit violation */
 120#define MMU_S        (0x2000)    /* supervisor violation */
 121#define MMU_WP       (0x0800)    /* write-protected */
 122#define MMU_I        (0x0400)    /* invalid descriptor */
 123#define MMU_M        (0x0200)    /* ATC entry modified */
 124#define MMU_T        (0x0040)    /* transparent translation */
 125#define MMU_NUM      (0x0007)    /* number of levels traversed */
 126
 127
 128/* bits for 68040 special status word */
 129#define CP_040  (0x8000)
 130#define CU_040  (0x4000)
 131#define CT_040  (0x2000)
 132#define CM_040  (0x1000)
 133#define MA_040  (0x0800)
 134#define ATC_040 (0x0400)
 135#define LK_040  (0x0200)
 136#define RW_040  (0x0100)
 137#define SIZ_040 (0x0060)
 138#define TT_040  (0x0018)
 139#define TM_040  (0x0007)
 140
 141/* bits for 68040 write back status word */
 142#define WBV_040   (0x80)
 143#define WBSIZ_040 (0x60)
 144#define WBBYT_040 (0x20)
 145#define WBWRD_040 (0x40)
 146#define WBLNG_040 (0x00)
 147#define WBTT_040  (0x18)
 148#define WBTM_040  (0x07)
 149
 150/* bus access size codes */
 151#define BA_SIZE_BYTE    (0x20)
 152#define BA_SIZE_WORD    (0x40)
 153#define BA_SIZE_LONG    (0x00)
 154#define BA_SIZE_LINE    (0x60)
 155
 156/* bus access transfer type codes */
 157#define BA_TT_MOVE16    (0x08)
 158
 159/* bits for 68040 MMU status register (mmusr) */
 160#define MMU_B_040   (0x0800)
 161#define MMU_G_040   (0x0400)
 162#define MMU_S_040   (0x0080)
 163#define MMU_CM_040  (0x0060)
 164#define MMU_M_040   (0x0010)
 165#define MMU_WP_040  (0x0004)
 166#define MMU_T_040   (0x0002)
 167#define MMU_R_040   (0x0001)
 168
 169/* bits in the 68060 fault status long word (FSLW) */
 170#define MMU060_MA       (0x08000000)    /* misaligned */
 171#define MMU060_LK       (0x02000000)    /* locked transfer */
 172#define MMU060_RW       (0x01800000)    /* read/write */
 173# define MMU060_RW_W    (0x00800000)    /* write */
 174# define MMU060_RW_R    (0x01000000)    /* read */
 175# define MMU060_RW_RMW  (0x01800000)    /* read/modify/write */
 176# define MMU060_W       (0x00800000)    /* general write, includes rmw */
 177#define MMU060_SIZ      (0x00600000)    /* transfer size */
 178#define MMU060_TT       (0x00180000)    /* transfer type (TT) bits */
 179#define MMU060_TM       (0x00070000)    /* transfer modifier (TM) bits */
 180#define MMU060_IO       (0x00008000)    /* instruction or operand */
 181#define MMU060_PBE      (0x00004000)    /* push buffer bus error */
 182#define MMU060_SBE      (0x00002000)    /* store buffer bus error */
 183#define MMU060_PTA      (0x00001000)    /* pointer A fault */
 184#define MMU060_PTB      (0x00000800)    /* pointer B fault */
 185#define MMU060_IL       (0x00000400)    /* double indirect descr fault */
 186#define MMU060_PF       (0x00000200)    /* page fault (invalid descr) */
 187#define MMU060_SP       (0x00000100)    /* supervisor protection */
 188#define MMU060_WP       (0x00000080)    /* write protection */
 189#define MMU060_TWE      (0x00000040)    /* bus error on table search */
 190#define MMU060_RE       (0x00000020)    /* bus error on read */
 191#define MMU060_WE       (0x00000010)    /* bus error on write */
 192#define MMU060_TTR      (0x00000008)    /* error caused by TTR translation */
 193#define MMU060_BPE      (0x00000004)    /* branch prediction error */
 194#define MMU060_SEE      (0x00000001)    /* software emulated error */
 195
 196/* cases of missing or invalid descriptors */
 197#define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \
 198                         MMU060_IL  | MMU060_PF)
 199/* bits that indicate real errors */
 200#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \
 201                         MMU060_WP  | MMU060_TWE | MMU060_RE       | MMU060_WE)
 202
 203/* structure for stack frames */
 204
 205struct frame {
 206    struct pt_regs ptregs;
 207    union {
 208            struct {
 209                    unsigned long  iaddr;    /* instruction address */
 210            } fmt2;
 211            struct {
 212                    unsigned long  effaddr;  /* effective address */
 213            } fmt3;
 214            struct {
 215                    unsigned long  effaddr;  /* effective address */
 216                    unsigned long  pc;       /* pc of faulted instr */
 217            } fmt4;
 218            struct {
 219                    unsigned long  effaddr;  /* effective address */
 220                    unsigned short ssw;      /* special status word */
 221                    unsigned short wb3s;     /* write back 3 status */
 222                    unsigned short wb2s;     /* write back 2 status */
 223                    unsigned short wb1s;     /* write back 1 status */
 224                    unsigned long  faddr;    /* fault address */
 225                    unsigned long  wb3a;     /* write back 3 address */
 226                    unsigned long  wb3d;     /* write back 3 data */
 227                    unsigned long  wb2a;     /* write back 2 address */
 228                    unsigned long  wb2d;     /* write back 2 data */
 229                    unsigned long  wb1a;     /* write back 1 address */
 230                    unsigned long  wb1dpd0;  /* write back 1 data/push data 0*/
 231                    unsigned long  pd1;      /* push data 1*/
 232                    unsigned long  pd2;      /* push data 2*/
 233                    unsigned long  pd3;      /* push data 3*/
 234            } fmt7;
 235            struct {
 236                    unsigned long  iaddr;    /* instruction address */
 237                    unsigned short int1[4];  /* internal registers */
 238            } fmt9;
 239            struct {
 240                    unsigned short int1;
 241                    unsigned short ssw;      /* special status word */
 242                    unsigned short isc;      /* instruction stage c */
 243                    unsigned short isb;      /* instruction stage b */
 244                    unsigned long  daddr;    /* data cycle fault address */
 245                    unsigned short int2[2];
 246                    unsigned long  dobuf;    /* data cycle output buffer */
 247                    unsigned short int3[2];
 248            } fmta;
 249            struct {
 250                    unsigned short int1;
 251                    unsigned short ssw;     /* special status word */
 252                    unsigned short isc;     /* instruction stage c */
 253                    unsigned short isb;     /* instruction stage b */
 254                    unsigned long  daddr;   /* data cycle fault address */
 255                    unsigned short int2[2];
 256                    unsigned long  dobuf;   /* data cycle output buffer */
 257                    unsigned short int3[4];
 258                    unsigned long  baddr;   /* stage B address */
 259                    unsigned short int4[2];
 260                    unsigned long  dibuf;   /* data cycle input buffer */
 261                    unsigned short int5[3];
 262                    unsigned       ver : 4; /* stack frame version # */
 263                    unsigned       int6:12;
 264                    unsigned short int7[18];
 265            } fmtb;
 266    } un;
 267};
 268
 269#endif /* __ASSEMBLY__ */
 270
 271#endif /* _M68K_TRAPS_H */
 272