1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2010 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_POW_DEFS_H__ 29#define __CVMX_POW_DEFS_H__ 30 31#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull)) 32#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull)) 33#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull)) 34#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull)) 35#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8) 36#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull)) 37#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull)) 38#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull)) 39#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8) 40#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull)) 41#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull)) 42#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull)) 43#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8) 44#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8) 45#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8) 46#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull)) 47#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull)) 48#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8) 49#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull)) 50#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8) 51#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull)) 52#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8) 53#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8) 54 55union cvmx_pow_bist_stat { 56 uint64_t u64; 57 struct cvmx_pow_bist_stat_s { 58 uint64_t reserved_32_63:32; 59 uint64_t pp:16; 60 uint64_t reserved_0_15:16; 61 } s; 62 struct cvmx_pow_bist_stat_cn30xx { 63 uint64_t reserved_17_63:47; 64 uint64_t pp:1; 65 uint64_t reserved_9_15:7; 66 uint64_t cam:1; 67 uint64_t nbt1:1; 68 uint64_t nbt0:1; 69 uint64_t index:1; 70 uint64_t fidx:1; 71 uint64_t nbr1:1; 72 uint64_t nbr0:1; 73 uint64_t pend:1; 74 uint64_t adr:1; 75 } cn30xx; 76 struct cvmx_pow_bist_stat_cn31xx { 77 uint64_t reserved_18_63:46; 78 uint64_t pp:2; 79 uint64_t reserved_9_15:7; 80 uint64_t cam:1; 81 uint64_t nbt1:1; 82 uint64_t nbt0:1; 83 uint64_t index:1; 84 uint64_t fidx:1; 85 uint64_t nbr1:1; 86 uint64_t nbr0:1; 87 uint64_t pend:1; 88 uint64_t adr:1; 89 } cn31xx; 90 struct cvmx_pow_bist_stat_cn38xx { 91 uint64_t reserved_32_63:32; 92 uint64_t pp:16; 93 uint64_t reserved_10_15:6; 94 uint64_t cam:1; 95 uint64_t nbt:1; 96 uint64_t index:1; 97 uint64_t fidx:1; 98 uint64_t nbr1:1; 99 uint64_t nbr0:1; 100 uint64_t pend1:1; 101 uint64_t pend0:1; 102 uint64_t adr1:1; 103 uint64_t adr0:1; 104 } cn38xx; 105 struct cvmx_pow_bist_stat_cn38xx cn38xxp2; 106 struct cvmx_pow_bist_stat_cn31xx cn50xx; 107 struct cvmx_pow_bist_stat_cn52xx { 108 uint64_t reserved_20_63:44; 109 uint64_t pp:4; 110 uint64_t reserved_9_15:7; 111 uint64_t cam:1; 112 uint64_t nbt1:1; 113 uint64_t nbt0:1; 114 uint64_t index:1; 115 uint64_t fidx:1; 116 uint64_t nbr1:1; 117 uint64_t nbr0:1; 118 uint64_t pend:1; 119 uint64_t adr:1; 120 } cn52xx; 121 struct cvmx_pow_bist_stat_cn52xx cn52xxp1; 122 struct cvmx_pow_bist_stat_cn56xx { 123 uint64_t reserved_28_63:36; 124 uint64_t pp:12; 125 uint64_t reserved_10_15:6; 126 uint64_t cam:1; 127 uint64_t nbt:1; 128 uint64_t index:1; 129 uint64_t fidx:1; 130 uint64_t nbr1:1; 131 uint64_t nbr0:1; 132 uint64_t pend1:1; 133 uint64_t pend0:1; 134 uint64_t adr1:1; 135 uint64_t adr0:1; 136 } cn56xx; 137 struct cvmx_pow_bist_stat_cn56xx cn56xxp1; 138 struct cvmx_pow_bist_stat_cn38xx cn58xx; 139 struct cvmx_pow_bist_stat_cn38xx cn58xxp1; 140 struct cvmx_pow_bist_stat_cn63xx { 141 uint64_t reserved_22_63:42; 142 uint64_t pp:6; 143 uint64_t reserved_12_15:4; 144 uint64_t cam:1; 145 uint64_t nbr:3; 146 uint64_t nbt:4; 147 uint64_t index:1; 148 uint64_t fidx:1; 149 uint64_t pend:1; 150 uint64_t adr:1; 151 } cn63xx; 152 struct cvmx_pow_bist_stat_cn63xx cn63xxp1; 153}; 154 155union cvmx_pow_ds_pc { 156 uint64_t u64; 157 struct cvmx_pow_ds_pc_s { 158 uint64_t reserved_32_63:32; 159 uint64_t ds_pc:32; 160 } s; 161 struct cvmx_pow_ds_pc_s cn30xx; 162 struct cvmx_pow_ds_pc_s cn31xx; 163 struct cvmx_pow_ds_pc_s cn38xx; 164 struct cvmx_pow_ds_pc_s cn38xxp2; 165 struct cvmx_pow_ds_pc_s cn50xx; 166 struct cvmx_pow_ds_pc_s cn52xx; 167 struct cvmx_pow_ds_pc_s cn52xxp1; 168 struct cvmx_pow_ds_pc_s cn56xx; 169 struct cvmx_pow_ds_pc_s cn56xxp1; 170 struct cvmx_pow_ds_pc_s cn58xx; 171 struct cvmx_pow_ds_pc_s cn58xxp1; 172 struct cvmx_pow_ds_pc_s cn63xx; 173 struct cvmx_pow_ds_pc_s cn63xxp1; 174}; 175 176union cvmx_pow_ecc_err { 177 uint64_t u64; 178 struct cvmx_pow_ecc_err_s { 179 uint64_t reserved_45_63:19; 180 uint64_t iop_ie:13; 181 uint64_t reserved_29_31:3; 182 uint64_t iop:13; 183 uint64_t reserved_14_15:2; 184 uint64_t rpe_ie:1; 185 uint64_t rpe:1; 186 uint64_t reserved_9_11:3; 187 uint64_t syn:5; 188 uint64_t dbe_ie:1; 189 uint64_t sbe_ie:1; 190 uint64_t dbe:1; 191 uint64_t sbe:1; 192 } s; 193 struct cvmx_pow_ecc_err_s cn30xx; 194 struct cvmx_pow_ecc_err_cn31xx { 195 uint64_t reserved_14_63:50; 196 uint64_t rpe_ie:1; 197 uint64_t rpe:1; 198 uint64_t reserved_9_11:3; 199 uint64_t syn:5; 200 uint64_t dbe_ie:1; 201 uint64_t sbe_ie:1; 202 uint64_t dbe:1; 203 uint64_t sbe:1; 204 } cn31xx; 205 struct cvmx_pow_ecc_err_s cn38xx; 206 struct cvmx_pow_ecc_err_cn31xx cn38xxp2; 207 struct cvmx_pow_ecc_err_s cn50xx; 208 struct cvmx_pow_ecc_err_s cn52xx; 209 struct cvmx_pow_ecc_err_s cn52xxp1; 210 struct cvmx_pow_ecc_err_s cn56xx; 211 struct cvmx_pow_ecc_err_s cn56xxp1; 212 struct cvmx_pow_ecc_err_s cn58xx; 213 struct cvmx_pow_ecc_err_s cn58xxp1; 214 struct cvmx_pow_ecc_err_s cn63xx; 215 struct cvmx_pow_ecc_err_s cn63xxp1; 216}; 217 218union cvmx_pow_int_ctl { 219 uint64_t u64; 220 struct cvmx_pow_int_ctl_s { 221 uint64_t reserved_6_63:58; 222 uint64_t pfr_dis:1; 223 uint64_t nbr_thr:5; 224 } s; 225 struct cvmx_pow_int_ctl_s cn30xx; 226 struct cvmx_pow_int_ctl_s cn31xx; 227 struct cvmx_pow_int_ctl_s cn38xx; 228 struct cvmx_pow_int_ctl_s cn38xxp2; 229 struct cvmx_pow_int_ctl_s cn50xx; 230 struct cvmx_pow_int_ctl_s cn52xx; 231 struct cvmx_pow_int_ctl_s cn52xxp1; 232 struct cvmx_pow_int_ctl_s cn56xx; 233 struct cvmx_pow_int_ctl_s cn56xxp1; 234 struct cvmx_pow_int_ctl_s cn58xx; 235 struct cvmx_pow_int_ctl_s cn58xxp1; 236 struct cvmx_pow_int_ctl_s cn63xx; 237 struct cvmx_pow_int_ctl_s cn63xxp1; 238}; 239 240union cvmx_pow_iq_cntx { 241 uint64_t u64; 242 struct cvmx_pow_iq_cntx_s { 243 uint64_t reserved_32_63:32; 244 uint64_t iq_cnt:32; 245 } s; 246 struct cvmx_pow_iq_cntx_s cn30xx; 247 struct cvmx_pow_iq_cntx_s cn31xx; 248 struct cvmx_pow_iq_cntx_s cn38xx; 249 struct cvmx_pow_iq_cntx_s cn38xxp2; 250 struct cvmx_pow_iq_cntx_s cn50xx; 251 struct cvmx_pow_iq_cntx_s cn52xx; 252 struct cvmx_pow_iq_cntx_s cn52xxp1; 253 struct cvmx_pow_iq_cntx_s cn56xx; 254 struct cvmx_pow_iq_cntx_s cn56xxp1; 255 struct cvmx_pow_iq_cntx_s cn58xx; 256 struct cvmx_pow_iq_cntx_s cn58xxp1; 257 struct cvmx_pow_iq_cntx_s cn63xx; 258 struct cvmx_pow_iq_cntx_s cn63xxp1; 259}; 260 261union cvmx_pow_iq_com_cnt { 262 uint64_t u64; 263 struct cvmx_pow_iq_com_cnt_s { 264 uint64_t reserved_32_63:32; 265 uint64_t iq_cnt:32; 266 } s; 267 struct cvmx_pow_iq_com_cnt_s cn30xx; 268 struct cvmx_pow_iq_com_cnt_s cn31xx; 269 struct cvmx_pow_iq_com_cnt_s cn38xx; 270 struct cvmx_pow_iq_com_cnt_s cn38xxp2; 271 struct cvmx_pow_iq_com_cnt_s cn50xx; 272 struct cvmx_pow_iq_com_cnt_s cn52xx; 273 struct cvmx_pow_iq_com_cnt_s cn52xxp1; 274 struct cvmx_pow_iq_com_cnt_s cn56xx; 275 struct cvmx_pow_iq_com_cnt_s cn56xxp1; 276 struct cvmx_pow_iq_com_cnt_s cn58xx; 277 struct cvmx_pow_iq_com_cnt_s cn58xxp1; 278 struct cvmx_pow_iq_com_cnt_s cn63xx; 279 struct cvmx_pow_iq_com_cnt_s cn63xxp1; 280}; 281 282union cvmx_pow_iq_int { 283 uint64_t u64; 284 struct cvmx_pow_iq_int_s { 285 uint64_t reserved_8_63:56; 286 uint64_t iq_int:8; 287 } s; 288 struct cvmx_pow_iq_int_s cn52xx; 289 struct cvmx_pow_iq_int_s cn52xxp1; 290 struct cvmx_pow_iq_int_s cn56xx; 291 struct cvmx_pow_iq_int_s cn56xxp1; 292 struct cvmx_pow_iq_int_s cn63xx; 293 struct cvmx_pow_iq_int_s cn63xxp1; 294}; 295 296union cvmx_pow_iq_int_en { 297 uint64_t u64; 298 struct cvmx_pow_iq_int_en_s { 299 uint64_t reserved_8_63:56; 300 uint64_t int_en:8; 301 } s; 302 struct cvmx_pow_iq_int_en_s cn52xx; 303 struct cvmx_pow_iq_int_en_s cn52xxp1; 304 struct cvmx_pow_iq_int_en_s cn56xx; 305 struct cvmx_pow_iq_int_en_s cn56xxp1; 306 struct cvmx_pow_iq_int_en_s cn63xx; 307 struct cvmx_pow_iq_int_en_s cn63xxp1; 308}; 309 310union cvmx_pow_iq_thrx { 311 uint64_t u64; 312 struct cvmx_pow_iq_thrx_s { 313 uint64_t reserved_32_63:32; 314 uint64_t iq_thr:32; 315 } s; 316 struct cvmx_pow_iq_thrx_s cn52xx; 317 struct cvmx_pow_iq_thrx_s cn52xxp1; 318 struct cvmx_pow_iq_thrx_s cn56xx; 319 struct cvmx_pow_iq_thrx_s cn56xxp1; 320 struct cvmx_pow_iq_thrx_s cn63xx; 321 struct cvmx_pow_iq_thrx_s cn63xxp1; 322}; 323 324union cvmx_pow_nos_cnt { 325 uint64_t u64; 326 struct cvmx_pow_nos_cnt_s { 327 uint64_t reserved_12_63:52; 328 uint64_t nos_cnt:12; 329 } s; 330 struct cvmx_pow_nos_cnt_cn30xx { 331 uint64_t reserved_7_63:57; 332 uint64_t nos_cnt:7; 333 } cn30xx; 334 struct cvmx_pow_nos_cnt_cn31xx { 335 uint64_t reserved_9_63:55; 336 uint64_t nos_cnt:9; 337 } cn31xx; 338 struct cvmx_pow_nos_cnt_s cn38xx; 339 struct cvmx_pow_nos_cnt_s cn38xxp2; 340 struct cvmx_pow_nos_cnt_cn31xx cn50xx; 341 struct cvmx_pow_nos_cnt_cn52xx { 342 uint64_t reserved_10_63:54; 343 uint64_t nos_cnt:10; 344 } cn52xx; 345 struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; 346 struct cvmx_pow_nos_cnt_s cn56xx; 347 struct cvmx_pow_nos_cnt_s cn56xxp1; 348 struct cvmx_pow_nos_cnt_s cn58xx; 349 struct cvmx_pow_nos_cnt_s cn58xxp1; 350 struct cvmx_pow_nos_cnt_cn63xx { 351 uint64_t reserved_11_63:53; 352 uint64_t nos_cnt:11; 353 } cn63xx; 354 struct cvmx_pow_nos_cnt_cn63xx cn63xxp1; 355}; 356 357union cvmx_pow_nw_tim { 358 uint64_t u64; 359 struct cvmx_pow_nw_tim_s { 360 uint64_t reserved_10_63:54; 361 uint64_t nw_tim:10; 362 } s; 363 struct cvmx_pow_nw_tim_s cn30xx; 364 struct cvmx_pow_nw_tim_s cn31xx; 365 struct cvmx_pow_nw_tim_s cn38xx; 366 struct cvmx_pow_nw_tim_s cn38xxp2; 367 struct cvmx_pow_nw_tim_s cn50xx; 368 struct cvmx_pow_nw_tim_s cn52xx; 369 struct cvmx_pow_nw_tim_s cn52xxp1; 370 struct cvmx_pow_nw_tim_s cn56xx; 371 struct cvmx_pow_nw_tim_s cn56xxp1; 372 struct cvmx_pow_nw_tim_s cn58xx; 373 struct cvmx_pow_nw_tim_s cn58xxp1; 374 struct cvmx_pow_nw_tim_s cn63xx; 375 struct cvmx_pow_nw_tim_s cn63xxp1; 376}; 377 378union cvmx_pow_pf_rst_msk { 379 uint64_t u64; 380 struct cvmx_pow_pf_rst_msk_s { 381 uint64_t reserved_8_63:56; 382 uint64_t rst_msk:8; 383 } s; 384 struct cvmx_pow_pf_rst_msk_s cn50xx; 385 struct cvmx_pow_pf_rst_msk_s cn52xx; 386 struct cvmx_pow_pf_rst_msk_s cn52xxp1; 387 struct cvmx_pow_pf_rst_msk_s cn56xx; 388 struct cvmx_pow_pf_rst_msk_s cn56xxp1; 389 struct cvmx_pow_pf_rst_msk_s cn58xx; 390 struct cvmx_pow_pf_rst_msk_s cn58xxp1; 391 struct cvmx_pow_pf_rst_msk_s cn63xx; 392 struct cvmx_pow_pf_rst_msk_s cn63xxp1; 393}; 394 395union cvmx_pow_pp_grp_mskx { 396 uint64_t u64; 397 struct cvmx_pow_pp_grp_mskx_s { 398 uint64_t reserved_48_63:16; 399 uint64_t qos7_pri:4; 400 uint64_t qos6_pri:4; 401 uint64_t qos5_pri:4; 402 uint64_t qos4_pri:4; 403 uint64_t qos3_pri:4; 404 uint64_t qos2_pri:4; 405 uint64_t qos1_pri:4; 406 uint64_t qos0_pri:4; 407 uint64_t grp_msk:16; 408 } s; 409 struct cvmx_pow_pp_grp_mskx_cn30xx { 410 uint64_t reserved_16_63:48; 411 uint64_t grp_msk:16; 412 } cn30xx; 413 struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; 414 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; 415 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2; 416 struct cvmx_pow_pp_grp_mskx_s cn50xx; 417 struct cvmx_pow_pp_grp_mskx_s cn52xx; 418 struct cvmx_pow_pp_grp_mskx_s cn52xxp1; 419 struct cvmx_pow_pp_grp_mskx_s cn56xx; 420 struct cvmx_pow_pp_grp_mskx_s cn56xxp1; 421 struct cvmx_pow_pp_grp_mskx_s cn58xx; 422 struct cvmx_pow_pp_grp_mskx_s cn58xxp1; 423 struct cvmx_pow_pp_grp_mskx_s cn63xx; 424 struct cvmx_pow_pp_grp_mskx_s cn63xxp1; 425}; 426 427union cvmx_pow_qos_rndx { 428 uint64_t u64; 429 struct cvmx_pow_qos_rndx_s { 430 uint64_t reserved_32_63:32; 431 uint64_t rnd_p3:8; 432 uint64_t rnd_p2:8; 433 uint64_t rnd_p1:8; 434 uint64_t rnd:8; 435 } s; 436 struct cvmx_pow_qos_rndx_s cn30xx; 437 struct cvmx_pow_qos_rndx_s cn31xx; 438 struct cvmx_pow_qos_rndx_s cn38xx; 439 struct cvmx_pow_qos_rndx_s cn38xxp2; 440 struct cvmx_pow_qos_rndx_s cn50xx; 441 struct cvmx_pow_qos_rndx_s cn52xx; 442 struct cvmx_pow_qos_rndx_s cn52xxp1; 443 struct cvmx_pow_qos_rndx_s cn56xx; 444 struct cvmx_pow_qos_rndx_s cn56xxp1; 445 struct cvmx_pow_qos_rndx_s cn58xx; 446 struct cvmx_pow_qos_rndx_s cn58xxp1; 447 struct cvmx_pow_qos_rndx_s cn63xx; 448 struct cvmx_pow_qos_rndx_s cn63xxp1; 449}; 450 451union cvmx_pow_qos_thrx { 452 uint64_t u64; 453 struct cvmx_pow_qos_thrx_s { 454 uint64_t reserved_60_63:4; 455 uint64_t des_cnt:12; 456 uint64_t buf_cnt:12; 457 uint64_t free_cnt:12; 458 uint64_t reserved_23_23:1; 459 uint64_t max_thr:11; 460 uint64_t reserved_11_11:1; 461 uint64_t min_thr:11; 462 } s; 463 struct cvmx_pow_qos_thrx_cn30xx { 464 uint64_t reserved_55_63:9; 465 uint64_t des_cnt:7; 466 uint64_t reserved_43_47:5; 467 uint64_t buf_cnt:7; 468 uint64_t reserved_31_35:5; 469 uint64_t free_cnt:7; 470 uint64_t reserved_18_23:6; 471 uint64_t max_thr:6; 472 uint64_t reserved_6_11:6; 473 uint64_t min_thr:6; 474 } cn30xx; 475 struct cvmx_pow_qos_thrx_cn31xx { 476 uint64_t reserved_57_63:7; 477 uint64_t des_cnt:9; 478 uint64_t reserved_45_47:3; 479 uint64_t buf_cnt:9; 480 uint64_t reserved_33_35:3; 481 uint64_t free_cnt:9; 482 uint64_t reserved_20_23:4; 483 uint64_t max_thr:8; 484 uint64_t reserved_8_11:4; 485 uint64_t min_thr:8; 486 } cn31xx; 487 struct cvmx_pow_qos_thrx_s cn38xx; 488 struct cvmx_pow_qos_thrx_s cn38xxp2; 489 struct cvmx_pow_qos_thrx_cn31xx cn50xx; 490 struct cvmx_pow_qos_thrx_cn52xx { 491 uint64_t reserved_58_63:6; 492 uint64_t des_cnt:10; 493 uint64_t reserved_46_47:2; 494 uint64_t buf_cnt:10; 495 uint64_t reserved_34_35:2; 496 uint64_t free_cnt:10; 497 uint64_t reserved_21_23:3; 498 uint64_t max_thr:9; 499 uint64_t reserved_9_11:3; 500 uint64_t min_thr:9; 501 } cn52xx; 502 struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; 503 struct cvmx_pow_qos_thrx_s cn56xx; 504 struct cvmx_pow_qos_thrx_s cn56xxp1; 505 struct cvmx_pow_qos_thrx_s cn58xx; 506 struct cvmx_pow_qos_thrx_s cn58xxp1; 507 struct cvmx_pow_qos_thrx_cn63xx { 508 uint64_t reserved_59_63:5; 509 uint64_t des_cnt:11; 510 uint64_t reserved_47_47:1; 511 uint64_t buf_cnt:11; 512 uint64_t reserved_35_35:1; 513 uint64_t free_cnt:11; 514 uint64_t reserved_22_23:2; 515 uint64_t max_thr:10; 516 uint64_t reserved_10_11:2; 517 uint64_t min_thr:10; 518 } cn63xx; 519 struct cvmx_pow_qos_thrx_cn63xx cn63xxp1; 520}; 521 522union cvmx_pow_ts_pc { 523 uint64_t u64; 524 struct cvmx_pow_ts_pc_s { 525 uint64_t reserved_32_63:32; 526 uint64_t ts_pc:32; 527 } s; 528 struct cvmx_pow_ts_pc_s cn30xx; 529 struct cvmx_pow_ts_pc_s cn31xx; 530 struct cvmx_pow_ts_pc_s cn38xx; 531 struct cvmx_pow_ts_pc_s cn38xxp2; 532 struct cvmx_pow_ts_pc_s cn50xx; 533 struct cvmx_pow_ts_pc_s cn52xx; 534 struct cvmx_pow_ts_pc_s cn52xxp1; 535 struct cvmx_pow_ts_pc_s cn56xx; 536 struct cvmx_pow_ts_pc_s cn56xxp1; 537 struct cvmx_pow_ts_pc_s cn58xx; 538 struct cvmx_pow_ts_pc_s cn58xxp1; 539 struct cvmx_pow_ts_pc_s cn63xx; 540 struct cvmx_pow_ts_pc_s cn63xxp1; 541}; 542 543union cvmx_pow_wa_com_pc { 544 uint64_t u64; 545 struct cvmx_pow_wa_com_pc_s { 546 uint64_t reserved_32_63:32; 547 uint64_t wa_pc:32; 548 } s; 549 struct cvmx_pow_wa_com_pc_s cn30xx; 550 struct cvmx_pow_wa_com_pc_s cn31xx; 551 struct cvmx_pow_wa_com_pc_s cn38xx; 552 struct cvmx_pow_wa_com_pc_s cn38xxp2; 553 struct cvmx_pow_wa_com_pc_s cn50xx; 554 struct cvmx_pow_wa_com_pc_s cn52xx; 555 struct cvmx_pow_wa_com_pc_s cn52xxp1; 556 struct cvmx_pow_wa_com_pc_s cn56xx; 557 struct cvmx_pow_wa_com_pc_s cn56xxp1; 558 struct cvmx_pow_wa_com_pc_s cn58xx; 559 struct cvmx_pow_wa_com_pc_s cn58xxp1; 560 struct cvmx_pow_wa_com_pc_s cn63xx; 561 struct cvmx_pow_wa_com_pc_s cn63xxp1; 562}; 563 564union cvmx_pow_wa_pcx { 565 uint64_t u64; 566 struct cvmx_pow_wa_pcx_s { 567 uint64_t reserved_32_63:32; 568 uint64_t wa_pc:32; 569 } s; 570 struct cvmx_pow_wa_pcx_s cn30xx; 571 struct cvmx_pow_wa_pcx_s cn31xx; 572 struct cvmx_pow_wa_pcx_s cn38xx; 573 struct cvmx_pow_wa_pcx_s cn38xxp2; 574 struct cvmx_pow_wa_pcx_s cn50xx; 575 struct cvmx_pow_wa_pcx_s cn52xx; 576 struct cvmx_pow_wa_pcx_s cn52xxp1; 577 struct cvmx_pow_wa_pcx_s cn56xx; 578 struct cvmx_pow_wa_pcx_s cn56xxp1; 579 struct cvmx_pow_wa_pcx_s cn58xx; 580 struct cvmx_pow_wa_pcx_s cn58xxp1; 581 struct cvmx_pow_wa_pcx_s cn63xx; 582 struct cvmx_pow_wa_pcx_s cn63xxp1; 583}; 584 585union cvmx_pow_wq_int { 586 uint64_t u64; 587 struct cvmx_pow_wq_int_s { 588 uint64_t reserved_32_63:32; 589 uint64_t iq_dis:16; 590 uint64_t wq_int:16; 591 } s; 592 struct cvmx_pow_wq_int_s cn30xx; 593 struct cvmx_pow_wq_int_s cn31xx; 594 struct cvmx_pow_wq_int_s cn38xx; 595 struct cvmx_pow_wq_int_s cn38xxp2; 596 struct cvmx_pow_wq_int_s cn50xx; 597 struct cvmx_pow_wq_int_s cn52xx; 598 struct cvmx_pow_wq_int_s cn52xxp1; 599 struct cvmx_pow_wq_int_s cn56xx; 600 struct cvmx_pow_wq_int_s cn56xxp1; 601 struct cvmx_pow_wq_int_s cn58xx; 602 struct cvmx_pow_wq_int_s cn58xxp1; 603 struct cvmx_pow_wq_int_s cn63xx; 604 struct cvmx_pow_wq_int_s cn63xxp1; 605}; 606 607union cvmx_pow_wq_int_cntx { 608 uint64_t u64; 609 struct cvmx_pow_wq_int_cntx_s { 610 uint64_t reserved_28_63:36; 611 uint64_t tc_cnt:4; 612 uint64_t ds_cnt:12; 613 uint64_t iq_cnt:12; 614 } s; 615 struct cvmx_pow_wq_int_cntx_cn30xx { 616 uint64_t reserved_28_63:36; 617 uint64_t tc_cnt:4; 618 uint64_t reserved_19_23:5; 619 uint64_t ds_cnt:7; 620 uint64_t reserved_7_11:5; 621 uint64_t iq_cnt:7; 622 } cn30xx; 623 struct cvmx_pow_wq_int_cntx_cn31xx { 624 uint64_t reserved_28_63:36; 625 uint64_t tc_cnt:4; 626 uint64_t reserved_21_23:3; 627 uint64_t ds_cnt:9; 628 uint64_t reserved_9_11:3; 629 uint64_t iq_cnt:9; 630 } cn31xx; 631 struct cvmx_pow_wq_int_cntx_s cn38xx; 632 struct cvmx_pow_wq_int_cntx_s cn38xxp2; 633 struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; 634 struct cvmx_pow_wq_int_cntx_cn52xx { 635 uint64_t reserved_28_63:36; 636 uint64_t tc_cnt:4; 637 uint64_t reserved_22_23:2; 638 uint64_t ds_cnt:10; 639 uint64_t reserved_10_11:2; 640 uint64_t iq_cnt:10; 641 } cn52xx; 642 struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; 643 struct cvmx_pow_wq_int_cntx_s cn56xx; 644 struct cvmx_pow_wq_int_cntx_s cn56xxp1; 645 struct cvmx_pow_wq_int_cntx_s cn58xx; 646 struct cvmx_pow_wq_int_cntx_s cn58xxp1; 647 struct cvmx_pow_wq_int_cntx_cn63xx { 648 uint64_t reserved_28_63:36; 649 uint64_t tc_cnt:4; 650 uint64_t reserved_23_23:1; 651 uint64_t ds_cnt:11; 652 uint64_t reserved_11_11:1; 653 uint64_t iq_cnt:11; 654 } cn63xx; 655 struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1; 656}; 657 658union cvmx_pow_wq_int_pc { 659 uint64_t u64; 660 struct cvmx_pow_wq_int_pc_s { 661 uint64_t reserved_60_63:4; 662 uint64_t pc:28; 663 uint64_t reserved_28_31:4; 664 uint64_t pc_thr:20; 665 uint64_t reserved_0_7:8; 666 } s; 667 struct cvmx_pow_wq_int_pc_s cn30xx; 668 struct cvmx_pow_wq_int_pc_s cn31xx; 669 struct cvmx_pow_wq_int_pc_s cn38xx; 670 struct cvmx_pow_wq_int_pc_s cn38xxp2; 671 struct cvmx_pow_wq_int_pc_s cn50xx; 672 struct cvmx_pow_wq_int_pc_s cn52xx; 673 struct cvmx_pow_wq_int_pc_s cn52xxp1; 674 struct cvmx_pow_wq_int_pc_s cn56xx; 675 struct cvmx_pow_wq_int_pc_s cn56xxp1; 676 struct cvmx_pow_wq_int_pc_s cn58xx; 677 struct cvmx_pow_wq_int_pc_s cn58xxp1; 678 struct cvmx_pow_wq_int_pc_s cn63xx; 679 struct cvmx_pow_wq_int_pc_s cn63xxp1; 680}; 681 682union cvmx_pow_wq_int_thrx { 683 uint64_t u64; 684 struct cvmx_pow_wq_int_thrx_s { 685 uint64_t reserved_29_63:35; 686 uint64_t tc_en:1; 687 uint64_t tc_thr:4; 688 uint64_t reserved_23_23:1; 689 uint64_t ds_thr:11; 690 uint64_t reserved_11_11:1; 691 uint64_t iq_thr:11; 692 } s; 693 struct cvmx_pow_wq_int_thrx_cn30xx { 694 uint64_t reserved_29_63:35; 695 uint64_t tc_en:1; 696 uint64_t tc_thr:4; 697 uint64_t reserved_18_23:6; 698 uint64_t ds_thr:6; 699 uint64_t reserved_6_11:6; 700 uint64_t iq_thr:6; 701 } cn30xx; 702 struct cvmx_pow_wq_int_thrx_cn31xx { 703 uint64_t reserved_29_63:35; 704 uint64_t tc_en:1; 705 uint64_t tc_thr:4; 706 uint64_t reserved_20_23:4; 707 uint64_t ds_thr:8; 708 uint64_t reserved_8_11:4; 709 uint64_t iq_thr:8; 710 } cn31xx; 711 struct cvmx_pow_wq_int_thrx_s cn38xx; 712 struct cvmx_pow_wq_int_thrx_s cn38xxp2; 713 struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; 714 struct cvmx_pow_wq_int_thrx_cn52xx { 715 uint64_t reserved_29_63:35; 716 uint64_t tc_en:1; 717 uint64_t tc_thr:4; 718 uint64_t reserved_21_23:3; 719 uint64_t ds_thr:9; 720 uint64_t reserved_9_11:3; 721 uint64_t iq_thr:9; 722 } cn52xx; 723 struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; 724 struct cvmx_pow_wq_int_thrx_s cn56xx; 725 struct cvmx_pow_wq_int_thrx_s cn56xxp1; 726 struct cvmx_pow_wq_int_thrx_s cn58xx; 727 struct cvmx_pow_wq_int_thrx_s cn58xxp1; 728 struct cvmx_pow_wq_int_thrx_cn63xx { 729 uint64_t reserved_29_63:35; 730 uint64_t tc_en:1; 731 uint64_t tc_thr:4; 732 uint64_t reserved_22_23:2; 733 uint64_t ds_thr:10; 734 uint64_t reserved_10_11:2; 735 uint64_t iq_thr:10; 736 } cn63xx; 737 struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1; 738}; 739 740union cvmx_pow_ws_pcx { 741 uint64_t u64; 742 struct cvmx_pow_ws_pcx_s { 743 uint64_t reserved_32_63:32; 744 uint64_t ws_pc:32; 745 } s; 746 struct cvmx_pow_ws_pcx_s cn30xx; 747 struct cvmx_pow_ws_pcx_s cn31xx; 748 struct cvmx_pow_ws_pcx_s cn38xx; 749 struct cvmx_pow_ws_pcx_s cn38xxp2; 750 struct cvmx_pow_ws_pcx_s cn50xx; 751 struct cvmx_pow_ws_pcx_s cn52xx; 752 struct cvmx_pow_ws_pcx_s cn52xxp1; 753 struct cvmx_pow_ws_pcx_s cn56xx; 754 struct cvmx_pow_ws_pcx_s cn56xxp1; 755 struct cvmx_pow_ws_pcx_s cn58xx; 756 struct cvmx_pow_ws_pcx_s cn58xxp1; 757 struct cvmx_pow_ws_pcx_s cn63xx; 758 struct cvmx_pow_ws_pcx_s cn63xxp1; 759}; 760 761#endif 762