LXR linux/arch/powerpc/include/asm/pte-hash64.h

   1#ifndef _ASM_POWERPC_PTE_HASH64_H
   2#define _ASM_POWERPC_PTE_HASH64_H
   3#ifdef __KERNEL__
   4
   5/*
   6 * Common bits between 4K and 64K pages in a linux-style PTE.
   7 * These match the bits in the (hardware-defined) PowerPC PTE as closely
   8 * as possible. Additional bits may be defined in pgtable-hash64-*.h
   9 *
  10 * Note: We only support user read/write permissions. Supervisor always
  11 * have full read/write to pages above PAGE_OFFSET (pages below that
  12 * always use the user access permissions).
  13 *
  14 * We could create separate kernel read-only if we used the 3 PP bits
  15 * combinations that newer processors provide but we currently don't.
  16 */
  17#define _PAGE_PRESENT           0x0001 /* software: pte contains a translation */
  18#define _PAGE_USER              0x0002 /* matches one of the PP bits */
  19#define _PAGE_FILE              0x0002 /* (!present only) software: pte holds file offset */
  20#define _PAGE_EXEC              0x0004 /* No execute on POWER4 and newer (we invert) */
  21#define _PAGE_GUARDED           0x0008
  22#define _PAGE_COHERENT          0x0010 /* M: enforce memory coherence (SMP systems) */
  23#define _PAGE_NO_CACHE          0x0020 /* I: cache inhibit */
  24#define _PAGE_WRITETHRU         0x0040 /* W: cache write-through */
  25#define _PAGE_DIRTY             0x0080 /* C: page changed */
  26#define _PAGE_ACCESSED          0x0100 /* R: page referenced */
  27#define _PAGE_RW                0x0200 /* software: user write access allowed */
  28#define _PAGE_BUSY              0x0800 /* software: PTE & hash are busy */
  29
  30/* No separate kernel read-only */
  31#define _PAGE_KERNEL_RW         (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
  32#define _PAGE_KERNEL_RO          _PAGE_KERNEL_RW
  33
  34/* Strong Access Ordering */
  35#define _PAGE_SAO               (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
  36
  37/* No page size encoding in the linux PTE */
  38#define _PAGE_PSIZE             0
  39
  40/* PTEIDX nibble */
  41#define _PTEIDX_SECONDARY       0x8
  42#define _PTEIDX_GROUP_IX        0x7
  43
  44/* Hash table based platforms need atomic updates of the linux PTE */
  45#define PTE_ATOMIC_UPDATES      1
  46
  47#ifdef CONFIG_PPC_64K_PAGES
  48#include <asm/pte-hash64-64k.h>
  49#else
  50#include <asm/pte-hash64-4k.h>
  51#endif
  52
  53#endif /* __KERNEL__ */
  54#endif /*  _ASM_POWERPC_PTE_HASH64_H */
  55