1#ifndef _ASM_POWERPC_PTRACE_H 2#define _ASM_POWERPC_PTRACE_H 3 4/* 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This struct defines the way the registers are stored on the 8 * kernel stack during a system call or other kernel entry. 9 * 10 * this should only contain volatile regs 11 * since we can keep non-volatile in the thread_struct 12 * should set this up when only volatiles are saved 13 * by intr code. 14 * 15 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure 16 * that the overall structure is a multiple of 16 bytes in length. 17 * 18 * Note that the offsets of the fields in this struct correspond with 19 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License 23 * as published by the Free Software Foundation; either version 24 * 2 of the License, or (at your option) any later version. 25 */ 26 27#include <linux/types.h> 28 29#ifndef __ASSEMBLY__ 30 31struct pt_regs { 32 unsigned long gpr[32]; 33 unsigned long nip; 34 unsigned long msr; 35 unsigned long orig_gpr3; /* Used for restarting system calls */ 36 unsigned long ctr; 37 unsigned long link; 38 unsigned long xer; 39 unsigned long ccr; 40#ifdef __powerpc64__ 41 unsigned long softe; /* Soft enabled/disabled */ 42#else 43 unsigned long mq; /* 601 only (not used at present) */ 44 /* Used on APUS to hold IPL value. */ 45#endif 46 unsigned long trap; /* Reason for being here */ 47 /* N.B. for critical exceptions on 4xx, the dar and dsisr 48 fields are overloaded to hold srr0 and srr1. */ 49 unsigned long dar; /* Fault registers */ 50 unsigned long dsisr; /* on 4xx/Book-E used for ESR */ 51 unsigned long result; /* Result of a system call */ 52}; 53 54#endif /* __ASSEMBLY__ */ 55 56#ifdef __KERNEL__ 57 58#ifdef __powerpc64__ 59 60#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ 61#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ 62#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) 63#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \ 64 STACK_FRAME_OVERHEAD + 288) 65#define STACK_FRAME_MARKER 12 66 67/* Size of dummy stack frame allocated when calling signal handler. */ 68#define __SIGNAL_FRAMESIZE 128 69#define __SIGNAL_FRAMESIZE32 64 70 71#else /* __powerpc64__ */ 72 73#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ 74#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */ 75#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773) 76#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD) 77#define STACK_FRAME_MARKER 2 78 79/* Size of stack frame allocated when calling signal handler. */ 80#define __SIGNAL_FRAMESIZE 64 81 82#endif /* __powerpc64__ */ 83 84#ifndef __ASSEMBLY__ 85 86#define instruction_pointer(regs) ((regs)->nip) 87#define user_stack_pointer(regs) ((regs)->gpr[1]) 88#define kernel_stack_pointer(regs) ((regs)->gpr[1]) 89#define regs_return_value(regs) ((regs)->gpr[3]) 90 91#ifdef CONFIG_SMP 92extern unsigned long profile_pc(struct pt_regs *regs); 93#else 94#define profile_pc(regs) instruction_pointer(regs) 95#endif 96 97#ifdef __powerpc64__ 98#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) 99#else 100#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) 101#endif 102 103#define force_successful_syscall_return() \ 104 do { \ 105 set_thread_flag(TIF_NOERROR); \ 106 } while(0) 107 108struct task_struct; 109extern unsigned long ptrace_get_reg(struct task_struct *task, int regno); 110extern int ptrace_put_reg(struct task_struct *task, int regno, 111 unsigned long data); 112 113/* 114 * We use the least-significant bit of the trap field to indicate 115 * whether we have saved the full set of registers, or only a 116 * partial set. A 1 there means the partial set. 117 * On 4xx we use the next bit to indicate whether the exception 118 * is a critical exception (1 means it is). 119 */ 120#define FULL_REGS(regs) (((regs)->trap & 1) == 0) 121#ifndef __powerpc64__ 122#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) 123#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) 124#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0) 125#endif /* ! __powerpc64__ */ 126#define TRAP(regs) ((regs)->trap & ~0xF) 127#ifdef __powerpc64__ 128#define NV_REG_POISON 0xdeadbeefdeadbeefUL 129#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) 130#else 131#define NV_REG_POISON 0xdeadbeef 132#define CHECK_FULL_REGS(regs) \ 133do { \ 134 if ((regs)->trap & 1) \ 135 printk(KERN_CRIT "%s: partial register set\n", __func__); \ 136} while (0) 137#endif /* __powerpc64__ */ 138 139#define arch_has_single_step() (1) 140#define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601)) 141#define ARCH_HAS_USER_SINGLE_STEP_INFO 142 143/* 144 * kprobe-based event tracer support 145 */ 146 147#include <linux/stddef.h> 148#include <linux/thread_info.h> 149extern int regs_query_register_offset(const char *name); 150extern const char *regs_query_register_name(unsigned int offset); 151#define MAX_REG_OFFSET (offsetof(struct pt_regs, dsisr)) 152 153/** 154 * regs_get_register() - get register value from its offset 155 * @regs: pt_regs from which register value is gotten 156 * @offset: offset number of the register. 157 * 158 * regs_get_register returns the value of a register whose offset from @regs. 159 * The @offset is the offset of the register in struct pt_regs. 160 * If @offset is bigger than MAX_REG_OFFSET, this returns 0. 161 */ 162static inline unsigned long regs_get_register(struct pt_regs *regs, 163 unsigned int offset) 164{ 165 if (unlikely(offset > MAX_REG_OFFSET)) 166 return 0; 167 return *(unsigned long *)((unsigned long)regs + offset); 168} 169 170/** 171 * regs_within_kernel_stack() - check the address in the stack 172 * @regs: pt_regs which contains kernel stack pointer. 173 * @addr: address which is checked. 174 * 175 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 176 * If @addr is within the kernel stack, it returns true. If not, returns false. 177 */ 178 179static inline bool regs_within_kernel_stack(struct pt_regs *regs, 180 unsigned long addr) 181{ 182 return ((addr & ~(THREAD_SIZE - 1)) == 183 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); 184} 185 186/** 187 * regs_get_kernel_stack_nth() - get Nth entry of the stack 188 * @regs: pt_regs which contains kernel stack pointer. 189 * @n: stack entry number. 190 * 191 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 192 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 193 * this returns 0. 194 */ 195static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, 196 unsigned int n) 197{ 198 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 199 addr += n; 200 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 201 return *addr; 202 else 203 return 0; 204} 205 206#endif /* __ASSEMBLY__ */ 207 208#endif /* __KERNEL__ */ 209 210/* 211 * Offsets used by 'ptrace' system call interface. 212 * These can't be changed without breaking binary compatibility 213 * with MkLinux, etc. 214 */ 215#define PT_R0 0 216#define PT_R1 1 217#define PT_R2 2 218#define PT_R3 3 219#define PT_R4 4 220#define PT_R5 5 221#define PT_R6 6 222#define PT_R7 7 223#define PT_R8 8 224#define PT_R9 9 225#define PT_R10 10 226#define PT_R11 11 227#define PT_R12 12 228#define PT_R13 13 229#define PT_R14 14 230#define PT_R15 15 231#define PT_R16 16 232#define PT_R17 17 233#define PT_R18 18 234#define PT_R19 19 235#define PT_R20 20 236#define PT_R21 21 237#define PT_R22 22 238#define PT_R23 23 239#define PT_R24 24 240#define PT_R25 25 241#define PT_R26 26 242#define PT_R27 27 243#define PT_R28 28 244#define PT_R29 29 245#define PT_R30 30 246#define PT_R31 31 247 248#define PT_NIP 32 249#define PT_MSR 33 250#define PT_ORIG_R3 34 251#define PT_CTR 35 252#define PT_LNK 36 253#define PT_XER 37 254#define PT_CCR 38 255#ifndef __powerpc64__ 256#define PT_MQ 39 257#else 258#define PT_SOFTE 39 259#endif 260#define PT_TRAP 40 261#define PT_DAR 41 262#define PT_DSISR 42 263#define PT_RESULT 43 264#define PT_REGS_COUNT 44 265 266#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ 267 268#ifndef __powerpc64__ 269 270#define PT_FPR31 (PT_FPR0 + 2*31) 271#define PT_FPSCR (PT_FPR0 + 2*32 + 1) 272 273#else /* __powerpc64__ */ 274 275#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ 276 277#ifdef __KERNEL__ 278#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */ 279#endif 280 281#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ 282#define PT_VSCR (PT_VR0 + 32*2 + 1) 283#define PT_VRSAVE (PT_VR0 + 33*2) 284 285#ifdef __KERNEL__ 286#define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */ 287#define PT_VSCR_32 (PT_VR0 + 32*4 + 3) 288#define PT_VRSAVE_32 (PT_VR0 + 33*4) 289#endif 290 291/* 292 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 293 */ 294#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ 295#define PT_VSR31 (PT_VSR0 + 2*31) 296#ifdef __KERNEL__ 297#define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */ 298#endif 299#endif /* __powerpc64__ */ 300 301/* 302 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 303 * The transfer totals 34 quadword. Quadwords 0-31 contain the 304 * corresponding vector registers. Quadword 32 contains the vscr as the 305 * last word (offset 12) within that quadword. Quadword 33 contains the 306 * vrsave as the first word (offset 0) within the quadword. 307 * 308 * This definition of the VMX state is compatible with the current PPC32 309 * ptrace interface. This allows signal handling and ptrace to use the same 310 * structures. This also simplifies the implementation of a bi-arch 311 * (combined (32- and 64-bit) gdb. 312 */ 313#define PTRACE_GETVRREGS 18 314#define PTRACE_SETVRREGS 19 315 316/* Get/set all the upper 32-bits of the SPE registers, accumulator, and 317 * spefscr, in one go */ 318#define PTRACE_GETEVRREGS 20 319#define PTRACE_SETEVRREGS 21 320 321/* Get the first 32 128bit VSX registers */ 322#define PTRACE_GETVSRREGS 27 323#define PTRACE_SETVSRREGS 28 324 325/* 326 * Get or set a debug register. The first 16 are DABR registers and the 327 * second 16 are IABR registers. 328 */ 329#define PTRACE_GET_DEBUGREG 25 330#define PTRACE_SET_DEBUGREG 26 331 332/* (new) PTRACE requests using the same numbers as x86 and the same 333 * argument ordering. Additionally, they support more registers too 334 */ 335#define PTRACE_GETREGS 12 336#define PTRACE_SETREGS 13 337#define PTRACE_GETFPREGS 14 338#define PTRACE_SETFPREGS 15 339#define PTRACE_GETREGS64 22 340#define PTRACE_SETREGS64 23 341 342/* (old) PTRACE requests with inverted arguments */ 343#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */ 344#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */ 345#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */ 346#define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */ 347 348/* Calls to trace a 64bit program from a 32bit program */ 349#define PPC_PTRACE_PEEKTEXT_3264 0x95 350#define PPC_PTRACE_PEEKDATA_3264 0x94 351#define PPC_PTRACE_POKETEXT_3264 0x93 352#define PPC_PTRACE_POKEDATA_3264 0x92 353#define PPC_PTRACE_PEEKUSR_3264 0x91 354#define PPC_PTRACE_POKEUSR_3264 0x90 355 356#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 357 358#define PPC_PTRACE_GETHWDBGINFO 0x89 359#define PPC_PTRACE_SETHWDEBUG 0x88 360#define PPC_PTRACE_DELHWDEBUG 0x87 361 362#ifndef __ASSEMBLY__ 363 364struct ppc_debug_info { 365 __u32 version; /* Only version 1 exists to date */ 366 __u32 num_instruction_bps; 367 __u32 num_data_bps; 368 __u32 num_condition_regs; 369 __u32 data_bp_alignment; 370 __u32 sizeof_condition; /* size of the DVC register */ 371 __u64 features; 372}; 373 374#endif /* __ASSEMBLY__ */ 375 376/* 377 * features will have bits indication whether there is support for: 378 */ 379#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001 380#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002 381#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004 382#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008 383 384#ifndef __ASSEMBLY__ 385 386struct ppc_hw_breakpoint { 387 __u32 version; /* currently, version must be 1 */ 388 __u32 trigger_type; /* only some combinations allowed */ 389 __u32 addr_mode; /* address match mode */ 390 __u32 condition_mode; /* break/watchpoint condition flags */ 391 __u64 addr; /* break/watchpoint address */ 392 __u64 addr2; /* range end or mask */ 393 __u64 condition_value; /* contents of the DVC register */ 394}; 395 396#endif /* __ASSEMBLY__ */ 397 398/* 399 * Trigger Type 400 */ 401#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001 402#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002 403#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004 404#define PPC_BREAKPOINT_TRIGGER_RW \ 405 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE) 406 407/* 408 * Address Mode 409 */ 410#define PPC_BREAKPOINT_MODE_EXACT 0x00000000 411#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001 412#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002 413#define PPC_BREAKPOINT_MODE_MASK 0x00000003 414 415/* 416 * Condition Mode 417 */ 418#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003 419#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000 420#define PPC_BREAKPOINT_CONDITION_AND 0x00000001 421#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND 422#define PPC_BREAKPOINT_CONDITION_OR 0x00000002 423#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003 424#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 425#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 426#define PPC_BREAKPOINT_CONDITION_BE(n) \ 427 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) 428 429#endif /* _ASM_POWERPC_PTRACE_H */ 430