1#ifndef __ASM_SH_HITACHI_SE7343_H
2#define __ASM_SH_HITACHI_SE7343_H
3
4
5
6
7
8
9
10
11
12
13
14
15#define PA_ROM 0x00000000
16#define PA_ROM_SIZE 0x00400000
17#define PA_FROM 0x00400000
18#define PA_FROM_SIZE 0x00400000
19#define PA_SRAM 0x00800000
20#define PA_FROM_SIZE 0x00400000
21
22#define PA_EXT1 0x04000000
23#define PA_EXT1_SIZE 0x04000000
24
25#define PA_EXT2 0x08000000
26#define PA_EXT2_SIZE 0x04000000
27
28#define PA_SDRAM 0x0c000000
29#define PA_SDRAM_SIZE 0x04000000
30
31#define PA_PCIC 0x10000000
32#define PA_MRSHPC 0xb03fffe0
33#define PA_MRSHPC_MW1 0xb0400000
34#define PA_MRSHPC_MW2 0xb0500000
35#define PA_MRSHPC_IO 0xb0600000
36#define MRSHPC_OPTION (PA_MRSHPC + 6)
37#define MRSHPC_CSR (PA_MRSHPC + 8)
38#define MRSHPC_ISR (PA_MRSHPC + 10)
39#define MRSHPC_ICR (PA_MRSHPC + 12)
40#define MRSHPC_CPWCR (PA_MRSHPC + 14)
41#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47#define MRSHPC_CDCR (PA_MRSHPC + 28)
48#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49#define PA_LED 0xb0C00000
50#define LED_SHIFT 0
51#define PA_DIPSW 0xb0900000
52#define PA_CPLD_MODESET 0xb1400004
53#define PA_CPLD_ST 0xb1400008
54#define PA_CPLD_IMSK 0xb140000a
55
56#define PA_EXT5 0x14000000
57#define PA_EXT5_SIZE 0x04000000
58
59#define PA_LCD1 0xb8000000
60#define PA_LCD2 0xb8800000
61
62#define PORT_PACR 0xA4050100
63#define PORT_PBCR 0xA4050102
64#define PORT_PCCR 0xA4050104
65#define PORT_PDCR 0xA4050106
66#define PORT_PECR 0xA4050108
67#define PORT_PFCR 0xA405010A
68#define PORT_PGCR 0xA405010C
69#define PORT_PHCR 0xA405010E
70#define PORT_PJCR 0xA4050110
71#define PORT_PKCR 0xA4050112
72#define PORT_PLCR 0xA4050114
73#define PORT_PMCR 0xA4050116
74#define PORT_PNCR 0xA4050118
75#define PORT_PQCR 0xA405011A
76#define PORT_PRCR 0xA405011C
77#define PORT_PSCR 0xA405011E
78#define PORT_PTCR 0xA4050140
79#define PORT_PUCR 0xA4050142
80#define PORT_PVCR 0xA4050144
81#define PORT_PWCR 0xA4050146
82#define PORT_PYCR 0xA4050148
83#define PORT_PZCR 0xA405014A
84
85#define PORT_PSELA 0xA405014C
86#define PORT_PSELB 0xA405014E
87#define PORT_PSELC 0xA4050150
88#define PORT_PSELD 0xA4050152
89#define PORT_PSELE 0xA4050154
90
91#define PORT_HIZCRA 0xA4050156
92#define PORT_HIZCRB 0xA4050158
93#define PORT_HIZCRC 0xA405015C
94
95#define PORT_DRVCR 0xA4050180
96
97#define PORT_PADR 0xA4050120
98#define PORT_PBDR 0xA4050122
99#define PORT_PCDR 0xA4050124
100#define PORT_PDDR 0xA4050126
101#define PORT_PEDR 0xA4050128
102#define PORT_PFDR 0xA405012A
103#define PORT_PGDR 0xA405012C
104#define PORT_PHDR 0xA405012E
105#define PORT_PJDR 0xA4050130
106#define PORT_PKDR 0xA4050132
107#define PORT_PLDR 0xA4050134
108#define PORT_PMDR 0xA4050136
109#define PORT_PNDR 0xA4050138
110#define PORT_PQDR 0xA405013A
111#define PORT_PRDR 0xA405013C
112#define PORT_PTDR 0xA4050160
113#define PORT_PUDR 0xA4050162
114#define PORT_PVDR 0xA4050164
115#define PORT_PWDR 0xA4050166
116#define PORT_PYDR 0xA4050168
117
118#define FPGA_IN 0xb1400000
119#define FPGA_OUT 0xb1400002
120
121#define IRQ0_IRQ 32
122#define IRQ1_IRQ 33
123#define IRQ4_IRQ 36
124#define IRQ5_IRQ 37
125
126#define SE7343_FPGA_IRQ_MRSHPC0 0
127#define SE7343_FPGA_IRQ_MRSHPC1 1
128#define SE7343_FPGA_IRQ_MRSHPC2 2
129#define SE7343_FPGA_IRQ_MRSHPC3 3
130#define SE7343_FPGA_IRQ_SMC 6
131#define SE7343_FPGA_IRQ_USB 8
132#define SE7343_FPGA_IRQ_UARTA 10
133#define SE7343_FPGA_IRQ_UARTB 11
134
135#define SE7343_FPGA_IRQ_NR 12
136
137
138extern unsigned int se7343_fpga_irq[];
139
140void init_7343se_IRQ(void);
141
142#endif
143