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11#ifndef _ASM_X86_UV_UV_BAU_H
12#define _ASM_X86_UV_UV_BAU_H
13
14#include <linux/bitmap.h>
15#define BITSPERBYTE 8
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36#define MAX_CPUS_PER_UVHUB 64
37#define MAX_CPUS_PER_SOCKET 32
38#define ADP_SZ 64
39#define UV_CPUS_PER_AS 32
40#define ITEMS_PER_DESC 8
41
42#define MAX_BAU_CONCURRENT 3
43#define UV_ACT_STATUS_MASK 0x3
44#define UV_ACT_STATUS_SIZE 2
45#define UV_DISTRIBUTION_SIZE 256
46#define UV_SW_ACK_NPENDING 8
47#define UV1_NET_ENDPOINT_INTD 0x38
48#define UV2_NET_ENDPOINT_INTD 0x28
49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51#define UV_DESC_PSHIFT 49
52#define UV_PAYLOADQ_PNODE_SHIFT 49
53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55#define UV_BAU_TUNABLES_DIR "sgi_uv"
56#define UV_BAU_TUNABLES_FILE "bau_tunables"
57#define WHITESPACE " \t\n"
58#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
59#define cpubit_isset(cpu, bau_local_cpumask) \
60 test_bit((cpu), (bau_local_cpumask).bits)
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68
69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
71
72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
74 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
75
76#define BAU_MISC_CONTROL_MULT_MASK 3
77
78#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
79
80#define BAU_URGENCY_7_SHIFT 28
81#define BAU_URGENCY_7_MASK 7
82
83#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
84
85#define BAU_TRANS_SHIFT 40
86#define BAU_TRANS_MASK 0x3f
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90
91#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
92#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
93#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
94#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
95#define write_gmmr uv_write_global_mmr64
96#define write_lmmr uv_write_local_mmr
97#define read_lmmr uv_read_local_mmr
98#define read_gmmr uv_read_global_mmr64
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102
103#define DS_IDLE 0
104#define DS_ACTIVE 1
105#define DS_DESTINATION_TIMEOUT 2
106#define DS_SOURCE_TIMEOUT 3
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119#define UV2H_DESC_IDLE 0
120#define UV2H_DESC_BUSY 2
121#define UV2H_DESC_DEST_TIMEOUT 4
122#define UV2H_DESC_DEST_STRONG_NACK 5
123#define UV2H_DESC_SOURCE_TIMEOUT 6
124#define UV2H_DESC_DEST_PUT_ERR 7
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129#define PLUGGED_DELAY 10
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135#define PLUGSB4RESET 100
136
137#define TIMEOUTSB4RESET 1
138
139#define IPI_RESET_LIMIT 1
140
141#define COMPLETE_THRESHOLD 5
142
143#define UV_LB_SUBNODEID 0x10
144
145
146#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
147#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
148
149#define UV2_ACK_MASK 0x7UL
150#define UV2_ACK_UNITS_SHFT 3
151#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
152#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
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156
157#define DEST_Q_SIZE 20
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161#define DEST_NUM_RESOURCES 8
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165#define FLUSH_RETRY_PLUGGED 1
166#define FLUSH_RETRY_TIMEOUT 2
167#define FLUSH_GIVEUP 3
168#define FLUSH_COMPLETE 4
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173#define CONGESTED_RESPONSE_US 1000
174
175#define CONGESTED_REPS 10
176
177#define CONGESTED_PERIOD 30
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180#define MSG_NOOP 0
181#define MSG_REGULAR 1
182#define MSG_RETRY 2
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193
194struct pnmask {
195 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
196};
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203struct bau_local_cpumask {
204 unsigned long bits;
205};
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224struct bau_msg_payload {
225 unsigned long address;
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228 unsigned short sending_cpu;
229
230 unsigned short acknowledge_count;
231
232 unsigned int reserved1:32;
233};
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240struct bau_msg_header {
241 unsigned int dest_subnodeid:6;
242
243 unsigned int base_dest_nasid:15;
244
245 unsigned int command:8;
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248 unsigned int rsvd_1:3;
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251 unsigned int rsvd_2:9;
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254 unsigned int sequence:16;
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261 unsigned int rsvd_3:1;
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266 unsigned int replied_to:1;
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269 unsigned int msg_type:3;
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272 unsigned int canceled:1;
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275 unsigned int payload_1a:1;
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277 unsigned int payload_1b:2;
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281 unsigned int payload_1ca:6;
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283 unsigned int payload_1c:2;
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287 unsigned int payload_1d:6;
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289 unsigned int payload_1e:2;
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292 unsigned int rsvd_4:7;
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294 unsigned int swack_flag:1;
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299 unsigned int rsvd_5:6;
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301 unsigned int rsvd_6:5;
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303 unsigned int int_both:1;
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306 unsigned int fairness:3;
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308 unsigned int multilevel:1;
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312 unsigned int chaining:1;
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315 unsigned int rsvd_7:21;
316
317};
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324struct bau_desc {
325 struct pnmask distribution;
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329 struct bau_msg_header header;
330 struct bau_msg_payload payload;
331};
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354struct bau_pq_entry {
355 unsigned long address;
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358 unsigned short sending_cpu;
359
360 unsigned short acknowledge_count;
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362
363 unsigned short replied_to:1;
364 unsigned short msg_type:3;
365 unsigned short canceled:1;
366 unsigned short unused1:3;
367
368 unsigned char unused2a;
369
370 unsigned char unused2;
371
372 unsigned char swack_vec;
373
374 unsigned short sequence;
375
376 unsigned char unused4[2];
377
378 int number_of_cpus;
379
380 unsigned char unused5[8];
381
382};
383
384struct msg_desc {
385 struct bau_pq_entry *msg;
386 int msg_slot;
387 int swack_slot;
388 struct bau_pq_entry *queue_first;
389 struct bau_pq_entry *queue_last;
390};
391
392struct reset_args {
393 int sender;
394};
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399struct ptc_stats {
400
401 unsigned long s_giveup;
402
403 unsigned long s_requestor;
404
405 unsigned long s_stimeout;
406 unsigned long s_dtimeout;
407 unsigned long s_time;
408 unsigned long s_retriesok;
409 unsigned long s_ntargcpu;
410
411 unsigned long s_ntargself;
412
413 unsigned long s_ntarglocals;
414
415 unsigned long s_ntargremotes;
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417 unsigned long s_ntarglocaluvhub;
418 unsigned long s_ntargremoteuvhub;
419 unsigned long s_ntarguvhub;
420
421 unsigned long s_ntarguvhub16;
422
423 unsigned long s_ntarguvhub8;
424
425 unsigned long s_ntarguvhub4;
426
427 unsigned long s_ntarguvhub2;
428
429 unsigned long s_ntarguvhub1;
430
431 unsigned long s_resets_plug;
432
433 unsigned long s_resets_timeout;
434
435 unsigned long s_busy;
436
437 unsigned long s_throttles;
438 unsigned long s_retry_messages;
439 unsigned long s_bau_reenabled;
440 unsigned long s_bau_disabled;
441
442 unsigned long d_alltlb;
443
444 unsigned long d_onetlb;
445
446 unsigned long d_multmsg;
447
448 unsigned long d_nomsg;
449 unsigned long d_time;
450
451 unsigned long d_requestee;
452
453 unsigned long d_retries;
454
455 unsigned long d_canceled;
456
457 unsigned long d_nocanceled;
458
459 unsigned long d_resets;
460
461 unsigned long d_rcanceled;
462
463};
464
465struct tunables {
466 int *tunp;
467 int deflt;
468};
469
470struct hub_and_pnode {
471 short uvhub;
472 short pnode;
473};
474
475struct socket_desc {
476 short num_cpus;
477 short cpu_number[MAX_CPUS_PER_SOCKET];
478};
479
480struct uvhub_desc {
481 unsigned short socket_mask;
482 short num_cpus;
483 short uvhub;
484 short pnode;
485 struct socket_desc socket[2];
486};
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491struct bau_control {
492 struct bau_desc *descriptor_base;
493 struct bau_pq_entry *queue_first;
494 struct bau_pq_entry *queue_last;
495 struct bau_pq_entry *bau_msg_head;
496 struct bau_control *uvhub_master;
497 struct bau_control *socket_master;
498 struct ptc_stats *statp;
499 cpumask_t *cpumask;
500 unsigned long timeout_interval;
501 unsigned long set_bau_on_time;
502 atomic_t active_descriptor_count;
503 int plugged_tries;
504 int timeout_tries;
505 int ipi_attempts;
506 int conseccompletes;
507 int baudisabled;
508 int set_bau_off;
509 short cpu;
510 short osnode;
511 short uvhub_cpu;
512 short uvhub;
513 short cpus_in_socket;
514 short cpus_in_uvhub;
515 short partition_base_pnode;
516 unsigned short message_number;
517 unsigned short uvhub_quiesce;
518 short socket_acknowledge_count[DEST_Q_SIZE];
519 cycles_t send_message;
520 spinlock_t uvhub_lock;
521 spinlock_t queue_lock;
522
523 int max_concurr;
524 int max_concurr_const;
525 int plugged_delay;
526 int plugsb4reset;
527 int timeoutsb4reset;
528 int ipi_reset_limit;
529 int complete_threshold;
530 int cong_response_us;
531 int cong_reps;
532 int cong_period;
533 cycles_t period_time;
534 long period_requests;
535 struct hub_and_pnode *thp;
536};
537
538static inline unsigned long read_mmr_uv2_status(void)
539{
540 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
541}
542
543static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
544{
545 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
546}
547
548static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
549{
550 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
551}
552
553static inline void write_mmr_activation(unsigned long index)
554{
555 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
556}
557
558static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
559{
560 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
561}
562
563static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
564{
565 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
566}
567
568static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
569{
570 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
571}
572
573static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
574{
575 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
576}
577
578static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
579{
580 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
581}
582
583static inline unsigned long read_mmr_misc_control(int pnode)
584{
585 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
586}
587
588static inline void write_mmr_sw_ack(unsigned long mr)
589{
590 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
591}
592
593static inline unsigned long read_mmr_sw_ack(void)
594{
595 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
596}
597
598static inline unsigned long read_gmmr_sw_ack(int pnode)
599{
600 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
601}
602
603static inline void write_mmr_data_config(int pnode, unsigned long mr)
604{
605 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
606}
607
608static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
609{
610 return constant_test_bit(uvhub, &dstp->bits[0]);
611}
612static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
613{
614 __set_bit(pnode, &dstp->bits[0]);
615}
616static inline void bau_uvhubs_clear(struct pnmask *dstp,
617 int nbits)
618{
619 bitmap_zero(&dstp->bits[0], nbits);
620}
621static inline int bau_uvhub_weight(struct pnmask *dstp)
622{
623 return bitmap_weight((unsigned long *)&dstp->bits[0],
624 UV_DISTRIBUTION_SIZE);
625}
626
627static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
628{
629 bitmap_zero(&dstp->bits, nbits);
630}
631
632extern void uv_bau_message_intr1(void);
633extern void uv_bau_timeout_intr1(void);
634
635struct atomic_short {
636 short counter;
637};
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645static inline int atomic_read_short(const struct atomic_short *v)
646{
647 return v->counter;
648}
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657static inline int atom_asr(short i, struct atomic_short *v)
658{
659 short __i = i;
660 asm volatile(LOCK_PREFIX "xaddw %0, %1"
661 : "+r" (i), "+m" (v->counter)
662 : : "memory");
663 return i + __i;
664}
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676static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
677{
678 spin_lock(lock);
679 if (atomic_read(v) >= u) {
680 spin_unlock(lock);
681 return 0;
682 }
683 atomic_inc(v);
684 spin_unlock(lock);
685 return 1;
686}
687
688#endif
689