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43#ifndef IPHASE_H
44#define IPHASE_H
45
46
47
48
49#define IF_IADBG_INIT_ADAPTER 0x00000001
50#define IF_IADBG_TX 0x00000002
51#define IF_IADBG_RX 0x00000004
52#define IF_IADBG_QUERY_INFO 0x00000008
53#define IF_IADBG_SHUTDOWN 0x00000010
54#define IF_IADBG_INTR 0x00000020
55#define IF_IADBG_TXPKT 0x00000040
56#define IF_IADBG_RXPKT 0x00000080
57#define IF_IADBG_ERR 0x00000100
58#define IF_IADBG_EVENT 0x00000200
59#define IF_IADBG_DIS_INTR 0x00001000
60#define IF_IADBG_EN_INTR 0x00002000
61#define IF_IADBG_LOUD 0x00004000
62#define IF_IADBG_VERY_LOUD 0x00008000
63#define IF_IADBG_CBR 0x00100000
64#define IF_IADBG_UBR 0x00200000
65#define IF_IADBG_ABR 0x00400000
66#define IF_IADBG_DESC 0x01000000
67#define IF_IADBG_SUNI_STAT 0x02000000
68#define IF_IADBG_RESET 0x04000000
69
70#define IF_IADBG(f) if (IADebugFlag & (f))
71
72#ifdef CONFIG_ATM_IA_DEBUG
73
74#define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
75#define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
76#define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
77
78#define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
79#define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
80#define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
81#define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
82#define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
83
84#define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
85#define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
86#define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
87
88#define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
89#define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
90#define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
91#define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
92
93#define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
94#define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
95#define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
96#define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
97#define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
98
99#else
100#define IF_LOUD(A)
101#define IF_VERY_LOUD(A)
102#define IF_INIT_ADAPTER(A)
103#define IF_INIT(A)
104#define IF_SUNI_STAT(A)
105#define IF_PVC_CHKPKT(A)
106#define IF_QUERY_INFO(A)
107#define IF_COPY_OVER(A)
108#define IF_HANG(A)
109#define IF_INTR(A)
110#define IF_DIS_INTR(A)
111#define IF_EN_INTR(A)
112#define IF_TX(A)
113#define IF_RX(A)
114#define IF_TXDEBUG(A)
115#define IF_VC(A)
116#define IF_ERR(A)
117#define IF_CBR(A)
118#define IF_UBR(A)
119#define IF_ABR(A)
120#define IF_SHUTDOWN(A)
121#define DbgPrint(A)
122#define IF_EVENT(A)
123#define IF_TXPKT(A)
124#define IF_RXPKT(A)
125#endif
126
127#define isprint(a) ((a >=' ')&&(a <= '~'))
128#define ATM_DESC(skb) (skb->protocol)
129#define IA_SKB_STATE(skb) (skb->protocol)
130#define IA_DLED 1
131#define IA_TX_DONE 2
132
133
134#define IA_CMD 0x7749
135typedef struct {
136 int cmd;
137 int sub_cmd;
138 int len;
139 u32 maddr;
140 int status;
141 void __user *buf;
142} IA_CMDBUF, *PIA_CMDBUF;
143
144
145#define MEMDUMP 0x01
146
147
148#define MEMDUMP_SEGREG 0x2
149#define MEMDUMP_DEV 0x1
150#define MEMDUMP_REASSREG 0x3
151#define MEMDUMP_FFL 0x4
152#define READ_REG 0x5
153#define WAKE_DBG_WAIT 0x6
154
155
156
157#define Boolean(x) ((x) ? 1 : 0)
158#define NR_VCI 1024
159#define NR_VCI_LD 10
160#define NR_VCI_4K 4096
161#define NR_VCI_4K_LD 12
162#define MEM_VALID 0xfffffff0
163
164#ifndef PCI_VENDOR_ID_IPHASE
165#define PCI_VENDOR_ID_IPHASE 0x107e
166#endif
167#ifndef PCI_DEVICE_ID_IPHASE_5575
168#define PCI_DEVICE_ID_IPHASE_5575 0x0008
169#endif
170#define DEV_LABEL "ia"
171#define PCR 207692
172#define ICR 100000
173#define MCR 0
174#define TBE 1000
175#define FRTT 1
176#define RIF 2
177#define RDF 4
178#define NRMCODE 5
179#define TRMCODE 3
180#define CDFCODE 6
181#define ATDFCODE 2
182
183
184#define TX_PACKET_RAM 0x00000
185#define DFL_TX_BUF_SZ 10240
186#define DFL_TX_BUFFERS 50
187
188#define REASS_RAM_SIZE 0x10000
189#define RX_PACKET_RAM 0x80000
190#define DFL_RX_BUF_SZ 10240
191#define DFL_RX_BUFFERS 50
192
193
194struct cpcs_trailer
195{
196 u_short control;
197 u_short length;
198 u_int crc32;
199};
200
201struct cpcs_trailer_desc
202{
203 struct cpcs_trailer *cpcs;
204 dma_addr_t dma_addr;
205};
206
207struct ia_vcc
208{
209 int rxing;
210 int txing;
211 int NumCbrEntry;
212 u32 pcr;
213 u32 saved_tx_quota;
214 int flow_inc;
215 struct sk_buff_head txing_skb;
216 int ltimeout;
217 u8 vc_desc_cnt;
218
219};
220
221struct abr_vc_table
222{
223 u_char status;
224 u_char rdf;
225 u_short air;
226 u_int res[3];
227 u_int req_rm_cell_data1;
228 u_int req_rm_cell_data2;
229 u_int add_rm_cell_data1;
230 u_int add_rm_cell_data2;
231};
232
233
234struct main_vc
235{
236 u_short type;
237#define ABR 0x8000
238#define UBR 0xc000
239#define CBR 0x0000
240
241 u_short nrm;
242 u_short trm;
243 u_short rm_timestamp_hi;
244 u_short rm_timestamp_lo:8,
245 crm:8;
246 u_short remainder;
247 u_short next_vc_sched;
248 u_short present_desc;
249 u_short last_cell_slot;
250 u_short pcr;
251 u_short fraction;
252 u_short icr;
253 u_short atdf;
254 u_short mcr;
255 u_short acr;
256 u_short unack:8,
257 status:8;
258#define UIOLI 0x80
259#define CRC_APPEND 0x40
260#define ABR_STATE 0x02
261
262};
263
264
265
266struct ext_vc
267{
268 u_short atm_hdr1;
269 u_short atm_hdr2;
270 u_short last_desc;
271 u_short out_of_rate_link;
272};
273
274
275#define DLE_ENTRIES 256
276#define DMA_INT_ENABLE 0x0002
277#define TX_DLE_PSI 0x0001
278#define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
279
280
281struct dle
282{
283 u32 sys_pkt_addr;
284 u32 local_pkt_addr;
285 u32 bytes;
286 u16 prq_wr_ptr_data;
287 u16 mode;
288};
289
290struct dle_q
291{
292 struct dle *start;
293 struct dle *end;
294 struct dle *read;
295 struct dle *write;
296};
297
298struct free_desc_q
299{
300 int desc;
301 struct free_desc_q *next;
302};
303
304struct tx_buf_desc {
305 unsigned short desc_mode;
306 unsigned short vc_index;
307 unsigned short res1;
308 unsigned short bytes;
309 unsigned short buf_start_hi;
310 unsigned short buf_start_lo;
311 unsigned short res2[10];
312};
313
314
315struct rx_buf_desc {
316 unsigned short desc_mode;
317 unsigned short vc_index;
318 unsigned short vpi;
319 unsigned short bytes;
320 unsigned short buf_start_hi;
321 unsigned short buf_start_lo;
322 unsigned short dma_start_hi;
323 unsigned short dma_start_lo;
324 unsigned short crc_upper;
325 unsigned short crc_lower;
326 unsigned short res:8, timeout:8;
327 unsigned short res2[5];
328};
329
330
331
332#define EPROM_SIZE 0x40000
333#define MAC1_LEN 4
334#define MAC2_LEN 2
335
336
337#define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
338#define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000
339#define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
340#define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
341#define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
342#define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE
343#define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
344#define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
345
346
347#define IPHASE5575_BUS_CONTROL_REG 0x00
348#define IPHASE5575_BUS_STATUS_REG 0x01
349#define IPHASE5575_MAC1 0x02
350#define IPHASE5575_REV 0x03
351#define IPHASE5575_MAC2 0x03
352#define IPHASE5575_EXT_RESET 0x04
353#define IPHASE5575_INT_RESET 0x05
354#define IPHASE5575_PCI_ADDR_PAGE 0x07
355#define IPHASE5575_EEPROM_ACCESS 0x0a
356#define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
357#define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
358#define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
359#define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
360#define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f
361
362
363#define CTRL_FE_RST 0x80000000
364#define CTRL_LED 0x40000000
365#define CTRL_25MBPHY 0x10000000
366#define CTRL_ENCMBMEM 0x08000000
367#define CTRL_ENOFFSEG 0x01000000
368#define CTRL_ERRMASK 0x00400000
369#define CTRL_DLETMASK 0x00100000
370#define CTRL_DLERMASK 0x00080000
371#define CTRL_FEMASK 0x00040000
372#define CTRL_SEGMASK 0x00020000
373#define CTRL_REASSMASK 0x00010000
374#define CTRL_CSPREEMPT 0x00002000
375#define CTRL_B128 0x00000200
376#define CTRL_B64 0x00000100
377#define CTRL_B48 0x00000080
378#define CTRL_B32 0x00000040
379#define CTRL_B16 0x00000020
380#define CTRL_B8 0x00000010
381
382
383#define STAT_CMEMSIZ 0xc0000000
384#define STAT_ADPARCK 0x20000000
385#define STAT_RESVD 0x1fffff80
386#define STAT_ERRINT 0x00000040
387#define STAT_MARKINT 0x00000020
388#define STAT_DLETINT 0x00000010
389#define STAT_DLERINT 0x00000008
390#define STAT_FEINT 0x00000004
391#define STAT_SEGINT 0x00000002
392#define STAT_REASSINT 0x00000001
393
394
395
396
397
398#define IDLEHEADHI 0x00
399#define IDLEHEADLO 0x01
400#define MAXRATE 0x02
401
402#define RATE155 0x64b1
403#define MAX_ATM_155 352768
404#define RATE25 0x5f9d
405
406#define STPARMS 0x03
407#define STPARMS_1K 0x008c
408#define STPARMS_2K 0x0049
409#define STPARMS_4K 0x0026
410#define COMP_EN 0x4000
411#define CBR_EN 0x2000
412#define ABR_EN 0x0800
413#define UBR_EN 0x0400
414
415#define ABRUBR_ARB 0x04
416#define RM_TYPE 0x05
417
418#define RM_TYPE_4_0 0x0100
419
420#define SEG_COMMAND_REG 0x17
421
422#define RESET_SEG 0x0055
423#define RESET_SEG_STATE 0x00aa
424#define RESET_TX_CELL_CTR 0x00cc
425
426#define CBR_PTR_BASE 0x20
427#define ABR_SBPTR_BASE 0x22
428#define UBR_SBPTR_BASE 0x23
429#define ABRWQ_BASE 0x26
430#define UBRWQ_BASE 0x27
431#define VCT_BASE 0x28
432#define VCTE_BASE 0x29
433#define CBR_TAB_BEG 0x2c
434#define CBR_TAB_END 0x2d
435#define PRQ_ST_ADR 0x30
436#define PRQ_ED_ADR 0x31
437#define PRQ_RD_PTR 0x32
438#define PRQ_WR_PTR 0x33
439#define TCQ_ST_ADR 0x34
440#define TCQ_ED_ADR 0x35
441#define TCQ_RD_PTR 0x36
442#define TCQ_WR_PTR 0x37
443#define SEG_QUEUE_BASE 0x40
444#define SEG_DESC_BASE 0x41
445#define MODE_REG_0 0x45
446#define T_ONLINE 0x0002
447
448#define MODE_REG_1 0x46
449#define MODE_REG_1_VAL 0x0400
450
451#define SEG_INTR_STATUS_REG 0x47
452#define SEG_MASK_REG 0x48
453#define TRANSMIT_DONE 0x0200
454#define TCQ_NOT_EMPTY 0x1000
455
456
457#define CELL_CTR_HIGH_AUTO 0x49
458#define CELL_CTR_HIGH_NOAUTO 0xc9
459#define CELL_CTR_LO_AUTO 0x4a
460#define CELL_CTR_LO_NOAUTO 0xca
461
462
463#define NEXTDESC 0x59
464#define NEXTVC 0x5a
465#define PSLOTCNT 0x5d
466#define NEWDN 0x6a
467#define NEWVC 0x6b
468#define SBPTR 0x6c
469#define ABRWQ_WRPTR 0x6f
470#define ABRWQ_RDPTR 0x70
471#define UBRWQ_WRPTR 0x71
472#define UBRWQ_RDPTR 0x72
473#define CBR_VC 0x73
474#define ABR_SBVC 0x75
475#define UBR_SBVC 0x76
476#define ABRNEXTLINK 0x78
477#define UBRNEXTLINK 0x79
478
479
480
481
482
483#define MODE_REG 0x00
484#define R_ONLINE 0x0002
485#define IGN_RAW_FL 0x0004
486
487#define PROTOCOL_ID 0x01
488#define REASS_MASK_REG 0x02
489#define REASS_INTR_STATUS_REG 0x03
490
491#define RX_PKT_CTR_OF 0x8000
492#define RX_ERR_CTR_OF 0x4000
493#define RX_CELL_CTR_OF 0x1000
494#define RX_FREEQ_EMPT 0x0200
495#define RX_EXCPQ_FL 0x0080
496#define RX_RAWQ_FL 0x0010
497#define RX_EXCP_RCVD 0x0008
498#define RX_PKT_RCVD 0x0004
499#define RX_RAW_RCVD 0x0001
500
501#define DRP_PKT_CNTR 0x04
502#define ERR_CNTR 0x05
503#define RAW_BASE_ADR 0x08
504#define CELL_CTR0 0x0c
505#define CELL_CTR1 0x0d
506#define REASS_COMMAND_REG 0x0f
507
508#define RESET_REASS 0x0055
509#define RESET_REASS_STATE 0x00aa
510#define RESET_DRP_PKT_CNTR 0x00f1
511#define RESET_ERR_CNTR 0x00f2
512#define RESET_CELL_CNTR 0x00f8
513#define RESET_REASS_ALL_REGS 0x00ff
514
515#define REASS_DESC_BASE 0x10
516#define VC_LKUP_BASE 0x11
517#define REASS_TABLE_BASE 0x12
518#define REASS_QUEUE_BASE 0x13
519#define PKT_TM_CNT 0x16
520#define TMOUT_RANGE 0x17
521#define INTRVL_CNTR 0x18
522#define TMOUT_INDX 0x19
523#define VP_LKUP_BASE 0x1c
524#define VP_FILTER 0x1d
525#define ABR_LKUP_BASE 0x1e
526#define FREEQ_ST_ADR 0x24
527#define FREEQ_ED_ADR 0x25
528#define FREEQ_RD_PTR 0x26
529#define FREEQ_WR_PTR 0x27
530#define PCQ_ST_ADR 0x28
531#define PCQ_ED_ADR 0x29
532#define PCQ_RD_PTR 0x2a
533#define PCQ_WR_PTR 0x2b
534#define EXCP_Q_ST_ADR 0x2c
535#define EXCP_Q_ED_ADR 0x2d
536#define EXCP_Q_RD_PTR 0x2e
537#define EXCP_Q_WR_PTR 0x2f
538#define CC_FIFO_ST_ADR 0x34
539#define CC_FIFO_ED_ADR 0x35
540#define CC_FIFO_RD_PTR 0x36
541#define CC_FIFO_WR_PTR 0x37
542#define STATE_REG 0x38
543#define BUF_SIZE 0x42
544#define XTRA_RM_OFFSET 0x44
545#define DRP_PKT_CNTR_NC 0x84
546#define ERR_CNTR_NC 0x85
547#define CELL_CNTR0_NC 0x8c
548#define CELL_CNTR1_NC 0x8d
549
550
551#define EXCPQ_EMPTY 0x0040
552#define PCQ_EMPTY 0x0010
553#define FREEQ_EMPTY 0x0004
554
555
556
557
558
559
560
561
562
563#define IPHASE5575_TX_COUNTER 0x200
564#define IPHASE5575_RX_COUNTER 0x280
565#define IPHASE5575_TX_LIST_ADDR 0x300
566#define IPHASE5575_RX_LIST_ADDR 0x380
567
568
569
570
571
572#define TX_DESC_BASE 0x0000
573#define TX_COMP_Q 0x1000
574#define PKT_RDY_Q 0x1400
575#define CBR_SCHED_TABLE 0x1800
576#define UBR_SCHED_TABLE 0x3000
577#define UBR_WAIT_Q 0x4000
578#define ABR_SCHED_TABLE 0x5000
579#define ABR_WAIT_Q 0x5800
580#define EXT_VC_TABLE 0x6000
581#define MAIN_VC_TABLE 0x8000
582#define SCHEDSZ 1024
583#define TX_DESC_TABLE_SZ 128
584
585
586
587#define DESC_MODE 0x0
588#define VC_INDEX 0x1
589#define BYTE_CNT 0x3
590#define PKT_START_HI 0x4
591#define PKT_START_LO 0x5
592
593
594#define EOM_EN 0x0800
595#define AAL5 0x0100
596#define APP_CRC32 0x0400
597#define CMPL_INT 0x1000
598
599#define TABLE_ADDRESS(db, dn, to) \
600 (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
601
602
603#define RX_DESC_BASE 0x0000
604#define VP_TABLE 0x5c00
605#define EXCEPTION_Q 0x5e00
606#define FREE_BUF_DESC_Q 0x6000
607#define PKT_COMP_Q 0x6800
608#define REASS_TABLE 0x7000
609#define RX_VC_TABLE 0x7800
610#define ABR_VC_TABLE 0x8000
611#define RX_DESC_TABLE_SZ 736
612
613#define VP_TABLE_SZ 256
614#define RX_VC_TABLE_SZ 1024
615#define REASS_TABLE_SZ 1024
616
617#define RX_ACT 0x8000
618#define RX_VPVC 0x4000
619#define RX_CNG 0x0040
620#define RX_CER 0x0008
621#define RX_PTE 0x0004
622#define RX_OFL 0x0002
623#define NUM_RX_EXCP 32
624
625
626#define NO_AAL5_PKT 0x0000
627#define AAL5_PKT_REASSEMBLED 0x4000
628#define AAL5_PKT_TERMINATED 0x8000
629#define RAW_PKT 0xc000
630#define REASS_ABR 0x2000
631
632
633#define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE
634#define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE
635#define PHY_BASE IPHASE5575_FRONT_END_REG_BASE
636#define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
637#define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
638
639typedef volatile u_int freg_t;
640typedef u_int rreg_t;
641
642typedef struct _ffredn_t {
643 freg_t idlehead_high;
644 freg_t idlehead_low;
645 freg_t maxrate;
646 freg_t stparms;
647 freg_t abrubr_abr;
648 freg_t rm_type;
649 u_int filler5[0x17 - 0x06];
650 freg_t cmd_reg;
651 u_int filler18[0x20 - 0x18];
652 freg_t cbr_base;
653 freg_t vbr_base;
654 freg_t abr_base;
655 freg_t ubr_base;
656 u_int filler24;
657 freg_t vbrwq_base;
658 freg_t abrwq_base;
659 freg_t ubrwq_base;
660 freg_t vct_base;
661 freg_t vcte_base;
662 u_int filler2a[0x2C - 0x2A];
663 freg_t cbr_tab_beg;
664 freg_t cbr_tab_end;
665 freg_t cbr_pointer;
666 u_int filler2f[0x30 - 0x2F];
667 freg_t prq_st_adr;
668 freg_t prq_ed_adr;
669 freg_t prq_rd_ptr;
670 freg_t prq_wr_ptr;
671 freg_t tcq_st_adr;
672 freg_t tcq_ed_adr;
673 freg_t tcq_rd_ptr;
674 freg_t tcq_wr_ptr;
675 u_int filler38[0x40 - 0x38];
676 freg_t queue_base;
677 freg_t desc_base;
678 u_int filler42[0x45 - 0x42];
679 freg_t mode_reg_0;
680 freg_t mode_reg_1;
681 freg_t intr_status_reg;
682 freg_t mask_reg;
683 freg_t cell_ctr_high1;
684 freg_t cell_ctr_lo1;
685 freg_t state_reg;
686 u_int filler4c[0x58 - 0x4c];
687 freg_t curr_desc_num;
688 freg_t next_desc;
689 freg_t next_vc;
690 u_int filler5b[0x5d - 0x5b];
691 freg_t present_slot_cnt;
692 u_int filler5e[0x6a - 0x5e];
693 freg_t new_desc_num;
694 freg_t new_vc;
695 freg_t sched_tbl_ptr;
696 freg_t vbrwq_wptr;
697 freg_t vbrwq_rptr;
698 freg_t abrwq_wptr;
699 freg_t abrwq_rptr;
700 freg_t ubrwq_wptr;
701 freg_t ubrwq_rptr;
702 freg_t cbr_vc;
703 freg_t vbr_sb_vc;
704 freg_t abr_sb_vc;
705 freg_t ubr_sb_vc;
706 freg_t vbr_next_link;
707 freg_t abr_next_link;
708 freg_t ubr_next_link;
709 u_int filler7a[0x7c-0x7a];
710 freg_t out_rate_head;
711 u_int filler7d[0xca-0x7d];
712 freg_t cell_ctr_high1_nc;
713 freg_t cell_ctr_lo1_nc;
714 u_int fillercc[0x100-0xcc];
715} ffredn_t;
716
717typedef struct _rfredn_t {
718 rreg_t mode_reg_0;
719 rreg_t protocol_id;
720 rreg_t mask_reg;
721 rreg_t intr_status_reg;
722 rreg_t drp_pkt_cntr;
723 rreg_t err_cntr;
724 u_int filler6[0x08 - 0x06];
725 rreg_t raw_base_adr;
726 u_int filler2[0x0c - 0x09];
727 rreg_t cell_ctr0;
728 rreg_t cell_ctr1;
729 u_int filler3[0x0f - 0x0e];
730 rreg_t cmd_reg;
731 rreg_t desc_base;
732 rreg_t vc_lkup_base;
733 rreg_t reass_base;
734 rreg_t queue_base;
735 u_int filler14[0x16 - 0x14];
736 rreg_t pkt_tm_cnt;
737 rreg_t tmout_range;
738 rreg_t intrvl_cntr;
739 rreg_t tmout_indx;
740 u_int filler1a[0x1c - 0x1a];
741 rreg_t vp_lkup_base;
742 rreg_t vp_filter;
743 rreg_t abr_lkup_base;
744 u_int filler1f[0x24 - 0x1f];
745 rreg_t fdq_st_adr;
746 rreg_t fdq_ed_adr;
747 rreg_t fdq_rd_ptr;
748 rreg_t fdq_wr_ptr;
749 rreg_t pcq_st_adr;
750 rreg_t pcq_ed_adr;
751 rreg_t pcq_rd_ptr;
752 rreg_t pcq_wr_ptr;
753 rreg_t excp_st_adr;
754 rreg_t excp_ed_adr;
755 rreg_t excp_rd_ptr;
756 rreg_t excp_wr_ptr;
757 u_int filler30[0x34 - 0x30];
758 rreg_t raw_st_adr;
759 rreg_t raw_ed_adr;
760 rreg_t raw_rd_ptr;
761 rreg_t raw_wr_ptr;
762 rreg_t state_reg;
763 u_int filler39[0x42 - 0x39];
764 rreg_t buf_size;
765 u_int filler43;
766 rreg_t xtra_rm_offset;
767 u_int filler45[0x84 - 0x45];
768 rreg_t drp_pkt_cntr_nc;
769 rreg_t err_cntr_nc;
770 u_int filler86[0x8c - 0x86];
771 rreg_t cell_ctr0_nc;
772 rreg_t cell_ctr1_nc;
773 u_int filler8e[0x100-0x8e];
774} rfredn_t;
775
776typedef struct {
777
778 ffredn_t ffredn;
779 rfredn_t rfredn;
780} ia_regs_t;
781
782typedef struct {
783 u_short f_vc_type;
784 u_short f_nrm;
785 u_short f_nrmexp;
786 u_short reserved6;
787 u_short f_crm;
788 u_short reserved10;
789 u_short reserved12;
790 u_short reserved14;
791 u_short last_cell_slot;
792 u_short f_pcr;
793 u_short fraction;
794 u_short f_icr;
795 u_short f_cdf;
796 u_short f_mcr;
797 u_short f_acr;
798 u_short f_status;
799} f_vc_abr_entry;
800
801typedef struct {
802 u_short r_status_rdf;
803 u_short r_air;
804 u_short reserved4[14];
805} r_vc_abr_entry;
806
807#define MRM 3
808
809typedef struct srv_cls_param {
810 u32 class_type;
811 u32 pcr;
812
813 u32 scr;
814 u32 max_burst_size;
815
816
817 u32 mcr;
818 u32 icr;
819 u32 tbe;
820 u32 frtt;
821
822#if 0
823bits 31 30 29 28 27-25 24-22 21-19 18-9
824-----------------------------------------------------------------------------
825| NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |
826-----------------------------------------------------------------------------
827#endif
828
829 u8 nrm;
830
831 u8 trm;
832 u16 adtf;
833 u8 cdf;
834 u8 rif;
835 u8 rdf;
836 u8 reserved;
837} srv_cls_param_t;
838
839struct testTable_t {
840 u16 lastTime;
841 u16 fract;
842 u8 vc_status;
843};
844
845typedef struct {
846 u16 vci;
847 u16 error;
848} RX_ERROR_Q;
849
850typedef struct {
851 u8 active: 1;
852 u8 abr: 1;
853 u8 ubr: 1;
854 u8 cnt: 5;
855#define VC_ACTIVE 0x01
856#define VC_ABR 0x02
857#define VC_UBR 0x04
858} vcstatus_t;
859
860struct ia_rfL_t {
861 u32 fdq_st;
862 u32 fdq_ed;
863 u32 fdq_rd;
864 u32 fdq_wr;
865 u32 pcq_st;
866 u32 pcq_ed;
867 u32 pcq_rd;
868 u32 pcq_wr;
869};
870
871struct ia_ffL_t {
872 u32 prq_st;
873 u32 prq_ed;
874 u32 prq_wr;
875 u32 tcq_st;
876 u32 tcq_ed;
877 u32 tcq_rd;
878};
879
880struct desc_tbl_t {
881 u32 timestamp;
882 struct ia_vcc *iavcc;
883 struct sk_buff *txskb;
884};
885
886typedef struct ia_rtn_q {
887 struct desc_tbl_t data;
888 struct ia_rtn_q *next, *tail;
889} IARTN_Q;
890
891#define SUNI_LOSV 0x04
892typedef struct {
893 u32 suni_master_reset;
894 u32 suni_master_config;
895 u32 suni_master_intr_stat;
896 u32 suni_reserved1;
897 u32 suni_master_clk_monitor;
898 u32 suni_master_control;
899 u32 suni_reserved2[10];
900
901 u32 suni_rsop_control;
902 u32 suni_rsop_status;
903 u32 suni_rsop_section_bip8l;
904 u32 suni_rsop_section_bip8m;
905
906 u32 suni_tsop_control;
907 u32 suni_tsop_diag;
908 u32 suni_tsop_reserved[2];
909
910 u32 suni_rlop_cs;
911 u32 suni_rlop_intr;
912 u32 suni_rlop_line_bip24l;
913 u32 suni_rlop_line_bip24;
914 u32 suni_rlop_line_bip24m;
915 u32 suni_rlop_line_febel;
916 u32 suni_rlop_line_febe;
917 u32 suni_rlop_line_febem;
918
919 u32 suni_tlop_control;
920 u32 suni_tlop_disg;
921 u32 suni_tlop_reserved[14];
922
923 u32 suni_rpop_cs;
924 u32 suni_rpop_intr;
925 u32 suni_rpop_reserved;
926 u32 suni_rpop_intr_ena;
927 u32 suni_rpop_reserved1[3];
928 u32 suni_rpop_path_sig;
929 u32 suni_rpop_bip8l;
930 u32 suni_rpop_bip8m;
931 u32 suni_rpop_febel;
932 u32 suni_rpop_febem;
933 u32 suni_rpop_reserved2[4];
934
935 u32 suni_tpop_cntrl_daig;
936 u32 suni_tpop_pointer_ctrl;
937 u32 suni_tpop_sourcer_ctrl;
938 u32 suni_tpop_reserved1[2];
939 u32 suni_tpop_arb_prtl;
940 u32 suni_tpop_arb_prtm;
941 u32 suni_tpop_reserved2;
942 u32 suni_tpop_path_sig;
943 u32 suni_tpop_path_status;
944 u32 suni_tpop_reserved3[6];
945
946 u32 suni_racp_cs;
947 u32 suni_racp_intr;
948 u32 suni_racp_hdr_pattern;
949 u32 suni_racp_hdr_mask;
950 u32 suni_racp_corr_hcs;
951 u32 suni_racp_uncorr_hcs;
952 u32 suni_racp_reserved[10];
953
954 u32 suni_tacp_control;
955 u32 suni_tacp_idle_hdr_pat;
956 u32 suni_tacp_idle_pay_pay;
957 u32 suni_tacp_reserved[5];
958
959 u32 suni_reserved3[24];
960
961 u32 suni_master_test;
962 u32 suni_reserved_test;
963} IA_SUNI;
964
965
966typedef struct _SUNI_STATS_
967{
968 u32 valid;
969 u32 carrier_detect;
970
971 u16 rsop_oof_state;
972 u16 rsop_lof_state;
973 u16 rsop_los_state;
974 u32 rsop_los_count;
975 u32 rsop_bse_count;
976
977 u16 rlop_ferf_state;
978 u16 rlop_lais_state;
979 u32 rlop_lbe_count;
980 u32 rlop_febe_count;
981
982 u16 rpop_lop_state;
983 u16 rpop_pais_state;
984 u16 rpop_pyel_state;
985 u32 rpop_bip_count;
986 u32 rpop_febe_count;
987 u16 rpop_psig;
988
989 u16 racp_hp_state;
990 u32 racp_fu_count;
991 u32 racp_fo_count;
992 u32 racp_chcs_count;
993 u32 racp_uchcs_count;
994} IA_SUNI_STATS;
995
996typedef struct iadev_t {
997
998 u32 __iomem *phy;
999 u32 __iomem *dma;
1000
1001 u32 __iomem *reg;
1002
1003 u32 __iomem *seg_reg;
1004
1005 u32 __iomem *reass_reg;
1006
1007 u32 __iomem *ram;
1008 void __iomem *seg_ram;
1009 void __iomem *reass_ram;
1010 struct dle_q tx_dle_q;
1011 struct free_desc_q *tx_free_desc_qhead;
1012 struct sk_buff_head tx_dma_q, tx_backlog;
1013 spinlock_t tx_lock;
1014 IARTN_Q tx_return_q;
1015 u32 close_pending;
1016 wait_queue_head_t close_wait;
1017 wait_queue_head_t timeout_wait;
1018 struct cpcs_trailer_desc *tx_buf;
1019 u16 num_tx_desc, tx_buf_sz, rate_limit;
1020 u32 tx_cell_cnt, tx_pkt_cnt;
1021 void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
1022 struct dle_q rx_dle_q;
1023 struct free_desc_q *rx_free_desc_qhead;
1024 struct sk_buff_head rx_dma_q;
1025 spinlock_t rx_lock;
1026 struct atm_vcc **rx_open;
1027 u16 num_rx_desc, rx_buf_sz, rxing;
1028 u32 rx_pkt_ram, rx_tmp_cnt;
1029 unsigned long rx_tmp_jif;
1030 void __iomem *RX_DESC_BASE_ADDR;
1031 u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
1032 struct atm_dev *next_board;
1033 struct pci_dev *pci;
1034 int mem;
1035 unsigned int real_base;
1036 void __iomem *base;
1037 unsigned int pci_map_size;
1038 unsigned char irq;
1039 unsigned char bus;
1040 unsigned char dev_fn;
1041 u_short phy_type;
1042 u_short num_vc, memSize, memType;
1043 struct ia_ffL_t ffL;
1044 struct ia_rfL_t rfL;
1045
1046
1047 unsigned char carrier_detect;
1048
1049
1050 unsigned int tx_dma_cnt;
1051 unsigned int rx_dma_cnt;
1052 unsigned int NumEnabledCBR;
1053
1054 unsigned int rx_mark_cnt;
1055 unsigned int CbrTotEntries;
1056 unsigned int CbrRemEntries;
1057 unsigned int CbrEntryPt;
1058 unsigned int Granularity;
1059
1060 unsigned int sum_mcr, sum_cbr, LineRate;
1061 unsigned int n_abr;
1062 struct desc_tbl_t *desc_tbl;
1063 u_short host_tcq_wr;
1064 struct testTable_t **testTable;
1065 dma_addr_t tx_dle_dma;
1066 dma_addr_t rx_dle_dma;
1067} IADEV;
1068
1069
1070#define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1071#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1072
1073
1074typedef struct {
1075 u_int mb25_master_ctrl;
1076 u_int mb25_intr_status;
1077 u_int mb25_diag_control;
1078 u_int mb25_led_hec;
1079 u_int mb25_low_byte_counter;
1080 u_int mb25_high_byte_counter;
1081} ia_mb25_t;
1082
1083
1084
1085
1086#define MB25_MC_UPLO 0x80
1087#define MB25_MC_DREC 0x40
1088#define MB25_MC_ECEIO 0x20
1089#define MB25_MC_TDPC 0x10
1090#define MB25_MC_DRIC 0x08
1091#define MB25_MC_HALTTX 0x04
1092#define MB25_MC_UMS 0x02
1093#define MB25_MC_ENABLED 0x01
1094
1095
1096
1097
1098#define MB25_IS_GSB 0x40
1099#define MB25_IS_HECECR 0x20
1100#define MB25_IS_SCR 0x10
1101#define MB25_IS_TPE 0x08
1102#define MB25_IS_RSCC 0x04
1103#define MB25_IS_RCSE 0x02
1104#define MB25_IS_RFIFOO 0x01
1105
1106
1107
1108
1109#define MB25_DC_FTXCD 0x80
1110#define MB25_DC_RXCOS 0x40
1111#define MB25_DC_ECEIO 0x20
1112#define MB25_DC_RLFLUSH 0x10
1113#define MB25_DC_IXPE 0x08
1114#define MB25_DC_IXHECE 0x04
1115#define MB25_DC_LB_MASK 0x03
1116
1117#define MB25_DC_LL 0x03
1118#define MB25_DC_PL 0x02
1119#define MB25_DC_NM 0x00
1120
1121#define FE_MASK 0x00F0
1122#define FE_MULTI_MODE 0x0000
1123#define FE_SINGLE_MODE 0x0010
1124#define FE_UTP_OPTION 0x0020
1125#define FE_25MBIT_PHY 0x0040
1126#define FE_DS3_PHY 0x0080
1127#define FE_E3_PHY 0x0090
1128
1129
1130typedef struct _suni_pm7345_t
1131{
1132 u_int suni_config;
1133 u_int suni_intr_enbl;
1134 u_int suni_intr_stat;
1135 u_int suni_control;
1136 u_int suni_id_reset;
1137 u_int suni_data_link_ctrl;
1138 u_int suni_rboc_conf_intr_enbl;
1139 u_int suni_rboc_stat;
1140 u_int suni_ds3_frm_cfg;
1141 u_int suni_ds3_frm_intr_enbl;
1142 u_int suni_ds3_frm_intr_stat;
1143 u_int suni_ds3_frm_stat;
1144 u_int suni_rfdl_cfg;
1145 u_int suni_rfdl_enbl_stat;
1146 u_int suni_rfdl_stat;
1147 u_int suni_rfdl_data;
1148 u_int suni_pmon_chng;
1149 u_int suni_pmon_intr_enbl_stat;
1150 u_int suni_reserved1[0x13-0x11];
1151 u_int suni_pmon_lcv_evt_cnt_lsb;
1152 u_int suni_pmon_lcv_evt_cnt_msb;
1153 u_int suni_pmon_fbe_evt_cnt_lsb;
1154 u_int suni_pmon_fbe_evt_cnt_msb;
1155 u_int suni_pmon_sez_det_cnt_lsb;
1156 u_int suni_pmon_sez_det_cnt_msb;
1157 u_int suni_pmon_pe_evt_cnt_lsb;
1158 u_int suni_pmon_pe_evt_cnt_msb;
1159 u_int suni_pmon_ppe_evt_cnt_lsb;
1160 u_int suni_pmon_ppe_evt_cnt_msb;
1161 u_int suni_pmon_febe_evt_cnt_lsb;
1162 u_int suni_pmon_febe_evt_cnt_msb;
1163 u_int suni_ds3_tran_cfg;
1164 u_int suni_ds3_tran_diag;
1165 u_int suni_reserved2[0x23-0x21];
1166 u_int suni_xfdl_cfg;
1167 u_int suni_xfdl_intr_st;
1168 u_int suni_xfdl_xmit_data;
1169 u_int suni_xboc_code;
1170 u_int suni_splr_cfg;
1171 u_int suni_splr_intr_en;
1172 u_int suni_splr_intr_st;
1173 u_int suni_splr_status;
1174 u_int suni_splt_cfg;
1175 u_int suni_splt_cntl;
1176 u_int suni_splt_diag_g1;
1177 u_int suni_splt_f1;
1178 u_int suni_cppm_loc_meters;
1179 u_int suni_cppm_chng_of_cppm_perf_meter;
1180 u_int suni_cppm_b1_err_cnt_lsb;
1181 u_int suni_cppm_b1_err_cnt_msb;
1182 u_int suni_cppm_framing_err_cnt_lsb;
1183 u_int suni_cppm_framing_err_cnt_msb;
1184 u_int suni_cppm_febe_cnt_lsb;
1185 u_int suni_cppm_febe_cnt_msb;
1186 u_int suni_cppm_hcs_err_cnt_lsb;
1187 u_int suni_cppm_hcs_err_cnt_msb;
1188 u_int suni_cppm_idle_un_cell_cnt_lsb;
1189 u_int suni_cppm_idle_un_cell_cnt_msb;
1190 u_int suni_cppm_rcv_cell_cnt_lsb;
1191 u_int suni_cppm_rcv_cell_cnt_msb;
1192 u_int suni_cppm_xmit_cell_cnt_lsb;
1193 u_int suni_cppm_xmit_cell_cnt_msb;
1194 u_int suni_rxcp_ctrl;
1195 u_int suni_rxcp_fctrl;
1196 u_int suni_rxcp_intr_en_sts;
1197 u_int suni_rxcp_idle_pat_h1;
1198 u_int suni_rxcp_idle_pat_h2;
1199 u_int suni_rxcp_idle_pat_h3;
1200 u_int suni_rxcp_idle_pat_h4;
1201 u_int suni_rxcp_idle_mask_h1;
1202 u_int suni_rxcp_idle_mask_h2;
1203 u_int suni_rxcp_idle_mask_h3;
1204 u_int suni_rxcp_idle_mask_h4;
1205 u_int suni_rxcp_cell_pat_h1;
1206 u_int suni_rxcp_cell_pat_h2;
1207 u_int suni_rxcp_cell_pat_h3;
1208 u_int suni_rxcp_cell_pat_h4;
1209 u_int suni_rxcp_cell_mask_h1;
1210 u_int suni_rxcp_cell_mask_h2;
1211 u_int suni_rxcp_cell_mask_h3;
1212 u_int suni_rxcp_cell_mask_h4;
1213 u_int suni_rxcp_hcs_cs;
1214 u_int suni_rxcp_lcd_cnt_threshold;
1215 u_int suni_reserved3[0x57-0x54];
1216 u_int suni_txcp_ctrl;
1217 u_int suni_txcp_intr_en_sts;
1218 u_int suni_txcp_idle_pat_h1;
1219 u_int suni_txcp_idle_pat_h2;
1220 u_int suni_txcp_idle_pat_h3;
1221 u_int suni_txcp_idle_pat_h4;
1222 u_int suni_txcp_idle_pat_h5;
1223 u_int suni_txcp_idle_payload;
1224 u_int suni_e3_frm_fram_options;
1225 u_int suni_e3_frm_maint_options;
1226 u_int suni_e3_frm_fram_intr_enbl;
1227 u_int suni_e3_frm_fram_intr_ind_stat;
1228 u_int suni_e3_frm_maint_intr_enbl;
1229 u_int suni_e3_frm_maint_intr_ind;
1230 u_int suni_e3_frm_maint_stat;
1231 u_int suni_reserved4;
1232 u_int suni_e3_tran_fram_options;
1233 u_int suni_e3_tran_stat_diag_options;
1234 u_int suni_e3_tran_bip_8_err_mask;
1235 u_int suni_e3_tran_maint_adapt_options;
1236 u_int suni_ttb_ctrl;
1237 u_int suni_ttb_trail_trace_id_stat;
1238 u_int suni_ttb_ind_addr;
1239 u_int suni_ttb_ind_data;
1240 u_int suni_ttb_exp_payload_type;
1241 u_int suni_ttb_payload_type_ctrl_stat;
1242 u_int suni_pad5[0x7f-0x71];
1243 u_int suni_master_test;
1244 u_int suni_pad6[0xff-0x80];
1245}suni_pm7345_t;
1246
1247#define SUNI_PM7345_T suni_pm7345_t
1248#define SUNI_PM7345 0x20
1249#define SUNI_PM5346 0x30
1250
1251
1252
1253#define SUNI_PM7345_CLB 0x01
1254#define SUNI_PM7345_PLB 0x02
1255#define SUNI_PM7345_DLB 0x04
1256#define SUNI_PM7345_LLB 0x80
1257#define SUNI_PM7345_E3ENBL 0x40
1258#define SUNI_PM7345_LOOPT 0x10
1259#define SUNI_PM7345_FIFOBP 0x20
1260#define SUNI_PM7345_FRMRBP 0x08
1261
1262
1263
1264#define SUNI_DS3_COFAE 0x80
1265#define SUNI_DS3_REDE 0x40
1266#define SUNI_DS3_CBITE 0x20
1267#define SUNI_DS3_FERFE 0x10
1268#define SUNI_DS3_IDLE 0x08
1269#define SUNI_DS3_AISE 0x04
1270#define SUNI_DS3_OOFE 0x02
1271#define SUNI_DS3_LOSE 0x01
1272
1273
1274
1275
1276#define SUNI_DS3_ACE 0x80
1277#define SUNI_DS3_REDV 0x40
1278#define SUNI_DS3_CBITV 0x20
1279#define SUNI_DS3_FERFV 0x10
1280#define SUNI_DS3_IDLV 0x08
1281#define SUNI_DS3_AISV 0x04
1282#define SUNI_DS3_OOFV 0x02
1283#define SUNI_DS3_LOSV 0x01
1284
1285
1286
1287
1288#define SUNI_E3_CZDI 0x40
1289#define SUNI_E3_LOSI 0x20
1290#define SUNI_E3_LCVI 0x10
1291#define SUNI_E3_COFAI 0x08
1292#define SUNI_E3_OOFI 0x04
1293#define SUNI_E3_LOS 0x02
1294#define SUNI_E3_OOF 0x01
1295
1296
1297
1298
1299#define SUNI_E3_AISD 0x80
1300#define SUNI_E3_FERF_RAI 0x40
1301#define SUNI_E3_FEBE 0x20
1302
1303
1304
1305
1306#define SUNI_DS3_HCSPASS 0x80
1307#define SUNI_DS3_HCSDQDB 0x40
1308#define SUNI_DS3_HCSADD 0x20
1309#define SUNI_DS3_HCK 0x10
1310#define SUNI_DS3_BLOCK 0x08
1311#define SUNI_DS3_DSCR 0x04
1312#define SUNI_DS3_OOCDV 0x02
1313#define SUNI_DS3_FIFORST 0x01
1314
1315
1316
1317
1318#define SUNI_DS3_OOCDE 0x80
1319#define SUNI_DS3_HCSE 0x40
1320#define SUNI_DS3_FIFOE 0x20
1321#define SUNI_DS3_OOCDI 0x10
1322#define SUNI_DS3_UHCSI 0x08
1323#define SUNI_DS3_COCAI 0x04
1324#define SUNI_DS3_FOVRI 0x02
1325#define SUNI_DS3_FUDRI 0x01
1326
1327
1328
1329
1330#define MEM_SIZE_MASK 0x000F
1331#define MEM_SIZE_128K 0x0000
1332#define MEM_SIZE_512K 0x0001
1333#define MEM_SIZE_1M 0x0002
1334
1335
1336#define FE_MASK 0x00F0
1337#define FE_MULTI_MODE 0x0000
1338#define FE_SINGLE_MODE 0x0010
1339#define FE_UTP_OPTION 0x0020
1340
1341#define NOVRAM_SIZE 64
1342#define CMD_LEN 10
1343
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1358#define EXTEND 0x100
1359#define IAWRITE 0x140
1360#define IAREAD 0x180
1361#define ERASE 0x1c0
1362
1363#define EWDS 0x00
1364#define WRAL 0x10
1365#define ERAL 0x20
1366#define EWEN 0x30
1367
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1371
1372
1373#define NVCE 0x02
1374#define NVSK 0x01
1375#define NVDO 0x08
1376#define NVDI 0x04
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1383
1384#define CFG_AND(val) { \
1385 u32 t; \
1386 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1387 t &= (val); \
1388 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1389 }
1390
1391
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1397
1398#define CFG_OR(val) { \
1399 u32 t; \
1400 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1401 t |= (val); \
1402 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1403 }
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1414
1415#define NVRAM_CMD(cmd) { \
1416 int i; \
1417 u_short c = cmd; \
1418 CFG_AND(~(NVCE|NVSK)); \
1419 CFG_OR(NVCE); \
1420 for (i=0; i<CMD_LEN; i++) { \
1421 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1422 c <<= 1; \
1423 } \
1424 }
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1431
1432#define NVRAM_CLR_CE {CFG_AND(~NVCE)}
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1440
1441#define NVRAM_CLKOUT(bitval) { \
1442 CFG_AND(~NVDI); \
1443 CFG_OR((bitval) ? NVDI : 0); \
1444 CFG_OR(NVSK); \
1445 CFG_AND( ~NVSK); \
1446 }
1447
1448
1449
1450
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1454
1455#define NVRAM_CLKIN(value) { \
1456 u32 _t; \
1457 CFG_OR(NVSK); \
1458 CFG_AND(~NVSK); \
1459 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1460 value = (_t & NVDO) ? 1 : 0; \
1461 }
1462
1463
1464#endif
1465