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8#include "scan.h"
9#include "bcma_private.h"
10
11#include <linux/bcma/bcma.h>
12#include <linux/bcma/bcma_regs.h>
13#include <linux/pci.h>
14#include <linux/io.h>
15#include <linux/dma-mapping.h>
16#include <linux/slab.h>
17
18struct bcma_device_id_name {
19 u16 id;
20 const char *name;
21};
22struct bcma_device_id_name bcma_device_names[] = {
23 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
24 { BCMA_CORE_INVALID, "Invalid" },
25 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
26 { BCMA_CORE_ILINE20, "ILine 20" },
27 { BCMA_CORE_SRAM, "SRAM" },
28 { BCMA_CORE_SDRAM, "SDRAM" },
29 { BCMA_CORE_PCI, "PCI" },
30 { BCMA_CORE_MIPS, "MIPS" },
31 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
32 { BCMA_CORE_V90, "V90" },
33 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
34 { BCMA_CORE_ADSL, "ADSL" },
35 { BCMA_CORE_ILINE100, "ILine 100" },
36 { BCMA_CORE_IPSEC, "IPSEC" },
37 { BCMA_CORE_UTOPIA, "UTOPIA" },
38 { BCMA_CORE_PCMCIA, "PCMCIA" },
39 { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
40 { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
41 { BCMA_CORE_OFDM, "OFDM" },
42 { BCMA_CORE_EXTIF, "EXTIF" },
43 { BCMA_CORE_80211, "IEEE 802.11" },
44 { BCMA_CORE_PHY_A, "PHY A" },
45 { BCMA_CORE_PHY_B, "PHY B" },
46 { BCMA_CORE_PHY_G, "PHY G" },
47 { BCMA_CORE_MIPS_3302, "MIPS 3302" },
48 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
49 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
50 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
51 { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
52 { BCMA_CORE_SDIO_HOST, "SDIO Host" },
53 { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
54 { BCMA_CORE_PARA_ATA, "PATA" },
55 { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
56 { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
57 { BCMA_CORE_PCIE, "PCIe" },
58 { BCMA_CORE_PHY_N, "PHY N" },
59 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
60 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
61 { BCMA_CORE_ARM_1176, "ARM 1176" },
62 { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
63 { BCMA_CORE_PHY_LP, "PHY LP" },
64 { BCMA_CORE_PMU, "PMU" },
65 { BCMA_CORE_PHY_SSN, "PHY SSN" },
66 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
67 { BCMA_CORE_ARM_CM3, "ARM CM3" },
68 { BCMA_CORE_PHY_HT, "PHY HT" },
69 { BCMA_CORE_MIPS_74K, "MIPS 74K" },
70 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
71 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
72 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
73 { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
74 { BCMA_CORE_SHARED_COMMON, "Common Shared" },
75 { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
76 { BCMA_CORE_SPI_HOST, "SPI Host" },
77 { BCMA_CORE_I2S, "I2S" },
78 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
79 { BCMA_CORE_SHIM, "SHIM" },
80 { BCMA_CORE_DEFAULT, "Default" },
81};
82const char *bcma_device_name(struct bcma_device_id *id)
83{
84 int i;
85
86 if (id->manuf == BCMA_MANUF_BCM) {
87 for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
88 if (bcma_device_names[i].id == id->id)
89 return bcma_device_names[i].name;
90 }
91 }
92 return "UNKNOWN";
93}
94
95static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
96 u16 offset)
97{
98 return readl(bus->mmio + offset);
99}
100
101static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
102{
103 if (bus->hosttype == BCMA_HOSTTYPE_PCI)
104 pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
105 addr);
106}
107
108static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
109{
110 u32 ent = readl(*eromptr);
111 (*eromptr)++;
112 return ent;
113}
114
115static void bcma_erom_push_ent(u32 **eromptr)
116{
117 (*eromptr)--;
118}
119
120static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
121{
122 u32 ent = bcma_erom_get_ent(bus, eromptr);
123 if (!(ent & SCAN_ER_VALID))
124 return -ENOENT;
125 if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
126 return -ENOENT;
127 return ent;
128}
129
130static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
131{
132 u32 ent = bcma_erom_get_ent(bus, eromptr);
133 bcma_erom_push_ent(eromptr);
134 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
135}
136
137static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
138{
139 u32 ent = bcma_erom_get_ent(bus, eromptr);
140 bcma_erom_push_ent(eromptr);
141 return (((ent & SCAN_ER_VALID)) &&
142 ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
143 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
144}
145
146static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
147{
148 u32 ent;
149 while (1) {
150 ent = bcma_erom_get_ent(bus, eromptr);
151 if ((ent & SCAN_ER_VALID) &&
152 ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
153 break;
154 if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
155 break;
156 }
157 bcma_erom_push_ent(eromptr);
158}
159
160static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
161{
162 u32 ent = bcma_erom_get_ent(bus, eromptr);
163 if (!(ent & SCAN_ER_VALID))
164 return -ENOENT;
165 if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
166 return -ENOENT;
167 return ent;
168}
169
170static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
171 u32 type, u8 port)
172{
173 u32 addrl, addrh, sizel, sizeh = 0;
174 u32 size;
175
176 u32 ent = bcma_erom_get_ent(bus, eromptr);
177 if ((!(ent & SCAN_ER_VALID)) ||
178 ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
179 ((ent & SCAN_ADDR_TYPE) != type) ||
180 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
181 bcma_erom_push_ent(eromptr);
182 return -EINVAL;
183 }
184
185 addrl = ent & SCAN_ADDR_ADDR;
186 if (ent & SCAN_ADDR_AG32)
187 addrh = bcma_erom_get_ent(bus, eromptr);
188 else
189 addrh = 0;
190
191 if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
192 size = bcma_erom_get_ent(bus, eromptr);
193 sizel = size & SCAN_SIZE_SZ;
194 if (size & SCAN_SIZE_SG32)
195 sizeh = bcma_erom_get_ent(bus, eromptr);
196 } else
197 sizel = SCAN_ADDR_SZ_BASE <<
198 ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
199
200 return addrl;
201}
202
203int bcma_bus_scan(struct bcma_bus *bus)
204{
205 u32 erombase;
206 u32 __iomem *eromptr, *eromend;
207
208 s32 cia, cib;
209 u8 ports[2], wrappers[2];
210
211 s32 tmp;
212 u8 i, j;
213
214 int err;
215
216 INIT_LIST_HEAD(&bus->cores);
217 bus->nr_cores = 0;
218
219 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
220
221 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
222 bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
223 bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
224 bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
225
226 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
227 eromptr = bus->mmio;
228 eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
229
230 bcma_scan_switch_core(bus, erombase);
231
232 while (eromptr < eromend) {
233 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
234 if (!core)
235 return -ENOMEM;
236 INIT_LIST_HEAD(&core->list);
237 core->bus = bus;
238
239
240 cia = bcma_erom_get_ci(bus, &eromptr);
241 if (cia < 0) {
242 bcma_erom_push_ent(&eromptr);
243 if (bcma_erom_is_end(bus, &eromptr))
244 break;
245 err= -EILSEQ;
246 goto out;
247 }
248 cib = bcma_erom_get_ci(bus, &eromptr);
249 if (cib < 0) {
250 err= -EILSEQ;
251 goto out;
252 }
253
254
255 core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
256 core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
257 core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
258 ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
259 ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
260 wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
261 wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
262 core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
263
264 if (((core->id.manuf == BCMA_MANUF_ARM) &&
265 (core->id.id == 0xFFF)) ||
266 (ports[1] == 0)) {
267 bcma_erom_skip_component(bus, &eromptr);
268 continue;
269 }
270
271
272 if (wrappers[0] + wrappers[1] == 0) {
273
274
275
276 bcma_erom_skip_component(bus, &eromptr);
277 continue;
278 }
279
280 if (bcma_erom_is_bridge(bus, &eromptr)) {
281 bcma_erom_skip_component(bus, &eromptr);
282 continue;
283 }
284
285
286 for (i = 0; i < ports[0]; i++) {
287 u32 mst_port_d = bcma_erom_get_mst_port(bus, &eromptr);
288 if (mst_port_d < 0) {
289 err= -EILSEQ;
290 goto out;
291 }
292 }
293
294
295 for (i = 0; i < ports[1]; i++) {
296 for (j = 0; ; j++) {
297 tmp = bcma_erom_get_addr_desc(bus, &eromptr,
298 SCAN_ADDR_TYPE_SLAVE, i);
299 if (tmp < 0) {
300
301
302
303 break;
304 } else {
305 if (i == 0 && j == 0)
306 core->addr = tmp;
307 }
308 }
309 }
310
311
312 for (i = 0; i < wrappers[0]; i++) {
313 for (j = 0; ; j++) {
314 tmp = bcma_erom_get_addr_desc(bus, &eromptr,
315 SCAN_ADDR_TYPE_MWRAP, i);
316 if (tmp < 0) {
317
318
319
320 break;
321 } else {
322 if (i == 0 && j == 0)
323 core->wrap = tmp;
324 }
325 }
326 }
327
328
329 for (i = 0; i < wrappers[1]; i++) {
330 u8 hack = (ports[1] == 1) ? 0 : 1;
331 for (j = 0; ; j++) {
332 tmp = bcma_erom_get_addr_desc(bus, &eromptr,
333 SCAN_ADDR_TYPE_SWRAP, i + hack);
334 if (tmp < 0) {
335
336
337
338 break;
339 } else {
340 if (wrappers[0] == 0 && !i && !j)
341 core->wrap = tmp;
342 }
343 }
344 }
345
346 pr_info("Core %d found: %s "
347 "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
348 bus->nr_cores, bcma_device_name(&core->id),
349 core->id.manuf, core->id.id, core->id.rev,
350 core->id.class);
351
352 core->core_index = bus->nr_cores++;
353 list_add(&core->list, &bus->cores);
354 continue;
355out:
356 return err;
357 }
358
359 return 0;
360}
361
