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22#include "cxd2820r_priv.h"
23
24int cxd2820r_set_frontend_t2(struct dvb_frontend *fe,
25 struct dvb_frontend_parameters *params)
26{
27 struct cxd2820r_priv *priv = fe->demodulator_priv;
28 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
29 int ret, i;
30 u32 if_khz, if_ctl;
31 u64 num;
32 u8 buf[3], bw_param;
33 u8 bw_params1[][5] = {
34 { 0x1c, 0xb3, 0x33, 0x33, 0x33 },
35 { 0x17, 0xea, 0xaa, 0xaa, 0xaa },
36 { 0x14, 0x80, 0x00, 0x00, 0x00 },
37 { 0x11, 0xf0, 0x00, 0x00, 0x00 },
38 };
39 struct reg_val_mask tab[] = {
40 { 0x00080, 0x02, 0xff },
41 { 0x00081, 0x20, 0xff },
42 { 0x00085, 0x07, 0xff },
43 { 0x00088, 0x01, 0xff },
44 { 0x02069, 0x01, 0xff },
45
46 { 0x0207f, 0x2a, 0xff },
47 { 0x02082, 0x0a, 0xff },
48 { 0x02083, 0x0a, 0xff },
49 { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 },
50 { 0x02070, priv->cfg.ts_mode, 0xff },
51 { 0x020b5, priv->cfg.spec_inv << 4, 0x10 },
52 { 0x02567, 0x07, 0x0f },
53 { 0x02569, 0x03, 0x03 },
54 { 0x02595, 0x1a, 0xff },
55 { 0x02596, 0x50, 0xff },
56 { 0x02a8c, 0x00, 0xff },
57 { 0x02a8d, 0x34, 0xff },
58 { 0x02a45, 0x06, 0x07 },
59 { 0x03f10, 0x0d, 0xff },
60 { 0x03f11, 0x02, 0xff },
61 { 0x03f12, 0x01, 0xff },
62 { 0x03f23, 0x2c, 0xff },
63 { 0x03f51, 0x13, 0xff },
64 { 0x03f52, 0x01, 0xff },
65 { 0x03f53, 0x00, 0xff },
66 { 0x027e6, 0x14, 0xff },
67 { 0x02786, 0x02, 0x07 },
68 { 0x02787, 0x40, 0xe0 },
69 { 0x027ef, 0x10, 0x18 },
70 };
71
72 dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
73
74
75 ret = cxd2820r_gpio(fe);
76 if (ret)
77 goto error;
78
79
80 if (fe->ops.tuner_ops.set_params)
81 fe->ops.tuner_ops.set_params(fe, params);
82
83 if (priv->delivery_system != SYS_DVBT2) {
84 for (i = 0; i < ARRAY_SIZE(tab); i++) {
85 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
86 tab[i].val, tab[i].mask);
87 if (ret)
88 goto error;
89 }
90 }
91
92 priv->delivery_system = SYS_DVBT2;
93
94 switch (c->bandwidth_hz) {
95 case 5000000:
96 if_khz = priv->cfg.if_dvbt2_5;
97 i = 0;
98 bw_param = 3;
99 break;
100 case 6000000:
101 if_khz = priv->cfg.if_dvbt2_6;
102 i = 1;
103 bw_param = 2;
104 break;
105 case 7000000:
106 if_khz = priv->cfg.if_dvbt2_7;
107 i = 2;
108 bw_param = 1;
109 break;
110 case 8000000:
111 if_khz = priv->cfg.if_dvbt2_8;
112 i = 3;
113 bw_param = 0;
114 break;
115 default:
116 return -EINVAL;
117 }
118
119 num = if_khz;
120 num *= 0x1000000;
121 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
122 buf[0] = ((if_ctl >> 16) & 0xff);
123 buf[1] = ((if_ctl >> 8) & 0xff);
124 buf[2] = ((if_ctl >> 0) & 0xff);
125
126 ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3);
127 if (ret)
128 goto error;
129
130 ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[i], 5);
131 if (ret)
132 goto error;
133
134 ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0);
135 if (ret)
136 goto error;
137
138 ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
139 if (ret)
140 goto error;
141
142 ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
143 if (ret)
144 goto error;
145
146 return ret;
147error:
148 dbg("%s: failed:%d", __func__, ret);
149 return ret;
150
151}
152
153int cxd2820r_get_frontend_t2(struct dvb_frontend *fe,
154 struct dvb_frontend_parameters *p)
155{
156 struct cxd2820r_priv *priv = fe->demodulator_priv;
157 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
158 int ret;
159 u8 buf[2];
160
161 ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2);
162 if (ret)
163 goto error;
164
165 switch ((buf[0] >> 0) & 0x07) {
166 case 0:
167 c->transmission_mode = TRANSMISSION_MODE_2K;
168 break;
169 case 1:
170 c->transmission_mode = TRANSMISSION_MODE_8K;
171 break;
172 case 2:
173 c->transmission_mode = TRANSMISSION_MODE_4K;
174 break;
175 case 3:
176 c->transmission_mode = TRANSMISSION_MODE_1K;
177 break;
178 case 4:
179 c->transmission_mode = TRANSMISSION_MODE_16K;
180 break;
181 case 5:
182 c->transmission_mode = TRANSMISSION_MODE_32K;
183 break;
184 }
185
186 switch ((buf[1] >> 4) & 0x07) {
187 case 0:
188 c->guard_interval = GUARD_INTERVAL_1_32;
189 break;
190 case 1:
191 c->guard_interval = GUARD_INTERVAL_1_16;
192 break;
193 case 2:
194 c->guard_interval = GUARD_INTERVAL_1_8;
195 break;
196 case 3:
197 c->guard_interval = GUARD_INTERVAL_1_4;
198 break;
199 case 4:
200 c->guard_interval = GUARD_INTERVAL_1_128;
201 break;
202 case 5:
203 c->guard_interval = GUARD_INTERVAL_19_128;
204 break;
205 case 6:
206 c->guard_interval = GUARD_INTERVAL_19_256;
207 break;
208 }
209
210 ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2);
211 if (ret)
212 goto error;
213
214 switch ((buf[0] >> 0) & 0x07) {
215 case 0:
216 c->fec_inner = FEC_1_2;
217 break;
218 case 1:
219 c->fec_inner = FEC_3_5;
220 break;
221 case 2:
222 c->fec_inner = FEC_2_3;
223 break;
224 case 3:
225 c->fec_inner = FEC_3_4;
226 break;
227 case 4:
228 c->fec_inner = FEC_4_5;
229 break;
230 case 5:
231 c->fec_inner = FEC_5_6;
232 break;
233 }
234
235 switch ((buf[1] >> 0) & 0x07) {
236 case 0:
237 c->modulation = QPSK;
238 break;
239 case 1:
240 c->modulation = QAM_16;
241 break;
242 case 2:
243 c->modulation = QAM_64;
244 break;
245 case 3:
246 c->modulation = QAM_256;
247 break;
248 }
249
250 ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]);
251 if (ret)
252 goto error;
253
254 switch ((buf[0] >> 4) & 0x01) {
255 case 0:
256 c->inversion = INVERSION_OFF;
257 break;
258 case 1:
259 c->inversion = INVERSION_ON;
260 break;
261 }
262
263 return ret;
264error:
265 dbg("%s: failed:%d", __func__, ret);
266 return ret;
267}
268
269int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status)
270{
271 struct cxd2820r_priv *priv = fe->demodulator_priv;
272 int ret;
273 u8 buf[1];
274 *status = 0;
275
276 ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]);
277 if (ret)
278 goto error;
279
280 if ((buf[0] & 0x07) == 6) {
281 if (((buf[0] >> 5) & 0x01) == 1) {
282 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
283 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
284 } else {
285 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
286 FE_HAS_VITERBI | FE_HAS_SYNC;
287 }
288 }
289
290 dbg("%s: lock=%02x", __func__, buf[0]);
291
292 return ret;
293error:
294 dbg("%s: failed:%d", __func__, ret);
295 return ret;
296}
297
298int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber)
299{
300 struct cxd2820r_priv *priv = fe->demodulator_priv;
301 int ret;
302 u8 buf[4];
303 unsigned int errbits;
304 *ber = 0;
305
306
307 ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf));
308 if (ret)
309 goto error;
310
311 if ((buf[0] >> 4) & 0x01) {
312 errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 |
313 buf[2] << 8 | buf[3];
314
315 if (errbits)
316 *ber = errbits * 64 / 16588800;
317 }
318
319 return ret;
320error:
321 dbg("%s: failed:%d", __func__, ret);
322 return ret;
323}
324
325int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe,
326 u16 *strength)
327{
328 struct cxd2820r_priv *priv = fe->demodulator_priv;
329 int ret;
330 u8 buf[2];
331 u16 tmp;
332
333 ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf));
334 if (ret)
335 goto error;
336
337 tmp = (buf[0] & 0x0f) << 8 | buf[1];
338 tmp = ~tmp & 0x0fff;
339
340
341 *strength = tmp * 0xffff / 0x0fff;
342
343 return ret;
344error:
345 dbg("%s: failed:%d", __func__, ret);
346 return ret;
347}
348
349int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr)
350{
351 struct cxd2820r_priv *priv = fe->demodulator_priv;
352 int ret;
353 u8 buf[2];
354 u16 tmp;
355
356
357 ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf));
358 if (ret)
359 goto error;
360
361 tmp = (buf[0] & 0x0f) << 8 | buf[1];
362 #define CXD2820R_LOG10_8_24 15151336
363 if (tmp)
364 *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
365 / 100);
366 else
367 *snr = 0;
368
369 dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);
370
371 return ret;
372error:
373 dbg("%s: failed:%d", __func__, ret);
374 return ret;
375}
376
377int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks)
378{
379 *ucblocks = 0;
380
381 return 0;
382}
383
384int cxd2820r_sleep_t2(struct dvb_frontend *fe)
385{
386 struct cxd2820r_priv *priv = fe->demodulator_priv;
387 int ret, i;
388 struct reg_val_mask tab[] = {
389 { 0x000ff, 0x1f, 0xff },
390 { 0x00085, 0x00, 0xff },
391 { 0x00088, 0x01, 0xff },
392 { 0x02069, 0x00, 0xff },
393 { 0x00081, 0x00, 0xff },
394 { 0x00080, 0x00, 0xff },
395 };
396
397 dbg("%s", __func__);
398
399 for (i = 0; i < ARRAY_SIZE(tab); i++) {
400 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
401 tab[i].mask);
402 if (ret)
403 goto error;
404 }
405
406 priv->delivery_system = SYS_UNDEFINED;
407
408 return ret;
409error:
410 dbg("%s: failed:%d", __func__, ret);
411 return ret;
412}
413
414int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
415 struct dvb_frontend_tune_settings *s)
416{
417 s->min_delay_ms = 1500;
418 s->step_size = fe->ops.info.frequency_stepsize * 2;
419 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
420
421 return 0;
422}
423
424
