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10#include <linux/kernel.h>
11#include <linux/i2c.h>
12#include <linux/mutex.h>
13
14#include "dvb_math.h"
15#include "dvb_frontend.h"
16
17#include "dib9000.h"
18#include "dibx000_common.h"
19
20static int debug;
21module_param(debug, int, 0644);
22MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
23
24#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
25#define MAX_NUMBER_OF_FRONTENDS 6
26
27struct i2c_device {
28 struct i2c_adapter *i2c_adap;
29 u8 i2c_addr;
30 u8 *i2c_read_buffer;
31 u8 *i2c_write_buffer;
32};
33
34
35#define DIB_LOCK struct mutex
36#define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock) < 0) dprintk("could not get the lock"); } while (0)
37#define DibReleaseLock(lock) mutex_unlock(lock)
38#define DibInitLock(lock) mutex_init(lock)
39#define DibFreeLock(lock)
40
41struct dib9000_state {
42 struct i2c_device i2c;
43
44 struct dibx000_i2c_master i2c_master;
45 struct i2c_adapter tuner_adap;
46 struct i2c_adapter component_bus;
47
48 u16 revision;
49 u8 reg_offs;
50
51 enum frontend_tune_state tune_state;
52 u32 status;
53 struct dvb_frontend_parametersContext channel_status;
54
55 u8 fe_id;
56
57#define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
58 u16 gpio_dir;
59#define DIB9000_GPIO_DEFAULT_VALUES 0x0000
60 u16 gpio_val;
61#define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
62 u16 gpio_pwm_pos;
63
64 union {
65 struct {
66 u8 mobile_mode:1;
67 } host;
68
69 struct {
70 struct dib9000_fe_memory_map {
71 u16 addr;
72 u16 size;
73 } fe_mm[18];
74 u8 memcmd;
75
76 DIB_LOCK mbx_if_lock;
77 DIB_LOCK mbx_lock;
78
79 DIB_LOCK mem_lock;
80 DIB_LOCK mem_mbx_lock;
81
82#define MBX_MAX_WORDS (256 - 200 - 2)
83#define DIB9000_MSG_CACHE_SIZE 2
84 u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
85 u8 fw_is_running;
86 } risc;
87 } platform;
88
89 union {
90 struct {
91 struct dib9000_config cfg;
92 } d9;
93 } chip;
94
95 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
96 u16 component_bus_speed;
97
98
99 struct i2c_msg msg[2];
100 u8 i2c_write_buffer[255];
101 u8 i2c_read_buffer[255];
102};
103
104static const u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
105 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
106 0, 0, 0, 0, 0, 0, 0, 0
107};
108
109enum dib9000_power_mode {
110 DIB9000_POWER_ALL = 0,
111
112 DIB9000_POWER_NO,
113 DIB9000_POWER_INTERF_ANALOG_AGC,
114 DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
115 DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
116 DIB9000_POWER_INTERFACE_ONLY,
117};
118
119enum dib9000_out_messages {
120 OUT_MSG_HBM_ACK,
121 OUT_MSG_HOST_BUF_FAIL,
122 OUT_MSG_REQ_VERSION,
123 OUT_MSG_BRIDGE_I2C_W,
124 OUT_MSG_BRIDGE_I2C_R,
125 OUT_MSG_BRIDGE_APB_W,
126 OUT_MSG_BRIDGE_APB_R,
127 OUT_MSG_SCAN_CHANNEL,
128 OUT_MSG_MONIT_DEMOD,
129 OUT_MSG_CONF_GPIO,
130 OUT_MSG_DEBUG_HELP,
131 OUT_MSG_SUBBAND_SEL,
132 OUT_MSG_ENABLE_TIME_SLICE,
133 OUT_MSG_FE_FW_DL,
134 OUT_MSG_FE_CHANNEL_SEARCH,
135 OUT_MSG_FE_CHANNEL_TUNE,
136 OUT_MSG_FE_SLEEP,
137 OUT_MSG_FE_SYNC,
138 OUT_MSG_CTL_MONIT,
139
140 OUT_MSG_CONF_SVC,
141 OUT_MSG_SET_HBM,
142 OUT_MSG_INIT_DEMOD,
143 OUT_MSG_ENABLE_DIVERSITY,
144 OUT_MSG_SET_OUTPUT_MODE,
145 OUT_MSG_SET_PRIORITARY_CHANNEL,
146 OUT_MSG_ACK_FRG,
147 OUT_MSG_INIT_PMU,
148};
149
150enum dib9000_in_messages {
151 IN_MSG_DATA,
152 IN_MSG_FRAME_INFO,
153 IN_MSG_CTL_MONIT,
154 IN_MSG_ACK_FREE_ITEM,
155 IN_MSG_DEBUG_BUF,
156 IN_MSG_MPE_MONITOR,
157 IN_MSG_RAWTS_MONITOR,
158 IN_MSG_END_BRIDGE_I2C_RW,
159 IN_MSG_END_BRIDGE_APB_RW,
160 IN_MSG_VERSION,
161 IN_MSG_END_OF_SCAN,
162 IN_MSG_MONIT_DEMOD,
163 IN_MSG_ERROR,
164 IN_MSG_FE_FW_DL_DONE,
165 IN_MSG_EVENT,
166 IN_MSG_ACK_CHANGE_SVC,
167 IN_MSG_HBM_PROF,
168};
169
170
171#define FE_MM_W_CHANNEL 0
172#define FE_MM_W_FE_INFO 1
173#define FE_MM_RW_SYNC 2
174
175#define FE_SYNC_CHANNEL 1
176#define FE_SYNC_W_GENERIC_MONIT 2
177#define FE_SYNC_COMPONENT_ACCESS 3
178
179#define FE_MM_R_CHANNEL_SEARCH_STATE 3
180#define FE_MM_R_CHANNEL_UNION_CONTEXT 4
181#define FE_MM_R_FE_INFO 5
182#define FE_MM_R_FE_MONITOR 6
183
184#define FE_MM_W_CHANNEL_HEAD 7
185#define FE_MM_W_CHANNEL_UNION 8
186#define FE_MM_W_CHANNEL_CONTEXT 9
187#define FE_MM_R_CHANNEL_UNION 10
188#define FE_MM_R_CHANNEL_CONTEXT 11
189#define FE_MM_R_CHANNEL_TUNE_STATE 12
190
191#define FE_MM_R_GENERIC_MONITORING_SIZE 13
192#define FE_MM_W_GENERIC_MONITORING 14
193#define FE_MM_R_GENERIC_MONITORING 15
194
195#define FE_MM_W_COMPONENT_ACCESS 16
196#define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
197static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
198static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
199
200static u16 to_fw_output_mode(u16 mode)
201{
202 switch (mode) {
203 case OUTMODE_HIGH_Z:
204 return 0;
205 case OUTMODE_MPEG2_PAR_GATED_CLK:
206 return 4;
207 case OUTMODE_MPEG2_PAR_CONT_CLK:
208 return 8;
209 case OUTMODE_MPEG2_SERIAL:
210 return 16;
211 case OUTMODE_DIVERSITY:
212 return 128;
213 case OUTMODE_MPEG2_FIFO:
214 return 2;
215 case OUTMODE_ANALOG_ADC:
216 return 1;
217 default:
218 return 0;
219 }
220}
221
222static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute)
223{
224 u32 chunk_size = 126;
225 u32 l;
226 int ret;
227
228 if (state->platform.risc.fw_is_running && (reg < 1024))
229 return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
230
231 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
232 state->msg[0].addr = state->i2c.i2c_addr >> 1;
233 state->msg[0].flags = 0;
234 state->msg[0].buf = state->i2c_write_buffer;
235 state->msg[0].len = 2;
236 state->msg[1].addr = state->i2c.i2c_addr >> 1;
237 state->msg[1].flags = I2C_M_RD;
238 state->msg[1].buf = b;
239 state->msg[1].len = len;
240
241 state->i2c_write_buffer[0] = reg >> 8;
242 state->i2c_write_buffer[1] = reg & 0xff;
243
244 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
245 state->i2c_write_buffer[0] |= (1 << 5);
246 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
247 state->i2c_write_buffer[0] |= (1 << 4);
248
249 do {
250 l = len < chunk_size ? len : chunk_size;
251 state->msg[1].len = l;
252 state->msg[1].buf = b;
253 ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 2) != 2 ? -EREMOTEIO : 0;
254 if (ret != 0) {
255 dprintk("i2c read error on %d", reg);
256 return -EREMOTEIO;
257 }
258
259 b += l;
260 len -= l;
261
262 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
263 reg += l / 2;
264 } while ((ret == 0) && len);
265
266 return 0;
267}
268
269static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
270{
271 struct i2c_msg msg[2] = {
272 {.addr = i2c->i2c_addr >> 1, .flags = 0,
273 .buf = i2c->i2c_write_buffer, .len = 2},
274 {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD,
275 .buf = i2c->i2c_read_buffer, .len = 2},
276 };
277
278 i2c->i2c_write_buffer[0] = reg >> 8;
279 i2c->i2c_write_buffer[1] = reg & 0xff;
280
281 if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
282 dprintk("read register %x error", reg);
283 return 0;
284 }
285
286 return (i2c->i2c_read_buffer[0] << 8) | i2c->i2c_read_buffer[1];
287}
288
289static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
290{
291 if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0)
292 return 0;
293 return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
294}
295
296static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
297{
298 if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2,
299 attribute) != 0)
300 return 0;
301 return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
302}
303
304#define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
305
306static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
307{
308 u32 chunk_size = 126;
309 u32 l;
310 int ret;
311
312 if (state->platform.risc.fw_is_running && (reg < 1024)) {
313 if (dib9000_risc_apb_access_write
314 (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
315 return -EINVAL;
316 return 0;
317 }
318
319 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
320 state->msg[0].addr = state->i2c.i2c_addr >> 1;
321 state->msg[0].flags = 0;
322 state->msg[0].buf = state->i2c_write_buffer;
323 state->msg[0].len = len + 2;
324
325 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
326 state->i2c_write_buffer[1] = (reg) & 0xff;
327
328 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
329 state->i2c_write_buffer[0] |= (1 << 5);
330 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
331 state->i2c_write_buffer[0] |= (1 << 4);
332
333 do {
334 l = len < chunk_size ? len : chunk_size;
335 state->msg[0].len = l + 2;
336 memcpy(&state->i2c_write_buffer[2], buf, l);
337
338 ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
339
340 buf += l;
341 len -= l;
342
343 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
344 reg += l / 2;
345 } while ((ret == 0) && len);
346
347 return ret;
348}
349
350static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
351{
352 struct i2c_msg msg = {
353 .addr = i2c->i2c_addr >> 1, .flags = 0,
354 .buf = i2c->i2c_write_buffer, .len = 4
355 };
356
357 i2c->i2c_write_buffer[0] = (reg >> 8) & 0xff;
358 i2c->i2c_write_buffer[1] = reg & 0xff;
359 i2c->i2c_write_buffer[2] = (val >> 8) & 0xff;
360 i2c->i2c_write_buffer[3] = val & 0xff;
361
362 return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
363}
364
365static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
366{
367 u8 b[2] = { val >> 8, val & 0xff };
368 return dib9000_write16_attr(state, reg, b, 2, 0);
369}
370
371static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
372{
373 u8 b[2] = { val >> 8, val & 0xff };
374 return dib9000_write16_attr(state, reg, b, 2, attribute);
375}
376
377#define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
378#define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
379#define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
380
381#define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
382#define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
383
384#define MAC_IRQ (1 << 1)
385#define IRQ_POL_MSK (1 << 4)
386
387#define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
388#define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
389
390static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
391{
392 u8 b[14] = { 0 };
393
394
395
396 b[1] = 1;
397
398
399
400 b[4] = (u8) (addr >> 8);
401 b[5] = (u8) (addr & 0xff);
402
403
404
405 b[12] = (u8) (addr >> 8);
406 b[13] = (u8) (addr & 0xff);
407
408 addr += len;
409
410
411 b[8] = (u8) (addr >> 8);
412 b[9] = (u8) (addr & 0xff);
413
414 dib9000_write(state, 1056, b, 14);
415 if (reading)
416 dib9000_write_word(state, 1056, (1 << 15) | 1);
417 state->platform.risc.memcmd = -1;
418}
419
420static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
421{
422 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
423
424 if (state->platform.risc.memcmd == cmd &&
425 !(cmd & 0x80 && m->size < 67))
426 return;
427 dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
428 state->platform.risc.memcmd = cmd;
429}
430
431static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
432{
433 if (!state->platform.risc.fw_is_running)
434 return -EIO;
435
436 DibAcquireLock(&state->platform.risc.mem_lock);
437 dib9000_risc_mem_setup(state, cmd | 0x80);
438 dib9000_risc_mem_read_chunks(state, b, len);
439 DibReleaseLock(&state->platform.risc.mem_lock);
440 return 0;
441}
442
443static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
444{
445 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
446 if (!state->platform.risc.fw_is_running)
447 return -EIO;
448
449 DibAcquireLock(&state->platform.risc.mem_lock);
450 dib9000_risc_mem_setup(state, cmd);
451 dib9000_risc_mem_write_chunks(state, b, m->size);
452 DibReleaseLock(&state->platform.risc.mem_lock);
453 return 0;
454}
455
456static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
457{
458 u16 offs;
459
460 if (risc_id == 1)
461 offs = 16;
462 else
463 offs = 0;
464
465
466 dib9000_write_word(state, 1024 + offs, 0x000f);
467 dib9000_write_word(state, 1025 + offs, 0);
468 dib9000_write_word(state, 1031 + offs, key);
469
470 dprintk("going to download %dB of microcode", len);
471 if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
472 dprintk("error while downloading microcode for RISC %c", 'A' + risc_id);
473 return -EIO;
474 }
475
476 dprintk("Microcode for RISC %c loaded", 'A' + risc_id);
477
478 return 0;
479}
480
481static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
482{
483 u16 mbox_offs;
484 u16 reset_reg;
485 u16 tries = 1000;
486
487 if (risc_id == 1)
488 mbox_offs = 16;
489 else
490 mbox_offs = 0;
491
492
493 dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
494
495
496 do {
497 reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
498 msleep(100);
499 } while ((reset_reg & 0x8000) && --tries);
500
501 if (reset_reg & 0x8000) {
502 dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id);
503 return -EIO;
504 }
505 dprintk("MBX: initialized");
506 return 0;
507}
508
509#define MAX_MAILBOX_TRY 100
510static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
511{
512 u8 *d, b[2];
513 u16 tmp;
514 u16 size;
515 u32 i;
516 int ret = 0;
517
518 if (!state->platform.risc.fw_is_running)
519 return -EINVAL;
520
521 DibAcquireLock(&state->platform.risc.mbx_if_lock);
522 tmp = MAX_MAILBOX_TRY;
523 do {
524 size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
525 if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
526 dprintk("MBX: RISC mbx full, retrying");
527 msleep(100);
528 } else
529 break;
530 } while (1);
531
532
533
534 if (tmp == 0) {
535 ret = -EINVAL;
536 goto out;
537 }
538#ifdef DUMP_MSG
539 dprintk("--> %02x %d ", id, len + 1);
540 for (i = 0; i < len; i++)
541 dprintk("%04x ", data[i]);
542 dprintk("\n");
543#endif
544
545
546 d = (u8 *) data;
547 for (i = 0; i < len; i++) {
548 tmp = data[i];
549 *d++ = tmp >> 8;
550 *d++ = tmp & 0xff;
551 }
552
553
554 b[0] = id;
555 b[1] = len + 1;
556 if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
557 ret = -EIO;
558 goto out;
559 }
560
561
562 ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
563
564out:
565 DibReleaseLock(&state->platform.risc.mbx_if_lock);
566
567 return ret;
568}
569
570static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
571{
572#ifdef DUMP_MSG
573 u16 *d = data;
574#endif
575
576 u16 tmp, i;
577 u8 size;
578 u8 mc_base;
579
580 if (!state->platform.risc.fw_is_running)
581 return 0;
582
583 DibAcquireLock(&state->platform.risc.mbx_if_lock);
584 if (risc_id == 1)
585 mc_base = 16;
586 else
587 mc_base = 0;
588
589
590 *data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
591
592 size = *data & 0xff;
593 if (size <= MBX_MAX_WORDS) {
594 data++;
595 size--;
596
597 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
598
599
600 for (i = 0; i < size; i++) {
601 tmp = *data;
602 *data = (tmp >> 8) | (tmp << 8);
603 data++;
604 }
605
606#ifdef DUMP_MSG
607 dprintk("<-- ");
608 for (i = 0; i < size + 1; i++)
609 dprintk("%04x ", d[i]);
610 dprintk("\n");
611#endif
612 } else {
613 dprintk("MBX: message is too big for message cache (%d), flushing message", size);
614 size--;
615 while (size--)
616 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
617 }
618
619 dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
620
621 DibReleaseLock(&state->platform.risc.mbx_if_lock);
622
623 return size + 1;
624}
625
626static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
627{
628 u32 ts = data[1] << 16 | data[0];
629 char *b = (char *)&data[2];
630
631 b[2 * (size - 2) - 1] = '\0';
632 if (*b == '~') {
633 b++;
634 dprintk(b);
635 } else
636 dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<emtpy>");
637 return 1;
638}
639
640static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
641{
642 int i;
643 u8 size;
644 u16 *block;
645
646 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
647 block = state->platform.risc.message_cache[i];
648 if (*block == 0) {
649 size = dib9000_mbx_read(state, block, 1, attr);
650
651
652
653 switch (*block >> 8) {
654 case IN_MSG_DEBUG_BUF:
655 dib9000_risc_debug_buf(state, block + 1, size);
656 *block = 0;
657 break;
658#if 0
659 case IN_MSG_DATA:
660 dib9000_risc_data_process(state, block + 1, size);
661 *block = 0;
662 break;
663#endif
664 default:
665 break;
666 }
667
668 return 1;
669 }
670 }
671 dprintk("MBX: no free cache-slot found for new message...");
672 return -1;
673}
674
675static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
676{
677 if (risc_id == 0)
678 return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f;
679 else
680 return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f;
681}
682
683static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
684{
685 int ret = 0;
686 u16 tmp;
687
688 if (!state->platform.risc.fw_is_running)
689 return -1;
690
691 DibAcquireLock(&state->platform.risc.mbx_lock);
692
693 if (dib9000_mbx_count(state, 1, attr))
694 ret = dib9000_mbx_fetch_to_cache(state, attr);
695
696 tmp = dib9000_read_word_attr(state, 1229, attr);
697
698
699 DibReleaseLock(&state->platform.risc.mbx_lock);
700
701 return ret;
702}
703
704static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
705{
706 u8 i;
707 u16 *block;
708 u16 timeout = 30;
709
710 *msg = 0;
711 do {
712
713 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
714 block = state->platform.risc.message_cache[i];
715 if ((*block >> 8) == id) {
716 *size = (*block & 0xff) - 1;
717 memcpy(msg, block + 1, (*size) * 2);
718 *block = 0;
719 i = 0;
720 break;
721 }
722 }
723
724 if (i == 0)
725 break;
726
727 if (dib9000_mbx_process(state, attr) == -1)
728 return -1;
729
730 } while (--timeout);
731
732 if (timeout == 0) {
733 dprintk("waiting for message %d timed out", id);
734 return -1;
735 }
736
737 return i == 0;
738}
739
740static int dib9000_risc_check_version(struct dib9000_state *state)
741{
742 u8 r[4];
743 u8 size;
744 u16 fw_version = 0;
745
746 if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
747 return -EIO;
748
749 if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
750 return -EIO;
751
752 fw_version = (r[0] << 8) | r[1];
753 dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
754
755 if ((fw_version >> 10) != 7)
756 return -EINVAL;
757
758 switch (fw_version & 0x3ff) {
759 case 11:
760 case 12:
761 case 14:
762 case 15:
763 case 16:
764 case 17:
765 break;
766 default:
767 dprintk("RISC: invalid firmware version");
768 return -EINVAL;
769 }
770
771 dprintk("RISC: valid firmware version");
772 return 0;
773}
774
775static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
776{
777
778 dib9000_write_word(state, 1225, 0x02);
779 dib9000_write_word(state, 1226, 0x05);
780
781
782 dib9000_write_word(state, 1542, 1);
783
784
785 dib9000_write_word(state, 1074, 0);
786 dib9000_write_word(state, 1075, 0);
787
788
789 dib9000_write_word(state, 1237, 0);
790
791
792 if (codeA != NULL)
793 dib9000_write_word(state, 1024, 2);
794 else
795 dib9000_write_word(state, 1024, 15);
796 if (codeB != NULL)
797 dib9000_write_word(state, 1040, 2);
798
799 if (codeA != NULL)
800 dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
801 if (codeB != NULL)
802 dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
803
804
805 if (codeA != NULL)
806 dib9000_write_word(state, 1024, 0);
807 if (codeB != NULL)
808 dib9000_write_word(state, 1040, 0);
809
810 if (codeA != NULL)
811 if (dib9000_mbx_host_init(state, 0) != 0)
812 return -EIO;
813 if (codeB != NULL)
814 if (dib9000_mbx_host_init(state, 1) != 0)
815 return -EIO;
816
817 msleep(100);
818 state->platform.risc.fw_is_running = 1;
819
820 if (dib9000_risc_check_version(state) != 0)
821 return -EINVAL;
822
823 state->platform.risc.memcmd = 0xff;
824 return 0;
825}
826
827static u16 dib9000_identify(struct i2c_device *client)
828{
829 u16 value;
830
831 value = dib9000_i2c_read16(client, 896);
832 if (value != 0x01b3) {
833 dprintk("wrong Vendor ID (0x%x)", value);
834 return 0;
835 }
836
837 value = dib9000_i2c_read16(client, 897);
838 if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
839 dprintk("wrong Device ID (0x%x)", value);
840 return 0;
841 }
842
843
844 if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
845 dprintk("this driver does not work with DiB7000PC");
846 return 0;
847 }
848
849 switch (value) {
850 case 0x4000:
851 dprintk("found DiB7000MA/PA/MB/PB");
852 break;
853 case 0x4001:
854 dprintk("found DiB7000HC");
855 break;
856 case 0x4002:
857 dprintk("found DiB7000MC");
858 break;
859 case 0x4003:
860 dprintk("found DiB9000A");
861 break;
862 case 0x4004:
863 dprintk("found DiB9000H");
864 break;
865 case 0x4005:
866 dprintk("found DiB9000M");
867 break;
868 }
869
870 return value;
871}
872
873static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
874{
875
876 u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
877 u8 offset;
878
879 if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
880 offset = 1;
881 else
882 offset = 0;
883
884 reg_906 = dib9000_read_word(state, 906 + offset) | 0x3;
885
886
887 switch (mode) {
888
889 case DIB9000_POWER_ALL:
890 reg_903 = 0x0000;
891 reg_904 = 0x0000;
892 reg_905 = 0x0000;
893 reg_906 = 0x0000;
894 break;
895
896
897 case DIB9000_POWER_INTERFACE_ONLY:
898 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
899 break;
900
901 case DIB9000_POWER_INTERF_ANALOG_AGC:
902 reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
903 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
904 reg_906 &= ~((1 << 0));
905 break;
906
907 case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
908 reg_903 = 0x0000;
909 reg_904 = 0x801f;
910 reg_905 = 0x0000;
911 reg_906 &= ~((1 << 0));
912 break;
913
914 case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
915 reg_903 = 0x0000;
916 reg_904 = 0x8000;
917 reg_905 = 0x010b;
918 reg_906 &= ~((1 << 0));
919 break;
920 default:
921 case DIB9000_POWER_NO:
922 break;
923 }
924
925
926 if (!state->platform.host.mobile_mode)
927 reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
928
929
930 if (state->revision != 0x4000)
931 reg_906 <<= 1;
932
933 dib9000_write_word(state, 903 + offset, reg_903);
934 dib9000_write_word(state, 904 + offset, reg_904);
935 dib9000_write_word(state, 905 + offset, reg_905);
936 dib9000_write_word(state, 906 + offset, reg_906);
937}
938
939static int dib9000_fw_reset(struct dvb_frontend *fe)
940{
941 struct dib9000_state *state = fe->demodulator_priv;
942
943 dib9000_write_word(state, 1817, 0x0003);
944
945 dib9000_write_word(state, 1227, 1);
946 dib9000_write_word(state, 1227, 0);
947
948 switch ((state->revision = dib9000_identify(&state->i2c))) {
949 case 0x4003:
950 case 0x4004:
951 case 0x4005:
952 state->reg_offs = 1;
953 break;
954 default:
955 return -EINVAL;
956 }
957
958
959 dibx000_reset_i2c_master(&state->i2c_master);
960
961 dib9000_set_power_mode(state, DIB9000_POWER_ALL);
962
963
964 dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
965 dib9000_write_word(state, 1796, 0);
966 dib9000_write_word(state, 1805, 0x805);
967
968
969 dib9000_write_word(state, 898, 0xffff);
970 dib9000_write_word(state, 899, 0xffff);
971 dib9000_write_word(state, 900, 0x0001);
972 dib9000_write_word(state, 901, 0xff19);
973 dib9000_write_word(state, 902, 0x003c);
974
975 dib9000_write_word(state, 898, 0);
976 dib9000_write_word(state, 899, 0);
977 dib9000_write_word(state, 900, 0);
978 dib9000_write_word(state, 901, 0);
979 dib9000_write_word(state, 902, 0);
980
981 dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
982
983 dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
984
985 return 0;
986}
987
988static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
989{
990 u16 mb[10];
991 u8 i, s;
992
993 if (address >= 1024 || !state->platform.risc.fw_is_running)
994 return -EINVAL;
995
996
997
998 mb[0] = (u16) address;
999 mb[1] = len / 2;
1000 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
1001 switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
1002 case 1:
1003 s--;
1004 for (i = 0; i < s; i++) {
1005 b[i * 2] = (mb[i + 1] >> 8) & 0xff;
1006 b[i * 2 + 1] = (mb[i + 1]) & 0xff;
1007 }
1008 return 0;
1009 default:
1010 return -EIO;
1011 }
1012 return -EIO;
1013}
1014
1015static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
1016{
1017 u16 mb[10];
1018 u8 s, i;
1019
1020 if (address >= 1024 || !state->platform.risc.fw_is_running)
1021 return -EINVAL;
1022
1023
1024
1025 mb[0] = (unsigned short)address;
1026 for (i = 0; i < len && i < 20; i += 2)
1027 mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
1028
1029 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
1030 return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
1031}
1032
1033static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
1034{
1035 u8 index_loop = 10;
1036
1037 if (!state->platform.risc.fw_is_running)
1038 return 0;
1039 dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
1040 do {
1041 dib9000_risc_mem_read(state, FE_MM_RW_SYNC, state->i2c_read_buffer, 1);
1042 } while (state->i2c_read_buffer[0] && index_loop--);
1043
1044 if (index_loop > 0)
1045 return 0;
1046 return -EIO;
1047}
1048
1049static int dib9000_fw_init(struct dib9000_state *state)
1050{
1051 struct dibGPIOFunction *f;
1052 u16 b[40] = { 0 };
1053 u8 i;
1054 u8 size;
1055
1056 if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
1057 return -EIO;
1058
1059
1060 for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
1061 f = &state->chip.d9.cfg.gpio_function[i];
1062 if (f->mask) {
1063 switch (f->function) {
1064 case BOARD_GPIO_FUNCTION_COMPONENT_ON:
1065 b[0] = (u16) f->mask;
1066 b[1] = (u16) f->direction;
1067 b[2] = (u16) f->value;
1068 break;
1069 case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
1070 b[3] = (u16) f->mask;
1071 b[4] = (u16) f->direction;
1072 b[5] = (u16) f->value;
1073 break;
1074 }
1075 }
1076 }
1077 if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
1078 return -EIO;
1079
1080
1081 b[0] = state->chip.d9.cfg.subband.size;
1082 for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
1083 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
1084 b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
1085 b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
1086 b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
1087 }
1088 b[1 + i * 4] = 0;
1089 if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
1090 return -EIO;
1091
1092
1093 b[0] = (0 << 8) | 1;
1094
1095 b[1] = (0 << 8) | (0);
1096 b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
1097 b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
1098 b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
1099 b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
1100 b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
1101 b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
1102 b[29] = state->chip.d9.cfg.if_drives;
1103 if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
1104 return -EIO;
1105
1106 if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
1107 return -EIO;
1108
1109 if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
1110 return -EIO;
1111
1112 if (size > ARRAY_SIZE(b)) {
1113 dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
1114 (int)ARRAY_SIZE(b));
1115 return -EINVAL;
1116 }
1117
1118 for (i = 0; i < size; i += 2) {
1119 state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
1120 state->platform.risc.fe_mm[i / 2].size = b[i + 1];
1121 }
1122
1123 return 0;
1124}
1125
1126static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_frontend_parameters *ch)
1127{
1128 u8 b[9];
1129 u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
1130 if (state->fe_id % 2)
1131 freq += 101;
1132
1133 b[0] = (u8) ((freq >> 0) & 0xff);
1134 b[1] = (u8) ((freq >> 8) & 0xff);
1135 b[2] = (u8) ((freq >> 16) & 0xff);
1136 b[3] = (u8) ((freq >> 24) & 0xff);
1137 b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
1138 b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
1139 b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
1140 b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
1141 b[8] = 0x80;
1142 if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
1143 b[8] |= 1;
1144 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
1145}
1146
1147static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1148{
1149 struct dib9000_state *state = fe->demodulator_priv;
1150 struct dibDVBTChannel {
1151 s8 spectrum_inversion;
1152
1153 s8 nfft;
1154 s8 guard;
1155 s8 constellation;
1156
1157 s8 hrch;
1158 s8 alpha;
1159 s8 code_rate_hp;
1160 s8 code_rate_lp;
1161 s8 select_hp;
1162
1163 s8 intlv_native;
1164 };
1165 struct dibDVBTChannel *ch;
1166 int ret = 0;
1167
1168 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1169 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
1170 goto error;
1171 ret = -EIO;
1172 }
1173
1174 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION,
1175 state->i2c_read_buffer, sizeof(struct dibDVBTChannel));
1176 ch = (struct dibDVBTChannel *)state->i2c_read_buffer;
1177
1178
1179 switch (ch->spectrum_inversion & 0x7) {
1180 case 1:
1181 state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
1182 break;
1183 case 0:
1184 state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
1185 break;
1186 default:
1187 case -1:
1188 state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
1189 break;
1190 }
1191 switch (ch->nfft) {
1192 case 0:
1193 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
1194 break;
1195 case 2:
1196 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
1197 break;
1198 case 1:
1199 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1200 break;
1201 default:
1202 case -1:
1203 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
1204 break;
1205 }
1206 switch (ch->guard) {
1207 case 0:
1208 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
1209 break;
1210 case 1:
1211 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
1212 break;
1213 case 2:
1214 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1215 break;
1216 case 3:
1217 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
1218 break;
1219 default:
1220 case -1:
1221 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
1222 break;
1223 }
1224 switch (ch->constellation) {
1225 case 2:
1226 state->fe[0]->dtv_property_cache.modulation = QAM_64;
1227 break;
1228 case 1:
1229 state->fe[0]->dtv_property_cache.modulation = QAM_16;
1230 break;
1231 case 0:
1232 state->fe[0]->dtv_property_cache.modulation = QPSK;
1233 break;
1234 default:
1235 case -1:
1236 state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
1237 break;
1238 }
1239 switch (ch->hrch) {
1240 case 0:
1241 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
1242 break;
1243 case 1:
1244 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
1245 break;
1246 default:
1247 case -1:
1248 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
1249 break;
1250 }
1251 switch (ch->code_rate_hp) {
1252 case 1:
1253 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
1254 break;
1255 case 2:
1256 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
1257 break;
1258 case 3:
1259 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
1260 break;
1261 case 5:
1262 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
1263 break;
1264 case 7:
1265 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
1266 break;
1267 default:
1268 case -1:
1269 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
1270 break;
1271 }
1272 switch (ch->code_rate_lp) {
1273 case 1:
1274 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
1275 break;
1276 case 2:
1277 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
1278 break;
1279 case 3:
1280 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
1281 break;
1282 case 5:
1283 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
1284 break;
1285 case 7:
1286 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
1287 break;
1288 default:
1289 case -1:
1290 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
1291 break;
1292 }
1293
1294error:
1295 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1296 return ret;
1297}
1298
1299static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1300{
1301 struct dib9000_state *state = fe->demodulator_priv;
1302 struct dibDVBTChannel {
1303 s8 spectrum_inversion;
1304
1305 s8 nfft;
1306 s8 guard;
1307 s8 constellation;
1308
1309 s8 hrch;
1310 s8 alpha;
1311 s8 code_rate_hp;
1312 s8 code_rate_lp;
1313 s8 select_hp;
1314
1315 s8 intlv_native;
1316 };
1317 struct dibDVBTChannel ch;
1318
1319 switch (state->fe[0]->dtv_property_cache.inversion) {
1320 case INVERSION_ON:
1321 ch.spectrum_inversion = 1;
1322 break;
1323 case INVERSION_OFF:
1324 ch.spectrum_inversion = 0;
1325 break;
1326 default:
1327 case INVERSION_AUTO:
1328 ch.spectrum_inversion = -1;
1329 break;
1330 }
1331 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1332 case TRANSMISSION_MODE_2K:
1333 ch.nfft = 0;
1334 break;
1335 case TRANSMISSION_MODE_4K:
1336 ch.nfft = 2;
1337 break;
1338 case TRANSMISSION_MODE_8K:
1339 ch.nfft = 1;
1340 break;
1341 default:
1342 case TRANSMISSION_MODE_AUTO:
1343 ch.nfft = 1;
1344 break;
1345 }
1346 switch (state->fe[0]->dtv_property_cache.guard_interval) {
1347 case GUARD_INTERVAL_1_32:
1348 ch.guard = 0;
1349 break;
1350 case GUARD_INTERVAL_1_16:
1351 ch.guard = 1;
1352 break;
1353 case GUARD_INTERVAL_1_8:
1354 ch.guard = 2;
1355 break;
1356 case GUARD_INTERVAL_1_4:
1357 ch.guard = 3;
1358 break;
1359 default:
1360 case GUARD_INTERVAL_AUTO:
1361 ch.guard = -1;
1362 break;
1363 }
1364 switch (state->fe[0]->dtv_property_cache.modulation) {
1365 case QAM_64:
1366 ch.constellation = 2;
1367 break;
1368 case QAM_16:
1369 ch.constellation = 1;
1370 break;
1371 case QPSK:
1372 ch.constellation = 0;
1373 break;
1374 default:
1375 case QAM_AUTO:
1376 ch.constellation = -1;
1377 break;
1378 }
1379 switch (state->fe[0]->dtv_property_cache.hierarchy) {
1380 case HIERARCHY_NONE:
1381 ch.hrch = 0;
1382 break;
1383 case HIERARCHY_1:
1384 case HIERARCHY_2:
1385 case HIERARCHY_4:
1386 ch.hrch = 1;
1387 break;
1388 default:
1389 case HIERARCHY_AUTO:
1390 ch.hrch = -1;
1391 break;
1392 }
1393 ch.alpha = 1;
1394 switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
1395 case FEC_1_2:
1396 ch.code_rate_hp = 1;
1397 break;
1398 case FEC_2_3:
1399 ch.code_rate_hp = 2;
1400 break;
1401 case FEC_3_4:
1402 ch.code_rate_hp = 3;
1403 break;
1404 case FEC_5_6:
1405 ch.code_rate_hp = 5;
1406 break;
1407 case FEC_7_8:
1408 ch.code_rate_hp = 7;
1409 break;
1410 default:
1411 case FEC_AUTO:
1412 ch.code_rate_hp = -1;
1413 break;
1414 }
1415 switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
1416 case FEC_1_2:
1417 ch.code_rate_lp = 1;
1418 break;
1419 case FEC_2_3:
1420 ch.code_rate_lp = 2;
1421 break;
1422 case FEC_3_4:
1423 ch.code_rate_lp = 3;
1424 break;
1425 case FEC_5_6:
1426 ch.code_rate_lp = 5;
1427 break;
1428 case FEC_7_8:
1429 ch.code_rate_lp = 7;
1430 break;
1431 default:
1432 case FEC_AUTO:
1433 ch.code_rate_lp = -1;
1434 break;
1435 }
1436 ch.select_hp = 1;
1437 ch.intlv_native = 1;
1438
1439 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
1440
1441 return 0;
1442}
1443
1444static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
1445{
1446 struct dib9000_state *state = fe->demodulator_priv;
1447 int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1448 s8 i;
1449
1450 switch (state->tune_state) {
1451 case CT_DEMOD_START:
1452 dib9000_fw_set_channel_head(state, ch);
1453
1454
1455 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
1456 dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
1457
1458 if (search)
1459 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
1460 else {
1461 dib9000_fw_set_channel_union(fe, ch);
1462 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
1463 }
1464 state->tune_state = CT_DEMOD_STEP_1;
1465 break;
1466 case CT_DEMOD_STEP_1:
1467 if (search)
1468 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, state->i2c_read_buffer, 1);
1469 else
1470 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, state->i2c_read_buffer, 1);
1471 i = (s8)state->i2c_read_buffer[0];
1472 switch (i) {
1473 case 0:
1474 break;
1475 case -2:
1476 if (search)
1477 state->status = FE_STATUS_DEMOD_SUCCESS;
1478 else {
1479 state->tune_state = CT_DEMOD_STOP;
1480 state->status = FE_STATUS_LOCKED;
1481 }
1482 break;
1483 default:
1484 state->status = FE_STATUS_TUNE_FAILED;
1485 state->tune_state = CT_DEMOD_STOP;
1486 break;
1487 }
1488 break;
1489 default:
1490 ret = FE_CALLBACK_TIME_NEVER;
1491 break;
1492 }
1493
1494 return ret;
1495}
1496
1497static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
1498{
1499 struct dib9000_state *state = fe->demodulator_priv;
1500 u16 mode = (u16) onoff;
1501 return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
1502}
1503
1504static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
1505{
1506 struct dib9000_state *state = fe->demodulator_priv;
1507 u16 outreg, smo_mode;
1508
1509 dprintk("setting output mode for demod %p to %d", fe, mode);
1510
1511 switch (mode) {
1512 case OUTMODE_MPEG2_PAR_GATED_CLK:
1513 outreg = (1 << 10);
1514 break;
1515 case OUTMODE_MPEG2_PAR_CONT_CLK:
1516 outreg = (1 << 10) | (1 << 6);
1517 break;
1518 case OUTMODE_MPEG2_SERIAL:
1519 outreg = (1 << 10) | (2 << 6) | (0 << 1);
1520 break;
1521 case OUTMODE_DIVERSITY:
1522 outreg = (1 << 10) | (4 << 6);
1523 break;
1524 case OUTMODE_MPEG2_FIFO:
1525 outreg = (1 << 10) | (5 << 6);
1526 break;
1527 case OUTMODE_HIGH_Z:
1528 outreg = 0;
1529 break;
1530 default:
1531 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
1532 return -EINVAL;
1533 }
1534
1535 dib9000_write_word(state, 1795, outreg);
1536
1537 switch (mode) {
1538 case OUTMODE_MPEG2_PAR_GATED_CLK:
1539 case OUTMODE_MPEG2_PAR_CONT_CLK:
1540 case OUTMODE_MPEG2_SERIAL:
1541 case OUTMODE_MPEG2_FIFO:
1542 smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
1543 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
1544 smo_mode |= (1 << 5);
1545 dib9000_write_word(state, 295, smo_mode);
1546 break;
1547 }
1548
1549 outreg = to_fw_output_mode(mode);
1550 return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
1551}
1552
1553static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1554{
1555 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1556 u16 i, len, t, index_msg;
1557
1558 for (index_msg = 0; index_msg < num; index_msg++) {
1559 if (msg[index_msg].flags & I2C_M_RD) {
1560 len = msg[index_msg].len;
1561 if (len > 16)
1562 len = 16;
1563
1564 if (dib9000_read_word(state, 790) != 0)
1565 dprintk("TunerITF: read busy");
1566
1567 dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
1568 dib9000_write_word(state, 787, (len / 2) - 1);
1569 dib9000_write_word(state, 786, 1);
1570
1571 i = 1000;
1572 while (dib9000_read_word(state, 790) != (len / 2) && i)
1573 i--;
1574
1575 if (i == 0)
1576 dprintk("TunerITF: read failed");
1577
1578 for (i = 0; i < len; i += 2) {
1579 t = dib9000_read_word(state, 785);
1580 msg[index_msg].buf[i] = (t >> 8) & 0xff;
1581 msg[index_msg].buf[i + 1] = (t) & 0xff;
1582 }
1583 if (dib9000_read_word(state, 790) != 0)
1584 dprintk("TunerITF: read more data than expected");
1585 } else {
1586 i = 1000;
1587 while (dib9000_read_word(state, 789) && i)
1588 i--;
1589 if (i == 0)
1590 dprintk("TunerITF: write busy");
1591
1592 len = msg[index_msg].len;
1593 if (len > 16)
1594 len = 16;
1595
1596 for (i = 0; i < len; i += 2)
1597 dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
1598 dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
1599 dib9000_write_word(state, 787, (len / 2) - 1);
1600 dib9000_write_word(state, 786, 0);
1601
1602 i = 1000;
1603 while (dib9000_read_word(state, 791) > 0 && i)
1604 i--;
1605 if (i == 0)
1606 dprintk("TunerITF: write failed");
1607 }
1608 }
1609 return num;
1610}
1611
1612int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
1613{
1614 struct dib9000_state *state = fe->demodulator_priv;
1615
1616 state->component_bus_speed = speed;
1617 return 0;
1618}
1619EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
1620
1621static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1622{
1623 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1624 u8 type = 0;
1625 u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
1626 u16 scl = state->component_bus_speed;
1627 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
1628 u8 p[13] = { 0 };
1629
1630 p[0] = type;
1631 p[1] = port;
1632 p[2] = msg[0].addr << 1;
1633
1634 p[3] = (u8) scl & 0xff;
1635 p[4] = (u8) (scl >> 8);
1636
1637 p[7] = 0;
1638 p[8] = 0;
1639
1640 p[9] = (u8) (msg[0].len);
1641 p[10] = (u8) (msg[0].len >> 8);
1642 if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
1643 p[11] = (u8) (msg[1].len);
1644 p[12] = (u8) (msg[1].len >> 8);
1645 } else {
1646 p[11] = 0;
1647 p[12] = 0;
1648 }
1649
1650 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1651
1652 dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
1653
1654 {
1655 dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
1656 dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
1657 }
1658
1659
1660 if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
1661 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1662 return 0;
1663 }
1664
1665
1666 if ((num > 1) && (msg[1].flags & I2C_M_RD))
1667 dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
1668
1669 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1670
1671 return num;
1672}
1673
1674static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
1675{
1676 return I2C_FUNC_I2C;
1677}
1678
1679static struct i2c_algorithm dib9000_tuner_algo = {
1680 .master_xfer = dib9000_tuner_xfer,
1681 .functionality = dib9000_i2c_func,
1682};
1683
1684static struct i2c_algorithm dib9000_component_bus_algo = {
1685 .master_xfer = dib9000_fw_component_bus_xfer,
1686 .functionality = dib9000_i2c_func,
1687};
1688
1689struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
1690{
1691 struct dib9000_state *st = fe->demodulator_priv;
1692 return &st->tuner_adap;
1693}
1694EXPORT_SYMBOL(dib9000_get_tuner_interface);
1695
1696struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
1697{
1698 struct dib9000_state *st = fe->demodulator_priv;
1699 return &st->component_bus;
1700}
1701EXPORT_SYMBOL(dib9000_get_component_bus_interface);
1702
1703struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
1704{
1705 struct dib9000_state *st = fe->demodulator_priv;
1706 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
1707}
1708EXPORT_SYMBOL(dib9000_get_i2c_master);
1709
1710int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
1711{
1712 struct dib9000_state *st = fe->demodulator_priv;
1713
1714 st->i2c.i2c_adap = i2c;
1715 return 0;
1716}
1717EXPORT_SYMBOL(dib9000_set_i2c_adapter);
1718
1719static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
1720{
1721 st->gpio_dir = dib9000_read_word(st, 773);
1722 st->gpio_dir &= ~(1 << num);
1723 st->gpio_dir |= (dir & 0x1) << num;
1724 dib9000_write_word(st, 773, st->gpio_dir);
1725
1726 st->gpio_val = dib9000_read_word(st, 774);
1727 st->gpio_val &= ~(1 << num);
1728 st->gpio_val |= (val & 0x01) << num;
1729 dib9000_write_word(st, 774, st->gpio_val);
1730
1731 dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val);
1732
1733 return 0;
1734}
1735
1736int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
1737{
1738 struct dib9000_state *state = fe->demodulator_priv;
1739 return dib9000_cfg_gpio(state, num, dir, val);
1740}
1741EXPORT_SYMBOL(dib9000_set_gpio);
1742
1743int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1744{
1745 struct dib9000_state *state = fe->demodulator_priv;
1746 u16 val = dib9000_read_word(state, 294 + 1) & 0xffef;
1747 val |= (onoff & 0x1) << 4;
1748
1749 dprintk("PID filter enabled %d", onoff);
1750 return dib9000_write_word(state, 294 + 1, val);
1751}
1752EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
1753
1754int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1755{
1756 struct dib9000_state *state = fe->demodulator_priv;
1757 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
1758 return dib9000_write_word(state, 300 + 1 + id, onoff ? (1 << 13) | pid : 0);
1759}
1760EXPORT_SYMBOL(dib9000_fw_pid_filter);
1761
1762int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
1763{
1764 struct dib9000_state *state = fe->demodulator_priv;
1765 return dib9000_fw_init(state);
1766}
1767EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
1768
1769static void dib9000_release(struct dvb_frontend *demod)
1770{
1771 struct dib9000_state *st = demod->demodulator_priv;
1772 u8 index_frontend;
1773
1774 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
1775 dvb_frontend_detach(st->fe[index_frontend]);
1776
1777 DibFreeLock(&state->platform.risc.mbx_if_lock);
1778 DibFreeLock(&state->platform.risc.mbx_lock);
1779 DibFreeLock(&state->platform.risc.mem_lock);
1780 DibFreeLock(&state->platform.risc.mem_mbx_lock);
1781 dibx000_exit_i2c_master(&st->i2c_master);
1782
1783 i2c_del_adapter(&st->tuner_adap);
1784 i2c_del_adapter(&st->component_bus);
1785 kfree(st->fe[0]);
1786 kfree(st);
1787}
1788
1789static int dib9000_wakeup(struct dvb_frontend *fe)
1790{
1791 return 0;
1792}
1793
1794static int dib9000_sleep(struct dvb_frontend *fe)
1795{
1796 struct dib9000_state *state = fe->demodulator_priv;
1797 u8 index_frontend;
1798 int ret;
1799
1800 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1801 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
1802 if (ret < 0)
1803 return ret;
1804 }
1805 return dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
1806}
1807
1808static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1809{
1810 tune->min_delay_ms = 1000;
1811 return 0;
1812}
1813
1814static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1815{
1816 struct dib9000_state *state = fe->demodulator_priv;
1817 u8 index_frontend, sub_index_frontend;
1818 fe_status_t stat;
1819 int ret;
1820
1821 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1822 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
1823 if (stat & FE_HAS_SYNC) {
1824 dprintk("TPS lock on the slave%i", index_frontend);
1825
1826
1827 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
1828 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
1829 sub_index_frontend++) {
1830 if (sub_index_frontend != index_frontend) {
1831 state->fe[sub_index_frontend]->dtv_property_cache.modulation =
1832 state->fe[index_frontend]->dtv_property_cache.modulation;
1833 state->fe[sub_index_frontend]->dtv_property_cache.inversion =
1834 state->fe[index_frontend]->dtv_property_cache.inversion;
1835 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
1836 state->fe[index_frontend]->dtv_property_cache.transmission_mode;
1837 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
1838 state->fe[index_frontend]->dtv_property_cache.guard_interval;
1839 state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
1840 state->fe[index_frontend]->dtv_property_cache.hierarchy;
1841 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
1842 state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
1843 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
1844 state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
1845 state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
1846 state->fe[index_frontend]->dtv_property_cache.rolloff;
1847 }
1848 }
1849 return 0;
1850 }
1851 }
1852
1853
1854 ret = dib9000_fw_get_channel(fe, fep);
1855 if (ret != 0)
1856 return ret;
1857
1858
1859 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1860 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
1861 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
1862 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
1863 state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation;
1864 state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy;
1865 state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP;
1866 state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP;
1867 state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff;
1868 }
1869
1870 return 0;
1871}
1872
1873static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
1874{
1875 struct dib9000_state *state = fe->demodulator_priv;
1876 state->tune_state = tune_state;
1877 if (tune_state == CT_DEMOD_START)
1878 state->status = FE_STATUS_TUNE_PENDING;
1879
1880 return 0;
1881}
1882
1883static u32 dib9000_get_status(struct dvb_frontend *fe)
1884{
1885 struct dib9000_state *state = fe->demodulator_priv;
1886 return state->status;
1887}
1888
1889static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
1890{
1891 struct dib9000_state *state = fe->demodulator_priv;
1892
1893 memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
1894 return 0;
1895}
1896
1897static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1898{
1899 struct dib9000_state *state = fe->demodulator_priv;
1900 int sleep_time, sleep_time_slave;
1901 u32 frontend_status;
1902 u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
1903 struct dvb_frontend_parametersContext channel_status;
1904
1905
1906 if (state->fe[0]->dtv_property_cache.frequency == 0) {
1907 dprintk("dib9000: must specify frequency ");
1908 return 0;
1909 }
1910
1911 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
1912 dprintk("dib9000: must specify bandwidth ");
1913 return 0;
1914 }
1915 fe->dtv_property_cache.delivery_system = SYS_DVBT;
1916
1917
1918 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
1919 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1920
1921 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1922 } else
1923 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1924
1925
1926 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1927 dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
1928
1929
1930 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
1931
1932 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
1933 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
1934
1935 dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
1936 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1937 }
1938
1939
1940 exit_condition = 0;
1941 index_frontend_success = 0;
1942 do {
1943 sleep_time = dib9000_fw_tune(state->fe[0], NULL);
1944 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1945 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1946 if (sleep_time == FE_CALLBACK_TIME_NEVER)
1947 sleep_time = sleep_time_slave;
1948 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
1949 sleep_time = sleep_time_slave;
1950 }
1951 if (sleep_time != FE_CALLBACK_TIME_NEVER)
1952 msleep(sleep_time / 10);
1953 else
1954 break;
1955
1956 nbr_pending = 0;
1957 exit_condition = 0;
1958 index_frontend_success = 0;
1959 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1960 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
1961 if (frontend_status > -FE_STATUS_TUNE_PENDING) {
1962 exit_condition = 2;
1963 index_frontend_success = index_frontend;
1964 break;
1965 }
1966 if (frontend_status == -FE_STATUS_TUNE_PENDING)
1967 nbr_pending++;
1968 }
1969 if ((exit_condition != 2) && (nbr_pending == 0))
1970 exit_condition = 1;
1971
1972 } while (exit_condition == 0);
1973
1974
1975 if (exit_condition == 1) {
1976 dprintk("tune failed");
1977 return 0;
1978 }
1979
1980 dprintk("tune success on frontend%i", index_frontend_success);
1981
1982
1983 dib9000_get_frontend(state->fe[0], fep);
1984
1985
1986 channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1987 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1988
1989 if (index_frontend != index_frontend_success) {
1990 dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
1991 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1992 }
1993 }
1994 do {
1995 sleep_time = FE_CALLBACK_TIME_NEVER;
1996 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1997 if (index_frontend != index_frontend_success) {
1998 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1999 if (sleep_time == FE_CALLBACK_TIME_NEVER)
2000 sleep_time = sleep_time_slave;
2001 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
2002 sleep_time = sleep_time_slave;
2003 }
2004 }
2005 if (sleep_time != FE_CALLBACK_TIME_NEVER)
2006 msleep(sleep_time / 10);
2007 else
2008 break;
2009
2010 nbr_pending = 0;
2011 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2012 if (index_frontend != index_frontend_success) {
2013 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
2014 if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
2015 nbr_pending++;
2016 }
2017 }
2018 } while (nbr_pending != 0);
2019
2020
2021 dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
2022 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2023 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
2024
2025
2026 dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
2027
2028 return 0;
2029}
2030
2031static u16 dib9000_read_lock(struct dvb_frontend *fe)
2032{
2033 struct dib9000_state *state = fe->demodulator_priv;
2034
2035 return dib9000_read_word(state, 535);
2036}
2037
2038static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2039{
2040 struct dib9000_state *state = fe->demodulator_priv;
2041 u8 index_frontend;
2042 u16 lock = 0, lock_slave = 0;
2043
2044 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2045 lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
2046
2047 lock = dib9000_read_word(state, 535);
2048
2049 *stat = 0;
2050
2051 if ((lock & 0x8000) || (lock_slave & 0x8000))
2052 *stat |= FE_HAS_SIGNAL;
2053 if ((lock & 0x3000) || (lock_slave & 0x3000))
2054 *stat |= FE_HAS_CARRIER;
2055 if ((lock & 0x0100) || (lock_slave & 0x0100))
2056 *stat |= FE_HAS_VITERBI;
2057 if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
2058 *stat |= FE_HAS_SYNC;
2059 if ((lock & 0x0008) || (lock_slave & 0x0008))
2060 *stat |= FE_HAS_LOCK;
2061
2062 return 0;
2063}
2064
2065static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
2066{
2067 struct dib9000_state *state = fe->demodulator_priv;
2068 u16 *c;
2069
2070 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2071 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2072 return -EIO;
2073 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR,
2074 state->i2c_read_buffer, 16 * 2);
2075 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2076
2077 c = (u16 *)state->i2c_read_buffer;
2078
2079 *ber = c[10] << 16 | c[11];
2080 return 0;
2081}
2082
2083static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2084{
2085 struct dib9000_state *state = fe->demodulator_priv;
2086 u8 index_frontend;
2087 u16 *c = (u16 *)state->i2c_read_buffer;
2088 u16 val;
2089
2090 *strength = 0;
2091 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2092 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
2093 if (val > 65535 - *strength)
2094 *strength = 65535;
2095 else
2096 *strength += val;
2097 }
2098
2099 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2100 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2101 return -EIO;
2102 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
2103 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2104
2105 val = 65535 - c[4];
2106 if (val > 65535 - *strength)
2107 *strength = 65535;
2108 else
2109 *strength += val;
2110 return 0;
2111}
2112
2113static u32 dib9000_get_snr(struct dvb_frontend *fe)
2114{
2115 struct dib9000_state *state = fe->demodulator_priv;
2116 u16 *c = (u16 *)state->i2c_read_buffer;
2117 u32 n, s, exp;
2118 u16 val;
2119
2120 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2121 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2122 return -EIO;
2123 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
2124 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2125
2126 val = c[7];
2127 n = (val >> 4) & 0xff;
2128 exp = ((val & 0xf) << 2);
2129 val = c[8];
2130 exp += ((val >> 14) & 0x3);
2131 if ((exp & 0x20) != 0)
2132 exp -= 0x40;
2133 n <<= exp + 16;
2134
2135 s = (val >> 6) & 0xFF;
2136 exp = (val & 0x3F);
2137 if ((exp & 0x20) != 0)
2138 exp -= 0x40;
2139 s <<= exp + 16;
2140
2141 if (n > 0) {
2142 u32 t = (s / n) << 16;
2143 return t + ((s << 16) - n * t) / n;
2144 }
2145 return 0xffffffff;
2146}
2147
2148static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
2149{
2150 struct dib9000_state *state = fe->demodulator_priv;
2151 u8 index_frontend;
2152 u32 snr_master;
2153
2154 snr_master = dib9000_get_snr(fe);
2155 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2156 snr_master += dib9000_get_snr(state->fe[index_frontend]);
2157
2158 if ((snr_master >> 16) != 0) {
2159 snr_master = 10 * intlog10(snr_master >> 16);
2160 *snr = snr_master / ((1 << 24) / 10);
2161 } else
2162 *snr = 0;
2163
2164 return 0;
2165}
2166
2167static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2168{
2169 struct dib9000_state *state = fe->demodulator_priv;
2170 u16 *c = (u16 *)state->i2c_read_buffer;
2171
2172 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2173 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2174 return -EIO;
2175 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
2176 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2177
2178 *unc = c[12];
2179 return 0;
2180}
2181
2182int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
2183{
2184 int k = 0, ret = 0;
2185 u8 new_addr = 0;
2186 struct i2c_device client = {.i2c_adap = i2c };
2187
2188 client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
2189 if (!client.i2c_write_buffer) {
2190 dprintk("%s: not enough memory", __func__);
2191 return -ENOMEM;
2192 }
2193 client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
2194 if (!client.i2c_read_buffer) {
2195 dprintk("%s: not enough memory", __func__);
2196 ret = -ENOMEM;
2197 goto error_memory;
2198 }
2199
2200 client.i2c_addr = default_addr + 16;
2201 dib9000_i2c_write16(&client, 1796, 0x0);
2202
2203 for (k = no_of_demods - 1; k >= 0; k--) {
2204
2205 new_addr = first_addr + (k << 1);
2206 client.i2c_addr = default_addr;
2207
2208 dib9000_i2c_write16(&client, 1817, 3);
2209 dib9000_i2c_write16(&client, 1796, 0);
2210 dib9000_i2c_write16(&client, 1227, 1);
2211 dib9000_i2c_write16(&client, 1227, 0);
2212
2213 client.i2c_addr = new_addr;
2214 dib9000_i2c_write16(&client, 1817, 3);
2215 dib9000_i2c_write16(&client, 1796, 0);
2216 dib9000_i2c_write16(&client, 1227, 1);
2217 dib9000_i2c_write16(&client, 1227, 0);
2218
2219 if (dib9000_identify(&client) == 0) {
2220 client.i2c_addr = default_addr;
2221 if (dib9000_identify(&client) == 0) {
2222 dprintk("DiB9000 #%d: not identified", k);
2223 ret = -EIO;
2224 goto error;
2225 }
2226 }
2227
2228 dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
2229 dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
2230
2231 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
2232 }
2233
2234 for (k = 0; k < no_of_demods; k++) {
2235 new_addr = first_addr | (k << 1);
2236 client.i2c_addr = new_addr;
2237
2238 dib9000_i2c_write16(&client, 1794, (new_addr << 2));
2239 dib9000_i2c_write16(&client, 1795, 0);
2240 }
2241
2242error:
2243 kfree(client.i2c_read_buffer);
2244error_memory:
2245 kfree(client.i2c_write_buffer);
2246
2247 return ret;
2248}
2249EXPORT_SYMBOL(dib9000_i2c_enumeration);
2250
2251int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
2252{
2253 struct dib9000_state *state = fe->demodulator_priv;
2254 u8 index_frontend = 1;
2255
2256 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2257 index_frontend++;
2258 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
2259 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
2260 state->fe[index_frontend] = fe_slave;
2261 return 0;
2262 }
2263
2264 dprintk("too many slave frontend");
2265 return -ENOMEM;
2266}
2267EXPORT_SYMBOL(dib9000_set_slave_frontend);
2268
2269int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
2270{
2271 struct dib9000_state *state = fe->demodulator_priv;
2272 u8 index_frontend = 1;
2273
2274 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2275 index_frontend++;
2276 if (index_frontend != 1) {
2277 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1);
2278 state->fe[index_frontend] = NULL;
2279 return 0;
2280 }
2281
2282 dprintk("no frontend to be removed");
2283 return -ENODEV;
2284}
2285EXPORT_SYMBOL(dib9000_remove_slave_frontend);
2286
2287struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
2288{
2289 struct dib9000_state *state = fe->demodulator_priv;
2290
2291 if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
2292 return NULL;
2293 return state->fe[slave_index];
2294}
2295EXPORT_SYMBOL(dib9000_get_slave_frontend);
2296
2297static struct dvb_frontend_ops dib9000_ops;
2298struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
2299{
2300 struct dvb_frontend *fe;
2301 struct dib9000_state *st;
2302 st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
2303 if (st == NULL)
2304 return NULL;
2305 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
2306 if (fe == NULL) {
2307 kfree(st);
2308 return NULL;
2309 }
2310
2311 memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
2312 st->i2c.i2c_adap = i2c_adap;
2313 st->i2c.i2c_addr = i2c_addr;
2314 st->i2c.i2c_write_buffer = st->i2c_write_buffer;
2315 st->i2c.i2c_read_buffer = st->i2c_read_buffer;
2316
2317 st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
2318 st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
2319 st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
2320
2321 DibInitLock(&st->platform.risc.mbx_if_lock);
2322 DibInitLock(&st->platform.risc.mbx_lock);
2323 DibInitLock(&st->platform.risc.mem_lock);
2324 DibInitLock(&st->platform.risc.mem_mbx_lock);
2325
2326 st->fe[0] = fe;
2327 fe->demodulator_priv = st;
2328 memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
2329
2330
2331
2332
2333 if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2334 st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
2335
2336 if (dib9000_identify(&st->i2c) == 0)
2337 goto error;
2338
2339 dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
2340
2341 st->tuner_adap.dev.parent = i2c_adap->dev.parent;
2342 strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name));
2343 st->tuner_adap.algo = &dib9000_tuner_algo;
2344 st->tuner_adap.algo_data = NULL;
2345 i2c_set_adapdata(&st->tuner_adap, st);
2346 if (i2c_add_adapter(&st->tuner_adap) < 0)
2347 goto error;
2348
2349 st->component_bus.dev.parent = i2c_adap->dev.parent;
2350 strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name));
2351 st->component_bus.algo = &dib9000_component_bus_algo;
2352 st->component_bus.algo_data = NULL;
2353 st->component_bus_speed = 340;
2354 i2c_set_adapdata(&st->component_bus, st);
2355 if (i2c_add_adapter(&st->component_bus) < 0)
2356 goto component_bus_add_error;
2357
2358 dib9000_fw_reset(fe);
2359
2360 return fe;
2361
2362component_bus_add_error:
2363 i2c_del_adapter(&st->tuner_adap);
2364error:
2365 kfree(st);
2366 return NULL;
2367}
2368EXPORT_SYMBOL(dib9000_attach);
2369
2370static struct dvb_frontend_ops dib9000_ops = {
2371 .info = {
2372 .name = "DiBcom 9000",
2373 .type = FE_OFDM,
2374 .frequency_min = 44250000,
2375 .frequency_max = 867250000,
2376 .frequency_stepsize = 62500,
2377 .caps = FE_CAN_INVERSION_AUTO |
2378 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2379 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2380 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2381 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2382 },
2383
2384 .release = dib9000_release,
2385
2386 .init = dib9000_wakeup,
2387 .sleep = dib9000_sleep,
2388
2389 .set_frontend = dib9000_set_frontend,
2390 .get_tune_settings = dib9000_fe_get_tune_settings,
2391 .get_frontend = dib9000_get_frontend,
2392
2393 .read_status = dib9000_read_status,
2394 .read_ber = dib9000_read_ber,
2395 .read_signal_strength = dib9000_read_signal_strength,
2396 .read_snr = dib9000_read_snr,
2397 .read_ucblocks = dib9000_read_unc_blocks,
2398};
2399
2400MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2401MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2402MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
2403MODULE_LICENSE("GPL");
2404
