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31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/videodev2.h>
35
36#include <media/v4l2-device.h>
37#include <media/v4l2-common.h>
38#include <media/v4l2-mediabus.h>
39#include <media/v4l2-chip-ident.h>
40#include <media/v4l2-ctrls.h>
41#include <media/tvp514x.h>
42
43#include "tvp514x_regs.h"
44
45
46#define TVP514X_MODULE_NAME "tvp514x"
47
48
49#define I2C_RETRY_COUNT (5)
50#define LOCK_RETRY_COUNT (5)
51#define LOCK_RETRY_DELAY (200)
52
53
54static int debug;
55module_param(debug, bool, 0644);
56MODULE_PARM_DESC(debug, "Debug level (0-1)");
57
58MODULE_AUTHOR("Texas Instruments");
59MODULE_DESCRIPTION("TVP514X linux decoder driver");
60MODULE_LICENSE("GPL");
61
62
63enum tvp514x_std {
64 STD_NTSC_MJ = 0,
65 STD_PAL_BDGHIN,
66 STD_INVALID
67};
68
69
70
71
72
73
74
75
76struct tvp514x_std_info {
77 unsigned long width;
78 unsigned long height;
79 u8 video_std;
80 struct v4l2_standard standard;
81};
82
83static struct tvp514x_reg tvp514x_reg_list_default[0x40];
84
85static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable);
86
87
88
89
90
91
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97
98
99struct tvp514x_decoder {
100 struct v4l2_subdev sd;
101 struct v4l2_ctrl_handler hdl;
102 struct tvp514x_reg tvp514x_regs[ARRAY_SIZE(tvp514x_reg_list_default)];
103 const struct tvp514x_platform_data *pdata;
104
105 int ver;
106 int streaming;
107
108 enum tvp514x_std current_std;
109 int num_stds;
110 const struct tvp514x_std_info *std_list;
111
112 u32 input;
113 u32 output;
114};
115
116
117static struct tvp514x_reg tvp514x_reg_list_default[] = {
118
119 {TOK_WRITE, REG_INPUT_SEL, 0x05},
120 {TOK_WRITE, REG_AFE_GAIN_CTRL, 0x0F},
121
122 {TOK_WRITE, REG_VIDEO_STD, 0x00},
123 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
124 {TOK_SKIP, REG_AUTOSWITCH_MASK, 0x3F},
125 {TOK_WRITE, REG_COLOR_KILLER, 0x10},
126 {TOK_WRITE, REG_LUMA_CONTROL1, 0x00},
127 {TOK_WRITE, REG_LUMA_CONTROL2, 0x00},
128 {TOK_WRITE, REG_LUMA_CONTROL3, 0x02},
129 {TOK_WRITE, REG_BRIGHTNESS, 0x80},
130 {TOK_WRITE, REG_CONTRAST, 0x80},
131 {TOK_WRITE, REG_SATURATION, 0x80},
132 {TOK_WRITE, REG_HUE, 0x00},
133 {TOK_WRITE, REG_CHROMA_CONTROL1, 0x00},
134 {TOK_WRITE, REG_CHROMA_CONTROL2, 0x0E},
135
136 {TOK_SKIP, 0x0F, 0x00},
137 {TOK_WRITE, REG_COMP_PR_SATURATION, 0x80},
138 {TOK_WRITE, REG_COMP_Y_CONTRAST, 0x80},
139 {TOK_WRITE, REG_COMP_PB_SATURATION, 0x80},
140
141 {TOK_SKIP, 0x13, 0x00},
142 {TOK_WRITE, REG_COMP_Y_BRIGHTNESS, 0x80},
143
144 {TOK_SKIP, 0x15, 0x00},
145
146 {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55},
147 {TOK_SKIP, REG_AVID_START_PIXEL_MSB, 0x00},
148 {TOK_SKIP, REG_AVID_STOP_PIXEL_LSB, 0x25},
149 {TOK_SKIP, REG_AVID_STOP_PIXEL_MSB, 0x03},
150
151 {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00},
152 {TOK_SKIP, REG_HSYNC_START_PIXEL_MSB, 0x00},
153 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_LSB, 0x40},
154 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_MSB, 0x00},
155
156 {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04},
157 {TOK_SKIP, REG_VSYNC_START_LINE_MSB, 0x00},
158 {TOK_SKIP, REG_VSYNC_STOP_LINE_LSB, 0x07},
159 {TOK_SKIP, REG_VSYNC_STOP_LINE_MSB, 0x00},
160
161 {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01},
162 {TOK_SKIP, REG_VBLK_START_LINE_MSB, 0x00},
163 {TOK_SKIP, REG_VBLK_STOP_LINE_LSB, 0x15},
164 {TOK_SKIP, REG_VBLK_STOP_LINE_MSB, 0x00},
165
166 {TOK_SKIP, 0x26, 0x00},
167
168 {TOK_SKIP, 0x27, 0x00},
169 {TOK_SKIP, REG_FAST_SWTICH_CONTROL, 0xCC},
170
171 {TOK_SKIP, 0x29, 0x00},
172 {TOK_SKIP, REG_FAST_SWTICH_SCART_DELAY, 0x00},
173
174 {TOK_SKIP, 0x2B, 0x00},
175 {TOK_SKIP, REG_SCART_DELAY, 0x00},
176 {TOK_SKIP, REG_CTI_DELAY, 0x00},
177 {TOK_SKIP, REG_CTI_CONTROL, 0x00},
178
179 {TOK_SKIP, 0x2F, 0x00},
180
181 {TOK_SKIP, 0x30, 0x00},
182
183 {TOK_SKIP, 0x31, 0x00},
184
185 {TOK_WRITE, REG_SYNC_CONTROL, 0x00},
186
187 {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00},
188
189 {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11},
190
191 {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE},
192
193 {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF},
194 {TOK_WRITE, REG_OUTPUT_FORMATTER5, 0xFF},
195 {TOK_WRITE, REG_OUTPUT_FORMATTER6, 0xFF},
196
197 {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01},
198 {TOK_TERM, 0, 0},
199};
200
201
202
203
204
205
206
207static const struct tvp514x_std_info tvp514x_std_list[] = {
208
209 [STD_NTSC_MJ] = {
210 .width = NTSC_NUM_ACTIVE_PIXELS,
211 .height = NTSC_NUM_ACTIVE_LINES,
212 .video_std = VIDEO_STD_NTSC_MJ_BIT,
213 .standard = {
214 .index = 0,
215 .id = V4L2_STD_NTSC,
216 .name = "NTSC",
217 .frameperiod = {1001, 30000},
218 .framelines = 525
219 },
220
221 },
222 [STD_PAL_BDGHIN] = {
223 .width = PAL_NUM_ACTIVE_PIXELS,
224 .height = PAL_NUM_ACTIVE_LINES,
225 .video_std = VIDEO_STD_PAL_BDGHIN_BIT,
226 .standard = {
227 .index = 1,
228 .id = V4L2_STD_PAL,
229 .name = "PAL",
230 .frameperiod = {1, 25},
231 .framelines = 625
232 },
233 },
234
235};
236
237
238static inline struct tvp514x_decoder *to_decoder(struct v4l2_subdev *sd)
239{
240 return container_of(sd, struct tvp514x_decoder, sd);
241}
242
243static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
244{
245 return &container_of(ctrl->handler, struct tvp514x_decoder, hdl)->sd;
246}
247
248
249
250
251
252
253
254
255
256static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg)
257{
258 int err, retry = 0;
259 struct i2c_client *client = v4l2_get_subdevdata(sd);
260
261read_again:
262
263 err = i2c_smbus_read_byte_data(client, reg);
264 if (err < 0) {
265 if (retry <= I2C_RETRY_COUNT) {
266 v4l2_warn(sd, "Read: retry ... %d\n", retry);
267 retry++;
268 msleep_interruptible(10);
269 goto read_again;
270 }
271 }
272
273 return err;
274}
275
276
277
278
279
280
281static void dump_reg(struct v4l2_subdev *sd, u8 reg)
282{
283 u32 val;
284
285 val = tvp514x_read_reg(sd, reg);
286 v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val);
287}
288
289
290
291
292
293
294
295
296
297
298static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val)
299{
300 int err, retry = 0;
301 struct i2c_client *client = v4l2_get_subdevdata(sd);
302
303write_again:
304
305 err = i2c_smbus_write_byte_data(client, reg, val);
306 if (err) {
307 if (retry <= I2C_RETRY_COUNT) {
308 v4l2_warn(sd, "Write: retry ... %d\n", retry);
309 retry++;
310 msleep_interruptible(10);
311 goto write_again;
312 }
313 }
314
315 return err;
316}
317
318
319
320
321
322
323
324
325
326
327
328
329
330static int tvp514x_write_regs(struct v4l2_subdev *sd,
331 const struct tvp514x_reg reglist[])
332{
333 int err;
334 const struct tvp514x_reg *next = reglist;
335
336 for (; next->token != TOK_TERM; next++) {
337 if (next->token == TOK_DELAY) {
338 msleep(next->val);
339 continue;
340 }
341
342 if (next->token == TOK_SKIP)
343 continue;
344
345 err = tvp514x_write_reg(sd, next->reg, (u8) next->val);
346 if (err) {
347 v4l2_err(sd, "Write failed. Err[%d]\n", err);
348 return err;
349 }
350 }
351 return 0;
352}
353
354
355
356
357
358
359
360
361static enum tvp514x_std tvp514x_query_current_std(struct v4l2_subdev *sd)
362{
363 u8 std, std_status;
364
365 std = tvp514x_read_reg(sd, REG_VIDEO_STD);
366 if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT)
367
368 std_status = tvp514x_read_reg(sd, REG_VIDEO_STD_STATUS);
369 else
370
371 std_status = std;
372
373 switch (std_status & VIDEO_STD_MASK) {
374 case VIDEO_STD_NTSC_MJ_BIT:
375 return STD_NTSC_MJ;
376
377 case VIDEO_STD_PAL_BDGHIN_BIT:
378 return STD_PAL_BDGHIN;
379
380 default:
381 return STD_INVALID;
382 }
383
384 return STD_INVALID;
385}
386
387
388static void tvp514x_reg_dump(struct v4l2_subdev *sd)
389{
390 dump_reg(sd, REG_INPUT_SEL);
391 dump_reg(sd, REG_AFE_GAIN_CTRL);
392 dump_reg(sd, REG_VIDEO_STD);
393 dump_reg(sd, REG_OPERATION_MODE);
394 dump_reg(sd, REG_COLOR_KILLER);
395 dump_reg(sd, REG_LUMA_CONTROL1);
396 dump_reg(sd, REG_LUMA_CONTROL2);
397 dump_reg(sd, REG_LUMA_CONTROL3);
398 dump_reg(sd, REG_BRIGHTNESS);
399 dump_reg(sd, REG_CONTRAST);
400 dump_reg(sd, REG_SATURATION);
401 dump_reg(sd, REG_HUE);
402 dump_reg(sd, REG_CHROMA_CONTROL1);
403 dump_reg(sd, REG_CHROMA_CONTROL2);
404 dump_reg(sd, REG_COMP_PR_SATURATION);
405 dump_reg(sd, REG_COMP_Y_CONTRAST);
406 dump_reg(sd, REG_COMP_PB_SATURATION);
407 dump_reg(sd, REG_COMP_Y_BRIGHTNESS);
408 dump_reg(sd, REG_AVID_START_PIXEL_LSB);
409 dump_reg(sd, REG_AVID_START_PIXEL_MSB);
410 dump_reg(sd, REG_AVID_STOP_PIXEL_LSB);
411 dump_reg(sd, REG_AVID_STOP_PIXEL_MSB);
412 dump_reg(sd, REG_HSYNC_START_PIXEL_LSB);
413 dump_reg(sd, REG_HSYNC_START_PIXEL_MSB);
414 dump_reg(sd, REG_HSYNC_STOP_PIXEL_LSB);
415 dump_reg(sd, REG_HSYNC_STOP_PIXEL_MSB);
416 dump_reg(sd, REG_VSYNC_START_LINE_LSB);
417 dump_reg(sd, REG_VSYNC_START_LINE_MSB);
418 dump_reg(sd, REG_VSYNC_STOP_LINE_LSB);
419 dump_reg(sd, REG_VSYNC_STOP_LINE_MSB);
420 dump_reg(sd, REG_VBLK_START_LINE_LSB);
421 dump_reg(sd, REG_VBLK_START_LINE_MSB);
422 dump_reg(sd, REG_VBLK_STOP_LINE_LSB);
423 dump_reg(sd, REG_VBLK_STOP_LINE_MSB);
424 dump_reg(sd, REG_SYNC_CONTROL);
425 dump_reg(sd, REG_OUTPUT_FORMATTER1);
426 dump_reg(sd, REG_OUTPUT_FORMATTER2);
427 dump_reg(sd, REG_OUTPUT_FORMATTER3);
428 dump_reg(sd, REG_OUTPUT_FORMATTER4);
429 dump_reg(sd, REG_OUTPUT_FORMATTER5);
430 dump_reg(sd, REG_OUTPUT_FORMATTER6);
431 dump_reg(sd, REG_CLEAR_LOST_LOCK);
432}
433
434
435
436
437
438
439
440
441static int tvp514x_configure(struct v4l2_subdev *sd,
442 struct tvp514x_decoder *decoder)
443{
444 int err;
445
446
447 err =
448 tvp514x_write_regs(sd, decoder->tvp514x_regs);
449 if (err)
450 return err;
451
452 if (debug)
453 tvp514x_reg_dump(sd);
454
455 return 0;
456}
457
458
459
460
461
462
463
464
465
466
467
468
469static int tvp514x_detect(struct v4l2_subdev *sd,
470 struct tvp514x_decoder *decoder)
471{
472 u8 chip_id_msb, chip_id_lsb, rom_ver;
473 struct i2c_client *client = v4l2_get_subdevdata(sd);
474
475 chip_id_msb = tvp514x_read_reg(sd, REG_CHIP_ID_MSB);
476 chip_id_lsb = tvp514x_read_reg(sd, REG_CHIP_ID_LSB);
477 rom_ver = tvp514x_read_reg(sd, REG_ROM_VERSION);
478
479 v4l2_dbg(1, debug, sd,
480 "chip id detected msb:0x%x lsb:0x%x rom version:0x%x\n",
481 chip_id_msb, chip_id_lsb, rom_ver);
482 if ((chip_id_msb != TVP514X_CHIP_ID_MSB)
483 || ((chip_id_lsb != TVP5146_CHIP_ID_LSB)
484 && (chip_id_lsb != TVP5147_CHIP_ID_LSB))) {
485
486
487
488 v4l2_err(sd, "chip id mismatch msb:0x%x lsb:0x%x\n",
489 chip_id_msb, chip_id_lsb);
490 return -ENODEV;
491 }
492
493 decoder->ver = rom_ver;
494
495 v4l2_info(sd, "%s (Version - 0x%.2x) found at 0x%x (%s)\n",
496 client->name, decoder->ver,
497 client->addr << 1, client->adapter->name);
498 return 0;
499}
500
501
502
503
504
505
506
507
508
509static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
510{
511 struct tvp514x_decoder *decoder = to_decoder(sd);
512 enum tvp514x_std current_std;
513 enum tvp514x_input input_sel;
514 u8 sync_lock_status, lock_mask;
515
516 if (std_id == NULL)
517 return -EINVAL;
518
519 *std_id = V4L2_STD_UNKNOWN;
520
521
522 current_std = tvp514x_query_current_std(sd);
523 if (current_std == STD_INVALID)
524 return 0;
525
526 input_sel = decoder->input;
527
528 switch (input_sel) {
529 case INPUT_CVBS_VI1A:
530 case INPUT_CVBS_VI1B:
531 case INPUT_CVBS_VI1C:
532 case INPUT_CVBS_VI2A:
533 case INPUT_CVBS_VI2B:
534 case INPUT_CVBS_VI2C:
535 case INPUT_CVBS_VI3A:
536 case INPUT_CVBS_VI3B:
537 case INPUT_CVBS_VI3C:
538 case INPUT_CVBS_VI4A:
539 lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
540 STATUS_HORZ_SYNC_LOCK_BIT |
541 STATUS_VIRT_SYNC_LOCK_BIT;
542 break;
543
544 case INPUT_SVIDEO_VI2A_VI1A:
545 case INPUT_SVIDEO_VI2B_VI1B:
546 case INPUT_SVIDEO_VI2C_VI1C:
547 case INPUT_SVIDEO_VI2A_VI3A:
548 case INPUT_SVIDEO_VI2B_VI3B:
549 case INPUT_SVIDEO_VI2C_VI3C:
550 case INPUT_SVIDEO_VI4A_VI1A:
551 case INPUT_SVIDEO_VI4A_VI1B:
552 case INPUT_SVIDEO_VI4A_VI1C:
553 case INPUT_SVIDEO_VI4A_VI3A:
554 case INPUT_SVIDEO_VI4A_VI3B:
555 case INPUT_SVIDEO_VI4A_VI3C:
556 lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
557 STATUS_VIRT_SYNC_LOCK_BIT;
558 break;
559
560 default:
561 return -EINVAL;
562 }
563
564 sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1);
565 if (lock_mask != (sync_lock_status & lock_mask))
566 return 0;
567
568 *std_id = decoder->std_list[current_std].standard.id;
569
570 v4l2_dbg(1, debug, sd, "Current STD: %s\n",
571 decoder->std_list[current_std].standard.name);
572 return 0;
573}
574
575
576
577
578
579
580
581
582
583static int tvp514x_s_std(struct v4l2_subdev *sd, v4l2_std_id std_id)
584{
585 struct tvp514x_decoder *decoder = to_decoder(sd);
586 int err, i;
587
588 for (i = 0; i < decoder->num_stds; i++)
589 if (std_id & decoder->std_list[i].standard.id)
590 break;
591
592 if ((i == decoder->num_stds) || (i == STD_INVALID))
593 return -EINVAL;
594
595 err = tvp514x_write_reg(sd, REG_VIDEO_STD,
596 decoder->std_list[i].video_std);
597 if (err)
598 return err;
599
600 decoder->current_std = i;
601 decoder->tvp514x_regs[REG_VIDEO_STD].val =
602 decoder->std_list[i].video_std;
603
604 v4l2_dbg(1, debug, sd, "Standard set to: %s\n",
605 decoder->std_list[i].standard.name);
606 return 0;
607}
608
609
610
611
612
613
614
615
616
617
618
619
620static int tvp514x_s_routing(struct v4l2_subdev *sd,
621 u32 input, u32 output, u32 config)
622{
623 struct tvp514x_decoder *decoder = to_decoder(sd);
624 int err;
625 enum tvp514x_input input_sel;
626 enum tvp514x_output output_sel;
627 u8 sync_lock_status, lock_mask;
628 int try_count = LOCK_RETRY_COUNT;
629
630 if ((input >= INPUT_INVALID) ||
631 (output >= OUTPUT_INVALID))
632
633 return -EINVAL;
634
635
636
637
638
639
640
641
642
643 if (!decoder->streaming)
644 tvp514x_s_stream(sd, 1);
645
646 input_sel = input;
647 output_sel = output;
648
649 err = tvp514x_write_reg(sd, REG_INPUT_SEL, input_sel);
650 if (err)
651 return err;
652
653 output_sel |= tvp514x_read_reg(sd,
654 REG_OUTPUT_FORMATTER1) & 0x7;
655 err = tvp514x_write_reg(sd, REG_OUTPUT_FORMATTER1,
656 output_sel);
657 if (err)
658 return err;
659
660 decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
661 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
662
663
664 msleep(LOCK_RETRY_DELAY);
665 err =
666 tvp514x_write_reg(sd, REG_CLEAR_LOST_LOCK, 0x01);
667 if (err)
668 return err;
669
670 switch (input_sel) {
671 case INPUT_CVBS_VI1A:
672 case INPUT_CVBS_VI1B:
673 case INPUT_CVBS_VI1C:
674 case INPUT_CVBS_VI2A:
675 case INPUT_CVBS_VI2B:
676 case INPUT_CVBS_VI2C:
677 case INPUT_CVBS_VI3A:
678 case INPUT_CVBS_VI3B:
679 case INPUT_CVBS_VI3C:
680 case INPUT_CVBS_VI4A:
681 lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
682 STATUS_HORZ_SYNC_LOCK_BIT |
683 STATUS_VIRT_SYNC_LOCK_BIT;
684 break;
685
686 case INPUT_SVIDEO_VI2A_VI1A:
687 case INPUT_SVIDEO_VI2B_VI1B:
688 case INPUT_SVIDEO_VI2C_VI1C:
689 case INPUT_SVIDEO_VI2A_VI3A:
690 case INPUT_SVIDEO_VI2B_VI3B:
691 case INPUT_SVIDEO_VI2C_VI3C:
692 case INPUT_SVIDEO_VI4A_VI1A:
693 case INPUT_SVIDEO_VI4A_VI1B:
694 case INPUT_SVIDEO_VI4A_VI1C:
695 case INPUT_SVIDEO_VI4A_VI3A:
696 case INPUT_SVIDEO_VI4A_VI3B:
697 case INPUT_SVIDEO_VI4A_VI3C:
698 lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
699 STATUS_VIRT_SYNC_LOCK_BIT;
700 break;
701
702 default:
703 return -EINVAL;
704 }
705
706 while (try_count-- > 0) {
707
708 msleep(LOCK_RETRY_DELAY);
709
710 sync_lock_status = tvp514x_read_reg(sd,
711 REG_STATUS1);
712 if (lock_mask == (sync_lock_status & lock_mask))
713
714 break;
715 }
716
717 if (try_count < 0)
718 return -EINVAL;
719
720 decoder->input = input;
721 decoder->output = output;
722
723 v4l2_dbg(1, debug, sd, "Input set to: %d\n", input_sel);
724
725 return 0;
726}
727
728
729
730
731
732
733
734
735static int tvp514x_s_ctrl(struct v4l2_ctrl *ctrl)
736{
737 struct v4l2_subdev *sd = to_sd(ctrl);
738 struct tvp514x_decoder *decoder = to_decoder(sd);
739 int err = -EINVAL, value;
740
741 value = ctrl->val;
742
743 switch (ctrl->id) {
744 case V4L2_CID_BRIGHTNESS:
745 err = tvp514x_write_reg(sd, REG_BRIGHTNESS, value);
746 if (!err)
747 decoder->tvp514x_regs[REG_BRIGHTNESS].val = value;
748 break;
749 case V4L2_CID_CONTRAST:
750 err = tvp514x_write_reg(sd, REG_CONTRAST, value);
751 if (!err)
752 decoder->tvp514x_regs[REG_CONTRAST].val = value;
753 break;
754 case V4L2_CID_SATURATION:
755 err = tvp514x_write_reg(sd, REG_SATURATION, value);
756 if (!err)
757 decoder->tvp514x_regs[REG_SATURATION].val = value;
758 break;
759 case V4L2_CID_HUE:
760 if (value == 180)
761 value = 0x7F;
762 else if (value == -180)
763 value = 0x80;
764 err = tvp514x_write_reg(sd, REG_HUE, value);
765 if (!err)
766 decoder->tvp514x_regs[REG_HUE].val = value;
767 break;
768 case V4L2_CID_AUTOGAIN:
769 err = tvp514x_write_reg(sd, REG_AFE_GAIN_CTRL, value ? 0x0f : 0x0c);
770 if (!err)
771 decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value;
772 break;
773 }
774
775 v4l2_dbg(1, debug, sd, "Set Control: ID - %d - %d\n",
776 ctrl->id, ctrl->val);
777 return err;
778}
779
780
781
782
783
784
785
786
787
788static int
789tvp514x_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
790 enum v4l2_mbus_pixelcode *code)
791{
792 if (index)
793 return -EINVAL;
794
795 *code = V4L2_MBUS_FMT_YUYV10_2X10;
796 return 0;
797}
798
799
800
801
802
803
804
805
806static int
807tvp514x_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
808{
809 struct tvp514x_decoder *decoder = to_decoder(sd);
810 enum tvp514x_std current_std;
811
812 if (f == NULL)
813 return -EINVAL;
814
815
816 current_std = decoder->current_std;
817
818 f->code = V4L2_MBUS_FMT_YUYV10_2X10;
819 f->width = decoder->std_list[current_std].width;
820 f->height = decoder->std_list[current_std].height;
821 f->field = V4L2_FIELD_INTERLACED;
822 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
823
824 v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d\n",
825 f->width, f->height);
826 return 0;
827}
828
829
830
831
832
833
834
835
836static int
837tvp514x_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
838{
839 struct tvp514x_decoder *decoder = to_decoder(sd);
840 struct v4l2_captureparm *cparm;
841 enum tvp514x_std current_std;
842
843 if (a == NULL)
844 return -EINVAL;
845
846 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
847
848 return -EINVAL;
849
850
851 current_std = decoder->current_std;
852
853 cparm = &a->parm.capture;
854 cparm->capability = V4L2_CAP_TIMEPERFRAME;
855 cparm->timeperframe =
856 decoder->std_list[current_std].standard.frameperiod;
857
858 return 0;
859}
860
861
862
863
864
865
866
867
868
869static int
870tvp514x_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
871{
872 struct tvp514x_decoder *decoder = to_decoder(sd);
873 struct v4l2_fract *timeperframe;
874 enum tvp514x_std current_std;
875
876 if (a == NULL)
877 return -EINVAL;
878
879 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
880
881 return -EINVAL;
882
883 timeperframe = &a->parm.capture.timeperframe;
884
885
886 current_std = decoder->current_std;
887
888 *timeperframe =
889 decoder->std_list[current_std].standard.frameperiod;
890
891 return 0;
892}
893
894
895
896
897
898
899
900
901static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable)
902{
903 int err = 0;
904 struct i2c_client *client = v4l2_get_subdevdata(sd);
905 struct tvp514x_decoder *decoder = to_decoder(sd);
906
907 if (decoder->streaming == enable)
908 return 0;
909
910 switch (enable) {
911 case 0:
912 {
913
914 err = tvp514x_write_reg(sd, REG_OPERATION_MODE, 0x01);
915 if (err) {
916 v4l2_err(sd, "Unable to turn off decoder\n");
917 return err;
918 }
919 decoder->streaming = enable;
920 break;
921 }
922 case 1:
923 {
924 struct tvp514x_reg *int_seq = (struct tvp514x_reg *)
925 client->driver->id_table->driver_data;
926
927
928 err = tvp514x_write_regs(sd, int_seq);
929 if (err) {
930 v4l2_err(sd, "Unable to turn on decoder\n");
931 return err;
932 }
933
934 err = tvp514x_detect(sd, decoder);
935 if (err) {
936 v4l2_err(sd, "Unable to detect decoder\n");
937 return err;
938 }
939 err = tvp514x_configure(sd, decoder);
940 if (err) {
941 v4l2_err(sd, "Unable to configure decoder\n");
942 return err;
943 }
944 decoder->streaming = enable;
945 break;
946 }
947 default:
948 err = -ENODEV;
949 break;
950 }
951
952 return err;
953}
954
955static const struct v4l2_ctrl_ops tvp514x_ctrl_ops = {
956 .s_ctrl = tvp514x_s_ctrl,
957};
958
959static const struct v4l2_subdev_core_ops tvp514x_core_ops = {
960 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
961 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
962 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
963 .g_ctrl = v4l2_subdev_g_ctrl,
964 .s_ctrl = v4l2_subdev_s_ctrl,
965 .queryctrl = v4l2_subdev_queryctrl,
966 .querymenu = v4l2_subdev_querymenu,
967 .s_std = tvp514x_s_std,
968};
969
970static const struct v4l2_subdev_video_ops tvp514x_video_ops = {
971 .s_routing = tvp514x_s_routing,
972 .querystd = tvp514x_querystd,
973 .enum_mbus_fmt = tvp514x_enum_mbus_fmt,
974 .g_mbus_fmt = tvp514x_mbus_fmt,
975 .try_mbus_fmt = tvp514x_mbus_fmt,
976 .s_mbus_fmt = tvp514x_mbus_fmt,
977 .g_parm = tvp514x_g_parm,
978 .s_parm = tvp514x_s_parm,
979 .s_stream = tvp514x_s_stream,
980};
981
982static const struct v4l2_subdev_ops tvp514x_ops = {
983 .core = &tvp514x_core_ops,
984 .video = &tvp514x_video_ops,
985};
986
987static struct tvp514x_decoder tvp514x_dev = {
988 .streaming = 0,
989 .current_std = STD_NTSC_MJ,
990 .std_list = tvp514x_std_list,
991 .num_stds = ARRAY_SIZE(tvp514x_std_list),
992
993};
994
995
996
997
998
999
1000
1001
1002
1003static int
1004tvp514x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1005{
1006 struct tvp514x_decoder *decoder;
1007 struct v4l2_subdev *sd;
1008
1009
1010 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1011 return -EIO;
1012
1013 if (!client->dev.platform_data) {
1014 v4l2_err(client, "No platform data!!\n");
1015 return -ENODEV;
1016 }
1017
1018 decoder = kzalloc(sizeof(*decoder), GFP_KERNEL);
1019 if (!decoder)
1020 return -ENOMEM;
1021
1022
1023 *decoder = tvp514x_dev;
1024
1025 memcpy(decoder->tvp514x_regs, tvp514x_reg_list_default,
1026 sizeof(tvp514x_reg_list_default));
1027
1028
1029 decoder->pdata = client->dev.platform_data;
1030
1031
1032
1033
1034
1035
1036 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |=
1037 (decoder->pdata->clk_polarity << 1);
1038 decoder->tvp514x_regs[REG_SYNC_CONTROL].val |=
1039 ((decoder->pdata->hs_polarity << 2) |
1040 (decoder->pdata->vs_polarity << 3));
1041
1042 decoder->tvp514x_regs[REG_VIDEO_STD].val =
1043 VIDEO_STD_AUTO_SWITCH_BIT;
1044
1045
1046 sd = &decoder->sd;
1047 v4l2_i2c_subdev_init(sd, client, &tvp514x_ops);
1048
1049 v4l2_ctrl_handler_init(&decoder->hdl, 5);
1050 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1051 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1052 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1053 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1054 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1055 V4L2_CID_SATURATION, 0, 255, 1, 128);
1056 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1057 V4L2_CID_HUE, -180, 180, 180, 0);
1058 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1059 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1060 sd->ctrl_handler = &decoder->hdl;
1061 if (decoder->hdl.error) {
1062 int err = decoder->hdl.error;
1063
1064 v4l2_ctrl_handler_free(&decoder->hdl);
1065 kfree(decoder);
1066 return err;
1067 }
1068 v4l2_ctrl_handler_setup(&decoder->hdl);
1069
1070 v4l2_info(sd, "%s decoder driver registered !!\n", sd->name);
1071
1072 return 0;
1073
1074}
1075
1076
1077
1078
1079
1080
1081
1082
1083static int tvp514x_remove(struct i2c_client *client)
1084{
1085 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1086 struct tvp514x_decoder *decoder = to_decoder(sd);
1087
1088 v4l2_device_unregister_subdev(sd);
1089 v4l2_ctrl_handler_free(&decoder->hdl);
1090 kfree(decoder);
1091 return 0;
1092}
1093
1094static const struct tvp514x_reg tvp5146_init_reg_seq[] = {
1095 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1096 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1097 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1098 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1099 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1100 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1101 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1102 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1103 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1104 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1105 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1106 {TOK_TERM, 0, 0},
1107};
1108
1109
1110static const struct tvp514x_reg tvp5147_init_reg_seq[] = {
1111 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1112 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1113 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1114 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1115 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1116 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1117 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1118 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1119 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x16},
1120 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1121 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xA0},
1122 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x16},
1123 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1124 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1125 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1126 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1127 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1128 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1129 {TOK_TERM, 0, 0},
1130};
1131
1132
1133static const struct tvp514x_reg tvp514xm_init_reg_seq[] = {
1134 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1135 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1136 {TOK_TERM, 0, 0},
1137};
1138
1139
1140
1141
1142
1143
1144
1145static const struct i2c_device_id tvp514x_id[] = {
1146 {"tvp5146", (unsigned long)tvp5146_init_reg_seq},
1147 {"tvp5146m2", (unsigned long)tvp514xm_init_reg_seq},
1148 {"tvp5147", (unsigned long)tvp5147_init_reg_seq},
1149 {"tvp5147m1", (unsigned long)tvp514xm_init_reg_seq},
1150 {},
1151};
1152
1153MODULE_DEVICE_TABLE(i2c, tvp514x_id);
1154
1155static struct i2c_driver tvp514x_driver = {
1156 .driver = {
1157 .owner = THIS_MODULE,
1158 .name = TVP514X_MODULE_NAME,
1159 },
1160 .probe = tvp514x_probe,
1161 .remove = tvp514x_remove,
1162 .id_table = tvp514x_id,
1163};
1164
1165static int __init tvp514x_init(void)
1166{
1167 return i2c_add_driver(&tvp514x_driver);
1168}
1169
1170static void __exit tvp514x_exit(void)
1171{
1172 i2c_del_driver(&tvp514x_driver);
1173}
1174
1175module_init(tvp514x_init);
1176module_exit(tvp514x_exit);
1177