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19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/gpio.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/platform_device.h>
27
28#include <linux/mfd/asic3.h>
29#include <linux/mfd/core.h>
30#include <linux/mfd/ds1wm.h>
31#include <linux/mfd/tmio.h>
32
33enum {
34 ASIC3_CLOCK_SPI,
35 ASIC3_CLOCK_OWM,
36 ASIC3_CLOCK_PWM0,
37 ASIC3_CLOCK_PWM1,
38 ASIC3_CLOCK_LED0,
39 ASIC3_CLOCK_LED1,
40 ASIC3_CLOCK_LED2,
41 ASIC3_CLOCK_SD_HOST,
42 ASIC3_CLOCK_SD_BUS,
43 ASIC3_CLOCK_SMBUS,
44 ASIC3_CLOCK_EX0,
45 ASIC3_CLOCK_EX1,
46};
47
48struct asic3_clk {
49 int enabled;
50 unsigned int cdex;
51 unsigned long rate;
52};
53
54#define INIT_CDEX(_name, _rate) \
55 [ASIC3_CLOCK_##_name] = { \
56 .cdex = CLOCK_CDEX_##_name, \
57 .rate = _rate, \
58 }
59
60static struct asic3_clk asic3_clk_init[] __initdata = {
61 INIT_CDEX(SPI, 0),
62 INIT_CDEX(OWM, 5000000),
63 INIT_CDEX(PWM0, 0),
64 INIT_CDEX(PWM1, 0),
65 INIT_CDEX(LED0, 0),
66 INIT_CDEX(LED1, 0),
67 INIT_CDEX(LED2, 0),
68 INIT_CDEX(SD_HOST, 24576000),
69 INIT_CDEX(SD_BUS, 12288000),
70 INIT_CDEX(SMBUS, 0),
71 INIT_CDEX(EX0, 32768),
72 INIT_CDEX(EX1, 24576000),
73};
74
75struct asic3 {
76 void __iomem *mapping;
77 unsigned int bus_shift;
78 unsigned int irq_nr;
79 unsigned int irq_base;
80 spinlock_t lock;
81 u16 irq_bothedge[4];
82 struct gpio_chip gpio;
83 struct device *dev;
84 void __iomem *tmio_cnf;
85
86 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
87};
88
89static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
90
91void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
92{
93 iowrite16(value, asic->mapping +
94 (reg >> asic->bus_shift));
95}
96EXPORT_SYMBOL_GPL(asic3_write_register);
97
98u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
99{
100 return ioread16(asic->mapping +
101 (reg >> asic->bus_shift));
102}
103EXPORT_SYMBOL_GPL(asic3_read_register);
104
105static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
106{
107 unsigned long flags;
108 u32 val;
109
110 spin_lock_irqsave(&asic->lock, flags);
111 val = asic3_read_register(asic, reg);
112 if (set)
113 val |= bits;
114 else
115 val &= ~bits;
116 asic3_write_register(asic, reg, val);
117 spin_unlock_irqrestore(&asic->lock, flags);
118}
119
120
121#define MAX_ASIC_ISR_LOOPS 20
122#define ASIC3_GPIO_BASE_INCR \
123 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
124
125static void asic3_irq_flip_edge(struct asic3 *asic,
126 u32 base, int bit)
127{
128 u16 edge;
129 unsigned long flags;
130
131 spin_lock_irqsave(&asic->lock, flags);
132 edge = asic3_read_register(asic,
133 base + ASIC3_GPIO_EDGE_TRIGGER);
134 edge ^= bit;
135 asic3_write_register(asic,
136 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
137 spin_unlock_irqrestore(&asic->lock, flags);
138}
139
140static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
141{
142 struct asic3 *asic = irq_desc_get_handler_data(desc);
143 struct irq_data *data = irq_desc_get_irq_data(desc);
144 int iter, i;
145 unsigned long flags;
146
147 data->chip->irq_ack(data);
148
149 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
150 u32 status;
151 int bank;
152
153 spin_lock_irqsave(&asic->lock, flags);
154 status = asic3_read_register(asic,
155 ASIC3_OFFSET(INTR, P_INT_STAT));
156 spin_unlock_irqrestore(&asic->lock, flags);
157
158
159 if ((status & 0x3ff) == 0)
160 break;
161
162
163 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
164 if (status & (1 << bank)) {
165 unsigned long base, istat;
166
167 base = ASIC3_GPIO_A_BASE
168 + bank * ASIC3_GPIO_BASE_INCR;
169
170 spin_lock_irqsave(&asic->lock, flags);
171 istat = asic3_read_register(asic,
172 base +
173 ASIC3_GPIO_INT_STATUS);
174
175 asic3_write_register(asic,
176 base +
177 ASIC3_GPIO_INT_STATUS, 0);
178 spin_unlock_irqrestore(&asic->lock, flags);
179
180 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
181 int bit = (1 << i);
182 unsigned int irqnr;
183
184 if (!(istat & bit))
185 continue;
186
187 irqnr = asic->irq_base +
188 (ASIC3_GPIOS_PER_BANK * bank)
189 + i;
190 generic_handle_irq(irqnr);
191 if (asic->irq_bothedge[bank] & bit)
192 asic3_irq_flip_edge(asic, base,
193 bit);
194 }
195 }
196 }
197
198
199 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
200
201 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
202 generic_handle_irq(asic->irq_base + i);
203 }
204 }
205
206 if (iter >= MAX_ASIC_ISR_LOOPS)
207 dev_err(asic->dev, "interrupt processing overrun\n");
208}
209
210static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
211{
212 int n;
213
214 n = (irq - asic->irq_base) >> 4;
215
216 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
217}
218
219static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
220{
221 return (irq - asic->irq_base) & 0xf;
222}
223
224static void asic3_mask_gpio_irq(struct irq_data *data)
225{
226 struct asic3 *asic = irq_data_get_irq_chip_data(data);
227 u32 val, bank, index;
228 unsigned long flags;
229
230 bank = asic3_irq_to_bank(asic, data->irq);
231 index = asic3_irq_to_index(asic, data->irq);
232
233 spin_lock_irqsave(&asic->lock, flags);
234 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
235 val |= 1 << index;
236 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
237 spin_unlock_irqrestore(&asic->lock, flags);
238}
239
240static void asic3_mask_irq(struct irq_data *data)
241{
242 struct asic3 *asic = irq_data_get_irq_chip_data(data);
243 int regval;
244 unsigned long flags;
245
246 spin_lock_irqsave(&asic->lock, flags);
247 regval = asic3_read_register(asic,
248 ASIC3_INTR_BASE +
249 ASIC3_INTR_INT_MASK);
250
251 regval &= ~(ASIC3_INTMASK_MASK0 <<
252 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
253
254 asic3_write_register(asic,
255 ASIC3_INTR_BASE +
256 ASIC3_INTR_INT_MASK,
257 regval);
258 spin_unlock_irqrestore(&asic->lock, flags);
259}
260
261static void asic3_unmask_gpio_irq(struct irq_data *data)
262{
263 struct asic3 *asic = irq_data_get_irq_chip_data(data);
264 u32 val, bank, index;
265 unsigned long flags;
266
267 bank = asic3_irq_to_bank(asic, data->irq);
268 index = asic3_irq_to_index(asic, data->irq);
269
270 spin_lock_irqsave(&asic->lock, flags);
271 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
272 val &= ~(1 << index);
273 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
274 spin_unlock_irqrestore(&asic->lock, flags);
275}
276
277static void asic3_unmask_irq(struct irq_data *data)
278{
279 struct asic3 *asic = irq_data_get_irq_chip_data(data);
280 int regval;
281 unsigned long flags;
282
283 spin_lock_irqsave(&asic->lock, flags);
284 regval = asic3_read_register(asic,
285 ASIC3_INTR_BASE +
286 ASIC3_INTR_INT_MASK);
287
288 regval |= (ASIC3_INTMASK_MASK0 <<
289 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
290
291 asic3_write_register(asic,
292 ASIC3_INTR_BASE +
293 ASIC3_INTR_INT_MASK,
294 regval);
295 spin_unlock_irqrestore(&asic->lock, flags);
296}
297
298static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
299{
300 struct asic3 *asic = irq_data_get_irq_chip_data(data);
301 u32 bank, index;
302 u16 trigger, level, edge, bit;
303 unsigned long flags;
304
305 bank = asic3_irq_to_bank(asic, data->irq);
306 index = asic3_irq_to_index(asic, data->irq);
307 bit = 1<<index;
308
309 spin_lock_irqsave(&asic->lock, flags);
310 level = asic3_read_register(asic,
311 bank + ASIC3_GPIO_LEVEL_TRIGGER);
312 edge = asic3_read_register(asic,
313 bank + ASIC3_GPIO_EDGE_TRIGGER);
314 trigger = asic3_read_register(asic,
315 bank + ASIC3_GPIO_TRIGGER_TYPE);
316 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
317
318 if (type == IRQ_TYPE_EDGE_RISING) {
319 trigger |= bit;
320 edge |= bit;
321 } else if (type == IRQ_TYPE_EDGE_FALLING) {
322 trigger |= bit;
323 edge &= ~bit;
324 } else if (type == IRQ_TYPE_EDGE_BOTH) {
325 trigger |= bit;
326 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
327 edge &= ~bit;
328 else
329 edge |= bit;
330 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
331 } else if (type == IRQ_TYPE_LEVEL_LOW) {
332 trigger &= ~bit;
333 level &= ~bit;
334 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
335 trigger &= ~bit;
336 level |= bit;
337 } else {
338
339
340
341
342
343 dev_notice(asic->dev, "irq type not changed\n");
344 }
345 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
346 level);
347 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
348 edge);
349 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
350 trigger);
351 spin_unlock_irqrestore(&asic->lock, flags);
352 return 0;
353}
354
355static struct irq_chip asic3_gpio_irq_chip = {
356 .name = "ASIC3-GPIO",
357 .irq_ack = asic3_mask_gpio_irq,
358 .irq_mask = asic3_mask_gpio_irq,
359 .irq_unmask = asic3_unmask_gpio_irq,
360 .irq_set_type = asic3_gpio_irq_type,
361};
362
363static struct irq_chip asic3_irq_chip = {
364 .name = "ASIC3",
365 .irq_ack = asic3_mask_irq,
366 .irq_mask = asic3_mask_irq,
367 .irq_unmask = asic3_unmask_irq,
368};
369
370static int __init asic3_irq_probe(struct platform_device *pdev)
371{
372 struct asic3 *asic = platform_get_drvdata(pdev);
373 unsigned long clksel = 0;
374 unsigned int irq, irq_base;
375 int ret;
376
377 ret = platform_get_irq(pdev, 0);
378 if (ret < 0)
379 return ret;
380 asic->irq_nr = ret;
381
382
383 clksel |= CLOCK_SEL_CX;
384 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
385 clksel);
386
387 irq_base = asic->irq_base;
388
389 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
390 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
391 irq_set_chip(irq, &asic3_gpio_irq_chip);
392 else
393 irq_set_chip(irq, &asic3_irq_chip);
394
395 irq_set_chip_data(irq, asic);
396 irq_set_handler(irq, handle_level_irq);
397 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
398 }
399
400 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
401 ASIC3_INTMASK_GINTMASK);
402
403 irq_set_chained_handler(asic->irq_nr, asic3_irq_demux);
404 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
405 irq_set_handler_data(asic->irq_nr, asic);
406
407 return 0;
408}
409
410static void asic3_irq_remove(struct platform_device *pdev)
411{
412 struct asic3 *asic = platform_get_drvdata(pdev);
413 unsigned int irq, irq_base;
414
415 irq_base = asic->irq_base;
416
417 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
418 set_irq_flags(irq, 0);
419 irq_set_chip_and_handler(irq, NULL, NULL);
420 irq_set_chip_data(irq, NULL);
421 }
422 irq_set_chained_handler(asic->irq_nr, NULL);
423}
424
425
426static int asic3_gpio_direction(struct gpio_chip *chip,
427 unsigned offset, int out)
428{
429 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
430 unsigned int gpio_base;
431 unsigned long flags;
432 struct asic3 *asic;
433
434 asic = container_of(chip, struct asic3, gpio);
435 gpio_base = ASIC3_GPIO_TO_BASE(offset);
436
437 if (gpio_base > ASIC3_GPIO_D_BASE) {
438 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
439 gpio_base, offset);
440 return -EINVAL;
441 }
442
443 spin_lock_irqsave(&asic->lock, flags);
444
445 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
446
447
448 if (out)
449 out_reg |= mask;
450 else
451 out_reg &= ~mask;
452
453 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
454
455 spin_unlock_irqrestore(&asic->lock, flags);
456
457 return 0;
458
459}
460
461static int asic3_gpio_direction_input(struct gpio_chip *chip,
462 unsigned offset)
463{
464 return asic3_gpio_direction(chip, offset, 0);
465}
466
467static int asic3_gpio_direction_output(struct gpio_chip *chip,
468 unsigned offset, int value)
469{
470 return asic3_gpio_direction(chip, offset, 1);
471}
472
473static int asic3_gpio_get(struct gpio_chip *chip,
474 unsigned offset)
475{
476 unsigned int gpio_base;
477 u32 mask = ASIC3_GPIO_TO_MASK(offset);
478 struct asic3 *asic;
479
480 asic = container_of(chip, struct asic3, gpio);
481 gpio_base = ASIC3_GPIO_TO_BASE(offset);
482
483 if (gpio_base > ASIC3_GPIO_D_BASE) {
484 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
485 gpio_base, offset);
486 return -EINVAL;
487 }
488
489 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
490}
491
492static void asic3_gpio_set(struct gpio_chip *chip,
493 unsigned offset, int value)
494{
495 u32 mask, out_reg;
496 unsigned int gpio_base;
497 unsigned long flags;
498 struct asic3 *asic;
499
500 asic = container_of(chip, struct asic3, gpio);
501 gpio_base = ASIC3_GPIO_TO_BASE(offset);
502
503 if (gpio_base > ASIC3_GPIO_D_BASE) {
504 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
505 gpio_base, offset);
506 return;
507 }
508
509 mask = ASIC3_GPIO_TO_MASK(offset);
510
511 spin_lock_irqsave(&asic->lock, flags);
512
513 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
514
515 if (value)
516 out_reg |= mask;
517 else
518 out_reg &= ~mask;
519
520 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
521
522 spin_unlock_irqrestore(&asic->lock, flags);
523
524 return;
525}
526
527static __init int asic3_gpio_probe(struct platform_device *pdev,
528 u16 *gpio_config, int num)
529{
530 struct asic3 *asic = platform_get_drvdata(pdev);
531 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
532 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
533 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
534 int i;
535
536 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
537 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
538 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
539
540
541 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
542 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
543 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
544 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
545
546 for (i = 0; i < num; i++) {
547 u8 alt, pin, dir, init, bank_num, bit_num;
548 u16 config = gpio_config[i];
549
550 pin = ASIC3_CONFIG_GPIO_PIN(config);
551 alt = ASIC3_CONFIG_GPIO_ALT(config);
552 dir = ASIC3_CONFIG_GPIO_DIR(config);
553 init = ASIC3_CONFIG_GPIO_INIT(config);
554
555 bank_num = ASIC3_GPIO_TO_BANK(pin);
556 bit_num = ASIC3_GPIO_TO_BIT(pin);
557
558 alt_reg[bank_num] |= (alt << bit_num);
559 out_reg[bank_num] |= (init << bit_num);
560 dir_reg[bank_num] |= (dir << bit_num);
561 }
562
563 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
564 asic3_write_register(asic,
565 ASIC3_BANK_TO_BASE(i) +
566 ASIC3_GPIO_DIRECTION,
567 dir_reg[i]);
568 asic3_write_register(asic,
569 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
570 out_reg[i]);
571 asic3_write_register(asic,
572 ASIC3_BANK_TO_BASE(i) +
573 ASIC3_GPIO_ALT_FUNCTION,
574 alt_reg[i]);
575 }
576
577 return gpiochip_add(&asic->gpio);
578}
579
580static int asic3_gpio_remove(struct platform_device *pdev)
581{
582 struct asic3 *asic = platform_get_drvdata(pdev);
583
584 return gpiochip_remove(&asic->gpio);
585}
586
587static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
588{
589 unsigned long flags;
590 u32 cdex;
591
592 spin_lock_irqsave(&asic->lock, flags);
593 if (clk->enabled++ == 0) {
594 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
595 cdex |= clk->cdex;
596 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
597 }
598 spin_unlock_irqrestore(&asic->lock, flags);
599
600 return 0;
601}
602
603static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
604{
605 unsigned long flags;
606 u32 cdex;
607
608 WARN_ON(clk->enabled == 0);
609
610 spin_lock_irqsave(&asic->lock, flags);
611 if (--clk->enabled == 0) {
612 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
613 cdex &= ~clk->cdex;
614 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
615 }
616 spin_unlock_irqrestore(&asic->lock, flags);
617}
618
619
620static struct ds1wm_driver_data ds1wm_pdata = {
621 .active_high = 1,
622 .reset_recover_delay = 1,
623};
624
625static struct resource ds1wm_resources[] = {
626 {
627 .start = ASIC3_OWM_BASE,
628 .end = ASIC3_OWM_BASE + 0x13,
629 .flags = IORESOURCE_MEM,
630 },
631 {
632 .start = ASIC3_IRQ_OWM,
633 .end = ASIC3_IRQ_OWM,
634 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
635 },
636};
637
638static int ds1wm_enable(struct platform_device *pdev)
639{
640 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
641
642
643 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
644 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
645 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
646 msleep(1);
647
648
649 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
650 ASIC3_EXTCF_OWM_RESET, 1);
651 msleep(1);
652 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
653 ASIC3_EXTCF_OWM_RESET, 0);
654 msleep(1);
655 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
656 ASIC3_EXTCF_OWM_EN, 1);
657 msleep(1);
658
659 return 0;
660}
661
662static int ds1wm_disable(struct platform_device *pdev)
663{
664 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
665
666 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
667 ASIC3_EXTCF_OWM_EN, 0);
668
669 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
670 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
671 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
672
673 return 0;
674}
675
676static struct mfd_cell asic3_cell_ds1wm = {
677 .name = "ds1wm",
678 .enable = ds1wm_enable,
679 .disable = ds1wm_disable,
680 .platform_data = &ds1wm_pdata,
681 .pdata_size = sizeof(ds1wm_pdata),
682 .num_resources = ARRAY_SIZE(ds1wm_resources),
683 .resources = ds1wm_resources,
684};
685
686static void asic3_mmc_pwr(struct platform_device *pdev, int state)
687{
688 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
689
690 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
691}
692
693static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
694{
695 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
696
697 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
698}
699
700static struct tmio_mmc_data asic3_mmc_data = {
701 .hclk = 24576000,
702 .set_pwr = asic3_mmc_pwr,
703 .set_clk_div = asic3_mmc_clk_div,
704};
705
706static struct resource asic3_mmc_resources[] = {
707 {
708 .start = ASIC3_SD_CTRL_BASE,
709 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
710 .flags = IORESOURCE_MEM,
711 },
712 {
713 .start = 0,
714 .end = 0,
715 .flags = IORESOURCE_IRQ,
716 },
717};
718
719static int asic3_mmc_enable(struct platform_device *pdev)
720{
721 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
722
723
724 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
725 ASIC3_SDHWCTRL_LEVCD, 1);
726 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
727 ASIC3_SDHWCTRL_LEVWP, 1);
728 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
729 ASIC3_SDHWCTRL_SUSPEND, 0);
730 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
731 ASIC3_SDHWCTRL_PCLR, 0);
732
733 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
734
735
736
737 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
738 msleep(1);
739
740
741 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
742 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
743
744 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
745 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
746 msleep(1);
747
748 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
749 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
750
751
752 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
753 ASIC3_SDHWCTRL_SDPWR, 1);
754
755
756 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
757 ASIC3_SD_CTRL_BASE >> 1);
758
759 return 0;
760}
761
762static int asic3_mmc_disable(struct platform_device *pdev)
763{
764 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
765
766
767 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
768 ASIC3_SDHWCTRL_SUSPEND, 1);
769
770
771 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
772 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
773 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
774 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
775 return 0;
776}
777
778static struct mfd_cell asic3_cell_mmc = {
779 .name = "tmio-mmc",
780 .enable = asic3_mmc_enable,
781 .disable = asic3_mmc_disable,
782 .platform_data = &asic3_mmc_data,
783 .pdata_size = sizeof(asic3_mmc_data),
784 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
785 .resources = asic3_mmc_resources,
786};
787
788static const int clock_ledn[ASIC3_NUM_LEDS] = {
789 [0] = ASIC3_CLOCK_LED0,
790 [1] = ASIC3_CLOCK_LED1,
791 [2] = ASIC3_CLOCK_LED2,
792};
793
794static int asic3_leds_enable(struct platform_device *pdev)
795{
796 const struct mfd_cell *cell = mfd_get_cell(pdev);
797 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
798
799 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
800
801 return 0;
802}
803
804static int asic3_leds_disable(struct platform_device *pdev)
805{
806 const struct mfd_cell *cell = mfd_get_cell(pdev);
807 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
808
809 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
810
811 return 0;
812}
813
814static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
815 [0] = {
816 .name = "leds-asic3",
817 .id = 0,
818 .enable = asic3_leds_enable,
819 .disable = asic3_leds_disable,
820 },
821 [1] = {
822 .name = "leds-asic3",
823 .id = 1,
824 .enable = asic3_leds_enable,
825 .disable = asic3_leds_disable,
826 },
827 [2] = {
828 .name = "leds-asic3",
829 .id = 2,
830 .enable = asic3_leds_enable,
831 .disable = asic3_leds_disable,
832 },
833};
834
835static int __init asic3_mfd_probe(struct platform_device *pdev,
836 struct asic3_platform_data *pdata,
837 struct resource *mem)
838{
839 struct asic3 *asic = platform_get_drvdata(pdev);
840 struct resource *mem_sdio;
841 int irq, ret;
842
843 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
844 if (!mem_sdio)
845 dev_dbg(asic->dev, "no SDIO MEM resource\n");
846
847 irq = platform_get_irq(pdev, 1);
848 if (irq < 0)
849 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
850
851
852 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
853 ASIC3_EXTCF_OWM_SMB, 0);
854
855 ds1wm_resources[0].start >>= asic->bus_shift;
856 ds1wm_resources[0].end >>= asic->bus_shift;
857
858
859 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
860 mem_sdio->start,
861 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
862 if (!asic->tmio_cnf) {
863 ret = -ENOMEM;
864 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
865 goto out;
866 }
867 asic3_mmc_resources[0].start >>= asic->bus_shift;
868 asic3_mmc_resources[0].end >>= asic->bus_shift;
869
870 ret = mfd_add_devices(&pdev->dev, pdev->id,
871 &asic3_cell_ds1wm, 1, mem, asic->irq_base);
872 if (ret < 0)
873 goto out;
874
875 if (mem_sdio && (irq >= 0)) {
876 ret = mfd_add_devices(&pdev->dev, pdev->id,
877 &asic3_cell_mmc, 1, mem_sdio, irq);
878 if (ret < 0)
879 goto out;
880 }
881
882 if (pdata->leds) {
883 int i;
884
885 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
886 asic3_cell_leds[i].platform_data = &pdata->leds[i];
887 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
888 }
889 ret = mfd_add_devices(&pdev->dev, 0,
890 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0);
891 }
892
893 out:
894 return ret;
895}
896
897static void asic3_mfd_remove(struct platform_device *pdev)
898{
899 struct asic3 *asic = platform_get_drvdata(pdev);
900
901 mfd_remove_devices(&pdev->dev);
902 iounmap(asic->tmio_cnf);
903}
904
905
906static int __init asic3_probe(struct platform_device *pdev)
907{
908 struct asic3_platform_data *pdata = pdev->dev.platform_data;
909 struct asic3 *asic;
910 struct resource *mem;
911 unsigned long clksel;
912 int ret = 0;
913
914 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
915 if (asic == NULL) {
916 printk(KERN_ERR "kzalloc failed\n");
917 return -ENOMEM;
918 }
919
920 spin_lock_init(&asic->lock);
921 platform_set_drvdata(pdev, asic);
922 asic->dev = &pdev->dev;
923
924 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
925 if (!mem) {
926 ret = -ENOMEM;
927 dev_err(asic->dev, "no MEM resource\n");
928 goto out_free;
929 }
930
931 asic->mapping = ioremap(mem->start, resource_size(mem));
932 if (!asic->mapping) {
933 ret = -ENOMEM;
934 dev_err(asic->dev, "Couldn't ioremap\n");
935 goto out_free;
936 }
937
938 asic->irq_base = pdata->irq_base;
939
940
941 asic->bus_shift = 2 - (resource_size(mem) >> 12);
942
943 clksel = 0;
944 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
945
946 ret = asic3_irq_probe(pdev);
947 if (ret < 0) {
948 dev_err(asic->dev, "Couldn't probe IRQs\n");
949 goto out_unmap;
950 }
951
952 asic->gpio.base = pdata->gpio_base;
953 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
954 asic->gpio.get = asic3_gpio_get;
955 asic->gpio.set = asic3_gpio_set;
956 asic->gpio.direction_input = asic3_gpio_direction_input;
957 asic->gpio.direction_output = asic3_gpio_direction_output;
958
959 ret = asic3_gpio_probe(pdev,
960 pdata->gpio_config,
961 pdata->gpio_config_num);
962 if (ret < 0) {
963 dev_err(asic->dev, "GPIO probe failed\n");
964 goto out_irq;
965 }
966
967
968
969
970 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
971
972 asic3_mfd_probe(pdev, pdata, mem);
973
974 dev_info(asic->dev, "ASIC3 Core driver\n");
975
976 return 0;
977
978 out_irq:
979 asic3_irq_remove(pdev);
980
981 out_unmap:
982 iounmap(asic->mapping);
983
984 out_free:
985 kfree(asic);
986
987 return ret;
988}
989
990static int __devexit asic3_remove(struct platform_device *pdev)
991{
992 int ret;
993 struct asic3 *asic = platform_get_drvdata(pdev);
994
995 asic3_mfd_remove(pdev);
996
997 ret = asic3_gpio_remove(pdev);
998 if (ret < 0)
999 return ret;
1000 asic3_irq_remove(pdev);
1001
1002 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1003
1004 iounmap(asic->mapping);
1005
1006 kfree(asic);
1007
1008 return 0;
1009}
1010
1011static void asic3_shutdown(struct platform_device *pdev)
1012{
1013}
1014
1015static struct platform_driver asic3_device_driver = {
1016 .driver = {
1017 .name = "asic3",
1018 },
1019 .remove = __devexit_p(asic3_remove),
1020 .shutdown = asic3_shutdown,
1021};
1022
1023static int __init asic3_init(void)
1024{
1025 int retval = 0;
1026 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1027 return retval;
1028}
1029
1030subsys_initcall(asic3_init);
1031
