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29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
32#include <linux/types.h>
33
34struct e1000_hw;
35struct e1000_adapter;
36
37#include "defines.h"
38
39#define er32(reg) __er32(hw, E1000_##reg)
40#define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41#define e1e_flush() er32(STATUS)
42
43#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
45
46#define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) << 2)))
48
49enum e1e_registers {
50 E1000_CTRL = 0x00000,
51 E1000_STATUS = 0x00008,
52 E1000_EECD = 0x00010,
53 E1000_EERD = 0x00014,
54 E1000_CTRL_EXT = 0x00018,
55 E1000_FLA = 0x0001C,
56 E1000_MDIC = 0x00020,
57 E1000_SCTL = 0x00024,
58 E1000_FCAL = 0x00028,
59 E1000_FCAH = 0x0002C,
60 E1000_FEXTNVM4 = 0x00024,
61 E1000_FEXTNVM = 0x00028,
62 E1000_FCT = 0x00030,
63 E1000_VET = 0x00038,
64 E1000_ICR = 0x000C0,
65 E1000_ITR = 0x000C4,
66 E1000_ICS = 0x000C8,
67 E1000_IMS = 0x000D0,
68 E1000_IMC = 0x000D8,
69 E1000_EIAC_82574 = 0x000DC,
70 E1000_IAM = 0x000E0,
71 E1000_IVAR = 0x000E4,
72 E1000_EITR_82574_BASE = 0x000E8,
73#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
74 E1000_RCTL = 0x00100,
75 E1000_FCTTV = 0x00170,
76 E1000_TXCW = 0x00178,
77 E1000_RXCW = 0x00180,
78 E1000_TCTL = 0x00400,
79 E1000_TCTL_EXT = 0x00404,
80 E1000_TIPG = 0x00410,
81 E1000_AIT = 0x00458,
82 E1000_LEDCTL = 0x00E00,
83 E1000_EXTCNF_CTRL = 0x00F00,
84 E1000_EXTCNF_SIZE = 0x00F08,
85 E1000_PHY_CTRL = 0x00F10,
86#define E1000_POEMB E1000_PHY_CTRL
87 E1000_PBA = 0x01000,
88 E1000_PBS = 0x01008,
89 E1000_EEMNGCTL = 0x01010,
90 E1000_EEWR = 0x0102C,
91 E1000_FLOP = 0x0103C,
92 E1000_PBA_ECC = 0x01100,
93 E1000_ERT = 0x02008,
94 E1000_FCRTL = 0x02160,
95 E1000_FCRTH = 0x02168,
96 E1000_PSRCTL = 0x02170,
97 E1000_RDBAL = 0x02800,
98 E1000_RDBAH = 0x02804,
99 E1000_RDLEN = 0x02808,
100 E1000_RDH = 0x02810,
101 E1000_RDT = 0x02818,
102 E1000_RDTR = 0x02820,
103 E1000_RXDCTL_BASE = 0x02828,
104#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
105 E1000_RADV = 0x0282C,
106
107
108
109
110
111
112
113
114
115#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
116 E1000_KABGTXD = 0x03004,
117 E1000_TDBAL = 0x03800,
118 E1000_TDBAH = 0x03804,
119 E1000_TDLEN = 0x03808,
120 E1000_TDH = 0x03810,
121 E1000_TDT = 0x03818,
122 E1000_TIDV = 0x03820,
123 E1000_TXDCTL_BASE = 0x03828,
124#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
125 E1000_TADV = 0x0382C,
126 E1000_TARC_BASE = 0x03840,
127#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
128 E1000_CRCERRS = 0x04000,
129 E1000_ALGNERRC = 0x04004,
130 E1000_SYMERRS = 0x04008,
131 E1000_RXERRC = 0x0400C,
132 E1000_MPC = 0x04010,
133 E1000_SCC = 0x04014,
134 E1000_ECOL = 0x04018,
135 E1000_MCC = 0x0401C,
136 E1000_LATECOL = 0x04020,
137 E1000_COLC = 0x04028,
138 E1000_DC = 0x04030,
139 E1000_TNCRS = 0x04034,
140 E1000_SEC = 0x04038,
141 E1000_CEXTERR = 0x0403C,
142 E1000_RLEC = 0x04040,
143 E1000_XONRXC = 0x04048,
144 E1000_XONTXC = 0x0404C,
145 E1000_XOFFRXC = 0x04050,
146 E1000_XOFFTXC = 0x04054,
147 E1000_FCRUC = 0x04058,
148 E1000_PRC64 = 0x0405C,
149 E1000_PRC127 = 0x04060,
150 E1000_PRC255 = 0x04064,
151 E1000_PRC511 = 0x04068,
152 E1000_PRC1023 = 0x0406C,
153 E1000_PRC1522 = 0x04070,
154 E1000_GPRC = 0x04074,
155 E1000_BPRC = 0x04078,
156 E1000_MPRC = 0x0407C,
157 E1000_GPTC = 0x04080,
158 E1000_GORCL = 0x04088,
159 E1000_GORCH = 0x0408C,
160 E1000_GOTCL = 0x04090,
161 E1000_GOTCH = 0x04094,
162 E1000_RNBC = 0x040A0,
163 E1000_RUC = 0x040A4,
164 E1000_RFC = 0x040A8,
165 E1000_ROC = 0x040AC,
166 E1000_RJC = 0x040B0,
167 E1000_MGTPRC = 0x040B4,
168 E1000_MGTPDC = 0x040B8,
169 E1000_MGTPTC = 0x040BC,
170 E1000_TORL = 0x040C0,
171 E1000_TORH = 0x040C4,
172 E1000_TOTL = 0x040C8,
173 E1000_TOTH = 0x040CC,
174 E1000_TPR = 0x040D0,
175 E1000_TPT = 0x040D4,
176 E1000_PTC64 = 0x040D8,
177 E1000_PTC127 = 0x040DC,
178 E1000_PTC255 = 0x040E0,
179 E1000_PTC511 = 0x040E4,
180 E1000_PTC1023 = 0x040E8,
181 E1000_PTC1522 = 0x040EC,
182 E1000_MPTC = 0x040F0,
183 E1000_BPTC = 0x040F4,
184 E1000_TSCTC = 0x040F8,
185 E1000_TSCTFC = 0x040FC,
186 E1000_IAC = 0x04100,
187 E1000_ICRXPTC = 0x04104,
188 E1000_ICRXATC = 0x04108,
189 E1000_ICTXPTC = 0x0410C,
190 E1000_ICTXATC = 0x04110,
191 E1000_ICTXQEC = 0x04118,
192 E1000_ICTXQMTC = 0x0411C,
193 E1000_ICRXDMTC = 0x04120,
194 E1000_ICRXOC = 0x04124,
195 E1000_RXCSUM = 0x05000,
196 E1000_RFCTL = 0x05008,
197 E1000_MTA = 0x05200,
198 E1000_RAL_BASE = 0x05400,
199#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
200#define E1000_RA (E1000_RAL(0))
201 E1000_RAH_BASE = 0x05404,
202#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
203 E1000_VFTA = 0x05600,
204 E1000_WUC = 0x05800,
205 E1000_WUFC = 0x05808,
206 E1000_WUS = 0x05810,
207 E1000_MANC = 0x05820,
208 E1000_FFLT = 0x05F00,
209 E1000_HOST_IF = 0x08800,
210
211 E1000_KMRNCTRLSTA = 0x00034,
212 E1000_MANC2H = 0x05860,
213 E1000_MDEF_BASE = 0x05890,
214#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
215 E1000_SW_FW_SYNC = 0x05B5C,
216 E1000_GCR = 0x05B00,
217 E1000_GCR2 = 0x05B64,
218 E1000_FACTPS = 0x05B30,
219 E1000_SWSM = 0x05B50,
220 E1000_FWSM = 0x05B54,
221 E1000_SWSM2 = 0x05B58,
222 E1000_FFLT_DBG = 0x05F04,
223 E1000_PCH_RAICC_BASE = 0x05F50,
224#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
225#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
226 E1000_HICR = 0x08F00,
227};
228
229#define E1000_MAX_PHY_ADDR 4
230
231
232#define IGP01E1000_PHY_PORT_CONFIG 0x10
233#define IGP01E1000_PHY_PORT_STATUS 0x11
234#define IGP01E1000_PHY_PORT_CTRL 0x12
235#define IGP01E1000_PHY_LINK_HEALTH 0x13
236#define IGP02E1000_PHY_POWER_MGMT 0x19
237#define IGP01E1000_PHY_PAGE_SELECT 0x1F
238#define BM_PHY_PAGE_SELECT 22
239#define IGP_PAGE_SHIFT 5
240#define PHY_REG_MASK 0x1F
241
242#define BM_WUC_PAGE 800
243#define BM_WUC_ADDRESS_OPCODE 0x11
244#define BM_WUC_DATA_OPCODE 0x12
245#define BM_WUC_ENABLE_PAGE 769
246#define BM_WUC_ENABLE_REG 17
247#define BM_WUC_ENABLE_BIT (1 << 2)
248#define BM_WUC_HOST_WU_BIT (1 << 4)
249#define BM_WUC_ME_WU_BIT (1 << 5)
250
251#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
252#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
253#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
254
255#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
256#define IGP01E1000_PHY_POLARITY_MASK 0x0078
257
258#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
259#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000
260
261#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
262
263#define IGP02E1000_PM_SPD 0x0001
264#define IGP02E1000_PM_D0_LPLU 0x0002
265#define IGP02E1000_PM_D3_LPLU 0x0004
266
267#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
268
269#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
270#define IGP01E1000_PSSR_MDIX 0x0800
271#define IGP01E1000_PSSR_SPEED_MASK 0xC000
272#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
273
274#define IGP02E1000_PHY_CHANNEL_NUM 4
275#define IGP02E1000_PHY_AGC_A 0x11B1
276#define IGP02E1000_PHY_AGC_B 0x12B1
277#define IGP02E1000_PHY_AGC_C 0x14B1
278#define IGP02E1000_PHY_AGC_D 0x18B1
279
280#define IGP02E1000_AGC_LENGTH_SHIFT 9
281#define IGP02E1000_AGC_LENGTH_MASK 0x7F
282#define IGP02E1000_AGC_RANGE 15
283
284
285#define E1000_VFTA_ENTRY_SHIFT 5
286#define E1000_VFTA_ENTRY_MASK 0x7F
287#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
288
289#define E1000_HICR_EN 0x01
290
291#define E1000_HICR_C 0x02
292#define E1000_HICR_FW_RESET_ENABLE 0x40
293#define E1000_HICR_FW_RESET 0x80
294
295#define E1000_FWSM_MODE_MASK 0xE
296#define E1000_FWSM_MODE_SHIFT 1
297
298#define E1000_MNG_IAMT_MODE 0x3
299#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
300#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
301#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
302#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
303#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
304#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
305
306
307#define E1000_STM_OPCODE 0xDB00
308
309#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
310#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
311#define E1000_KMRNCTRLSTA_REN 0x00200000
312#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1
313#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3
314#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4
315#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9
316#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200
317#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000
318#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
319#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
320#define E1000_KMRNCTRLSTA_HD_CTRL 0x10
321
322#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
323#define IFE_PHY_SPECIAL_CONTROL 0x11
324#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B
325#define IFE_PHY_MDIX_CONTROL 0x1C
326
327
328#define IFE_PESC_POLARITY_REVERSED 0x0100
329
330
331#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
332#define IFE_PSC_FORCE_POLARITY 0x0020
333
334
335#define IFE_PSCL_PROBE_MODE 0x0020
336#define IFE_PSCL_PROBE_LEDS_OFF 0x0006
337#define IFE_PSCL_PROBE_LEDS_ON 0x0007
338
339
340#define IFE_PMC_MDIX_STATUS 0x0020
341#define IFE_PMC_FORCE_MDIX 0x0040
342#define IFE_PMC_AUTO_MDIX 0x0080
343
344#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
345
346#define E1000_DEV_ID_82571EB_COPPER 0x105E
347#define E1000_DEV_ID_82571EB_FIBER 0x105F
348#define E1000_DEV_ID_82571EB_SERDES 0x1060
349#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
350#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
351#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
352#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
353#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
354#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
355#define E1000_DEV_ID_82572EI_COPPER 0x107D
356#define E1000_DEV_ID_82572EI_FIBER 0x107E
357#define E1000_DEV_ID_82572EI_SERDES 0x107F
358#define E1000_DEV_ID_82572EI 0x10B9
359#define E1000_DEV_ID_82573E 0x108B
360#define E1000_DEV_ID_82573E_IAMT 0x108C
361#define E1000_DEV_ID_82573L 0x109A
362#define E1000_DEV_ID_82574L 0x10D3
363#define E1000_DEV_ID_82574LA 0x10F6
364#define E1000_DEV_ID_82583V 0x150C
365
366#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
367#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
368#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
369#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
370
371#define E1000_DEV_ID_ICH8_82567V_3 0x1501
372#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
373#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
374#define E1000_DEV_ID_ICH8_IGP_C 0x104B
375#define E1000_DEV_ID_ICH8_IFE 0x104C
376#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
377#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
378#define E1000_DEV_ID_ICH8_IGP_M 0x104D
379#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
380#define E1000_DEV_ID_ICH9_BM 0x10E5
381#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
382#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
383#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
384#define E1000_DEV_ID_ICH9_IGP_C 0x294C
385#define E1000_DEV_ID_ICH9_IFE 0x10C0
386#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
387#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
388#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
389#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
390#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
391#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
392#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
393#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
394#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
395#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
396#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
397#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
398#define E1000_DEV_ID_PCH2_LV_LM 0x1502
399#define E1000_DEV_ID_PCH2_LV_V 0x1503
400
401#define E1000_REVISION_4 4
402
403#define E1000_FUNC_1 1
404
405#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
406#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
407
408enum e1000_mac_type {
409 e1000_82571,
410 e1000_82572,
411 e1000_82573,
412 e1000_82574,
413 e1000_82583,
414 e1000_80003es2lan,
415 e1000_ich8lan,
416 e1000_ich9lan,
417 e1000_ich10lan,
418 e1000_pchlan,
419 e1000_pch2lan,
420};
421
422enum e1000_media_type {
423 e1000_media_type_unknown = 0,
424 e1000_media_type_copper = 1,
425 e1000_media_type_fiber = 2,
426 e1000_media_type_internal_serdes = 3,
427 e1000_num_media_types
428};
429
430enum e1000_nvm_type {
431 e1000_nvm_unknown = 0,
432 e1000_nvm_none,
433 e1000_nvm_eeprom_spi,
434 e1000_nvm_flash_hw,
435 e1000_nvm_flash_sw
436};
437
438enum e1000_nvm_override {
439 e1000_nvm_override_none = 0,
440 e1000_nvm_override_spi_small,
441 e1000_nvm_override_spi_large
442};
443
444enum e1000_phy_type {
445 e1000_phy_unknown = 0,
446 e1000_phy_none,
447 e1000_phy_m88,
448 e1000_phy_igp,
449 e1000_phy_igp_2,
450 e1000_phy_gg82563,
451 e1000_phy_igp_3,
452 e1000_phy_ife,
453 e1000_phy_bm,
454 e1000_phy_82578,
455 e1000_phy_82577,
456 e1000_phy_82579,
457};
458
459enum e1000_bus_width {
460 e1000_bus_width_unknown = 0,
461 e1000_bus_width_pcie_x1,
462 e1000_bus_width_pcie_x2,
463 e1000_bus_width_pcie_x4 = 4,
464 e1000_bus_width_32,
465 e1000_bus_width_64,
466 e1000_bus_width_reserved
467};
468
469enum e1000_1000t_rx_status {
470 e1000_1000t_rx_status_not_ok = 0,
471 e1000_1000t_rx_status_ok,
472 e1000_1000t_rx_status_undefined = 0xFF
473};
474
475enum e1000_rev_polarity{
476 e1000_rev_polarity_normal = 0,
477 e1000_rev_polarity_reversed,
478 e1000_rev_polarity_undefined = 0xFF
479};
480
481enum e1000_fc_mode {
482 e1000_fc_none = 0,
483 e1000_fc_rx_pause,
484 e1000_fc_tx_pause,
485 e1000_fc_full,
486 e1000_fc_default = 0xFF
487};
488
489enum e1000_ms_type {
490 e1000_ms_hw_default = 0,
491 e1000_ms_force_master,
492 e1000_ms_force_slave,
493 e1000_ms_auto
494};
495
496enum e1000_smart_speed {
497 e1000_smart_speed_default = 0,
498 e1000_smart_speed_on,
499 e1000_smart_speed_off
500};
501
502enum e1000_serdes_link_state {
503 e1000_serdes_link_down = 0,
504 e1000_serdes_link_autoneg_progress,
505 e1000_serdes_link_autoneg_complete,
506 e1000_serdes_link_forced_up
507};
508
509
510struct e1000_rx_desc {
511 __le64 buffer_addr;
512 __le16 length;
513 __le16 csum;
514 u8 status;
515 u8 errors;
516 __le16 special;
517};
518
519
520union e1000_rx_desc_extended {
521 struct {
522 __le64 buffer_addr;
523 __le64 reserved;
524 } read;
525 struct {
526 struct {
527 __le32 mrq;
528 union {
529 __le32 rss;
530 struct {
531 __le16 ip_id;
532 __le16 csum;
533 } csum_ip;
534 } hi_dword;
535 } lower;
536 struct {
537 __le32 status_error;
538 __le16 length;
539 __le16 vlan;
540 } upper;
541 } wb;
542};
543
544#define MAX_PS_BUFFERS 4
545
546union e1000_rx_desc_packet_split {
547 struct {
548
549 __le64 buffer_addr[MAX_PS_BUFFERS];
550 } read;
551 struct {
552 struct {
553 __le32 mrq;
554 union {
555 __le32 rss;
556 struct {
557 __le16 ip_id;
558 __le16 csum;
559 } csum_ip;
560 } hi_dword;
561 } lower;
562 struct {
563 __le32 status_error;
564 __le16 length0;
565 __le16 vlan;
566 } middle;
567 struct {
568 __le16 header_status;
569 __le16 length[3];
570 } upper;
571 __le64 reserved;
572 } wb;
573};
574
575
576struct e1000_tx_desc {
577 __le64 buffer_addr;
578 union {
579 __le32 data;
580 struct {
581 __le16 length;
582 u8 cso;
583 u8 cmd;
584 } flags;
585 } lower;
586 union {
587 __le32 data;
588 struct {
589 u8 status;
590 u8 css;
591 __le16 special;
592 } fields;
593 } upper;
594};
595
596
597struct e1000_context_desc {
598 union {
599 __le32 ip_config;
600 struct {
601 u8 ipcss;
602 u8 ipcso;
603 __le16 ipcse;
604 } ip_fields;
605 } lower_setup;
606 union {
607 __le32 tcp_config;
608 struct {
609 u8 tucss;
610 u8 tucso;
611 __le16 tucse;
612 } tcp_fields;
613 } upper_setup;
614 __le32 cmd_and_length;
615 union {
616 __le32 data;
617 struct {
618 u8 status;
619 u8 hdr_len;
620 __le16 mss;
621 } fields;
622 } tcp_seg_setup;
623};
624
625
626struct e1000_data_desc {
627 __le64 buffer_addr;
628 union {
629 __le32 data;
630 struct {
631 __le16 length;
632 u8 typ_len_ext;
633 u8 cmd;
634 } flags;
635 } lower;
636 union {
637 __le32 data;
638 struct {
639 u8 status;
640 u8 popts;
641 __le16 special;
642 } fields;
643 } upper;
644};
645
646
647struct e1000_hw_stats {
648 u64 crcerrs;
649 u64 algnerrc;
650 u64 symerrs;
651 u64 rxerrc;
652 u64 mpc;
653 u64 scc;
654 u64 ecol;
655 u64 mcc;
656 u64 latecol;
657 u64 colc;
658 u64 dc;
659 u64 tncrs;
660 u64 sec;
661 u64 cexterr;
662 u64 rlec;
663 u64 xonrxc;
664 u64 xontxc;
665 u64 xoffrxc;
666 u64 xofftxc;
667 u64 fcruc;
668 u64 prc64;
669 u64 prc127;
670 u64 prc255;
671 u64 prc511;
672 u64 prc1023;
673 u64 prc1522;
674 u64 gprc;
675 u64 bprc;
676 u64 mprc;
677 u64 gptc;
678 u64 gorc;
679 u64 gotc;
680 u64 rnbc;
681 u64 ruc;
682 u64 rfc;
683 u64 roc;
684 u64 rjc;
685 u64 mgprc;
686 u64 mgpdc;
687 u64 mgptc;
688 u64 tor;
689 u64 tot;
690 u64 tpr;
691 u64 tpt;
692 u64 ptc64;
693 u64 ptc127;
694 u64 ptc255;
695 u64 ptc511;
696 u64 ptc1023;
697 u64 ptc1522;
698 u64 mptc;
699 u64 bptc;
700 u64 tsctc;
701 u64 tsctfc;
702 u64 iac;
703 u64 icrxptc;
704 u64 icrxatc;
705 u64 ictxptc;
706 u64 ictxatc;
707 u64 ictxqec;
708 u64 ictxqmtc;
709 u64 icrxdmtc;
710 u64 icrxoc;
711};
712
713struct e1000_phy_stats {
714 u32 idle_errors;
715 u32 receive_errors;
716};
717
718struct e1000_host_mng_dhcp_cookie {
719 u32 signature;
720 u8 status;
721 u8 reserved0;
722 u16 vlan_id;
723 u32 reserved1;
724 u16 reserved2;
725 u8 reserved3;
726 u8 checksum;
727};
728
729
730struct e1000_host_command_header {
731 u8 command_id;
732 u8 command_length;
733 u8 command_options;
734 u8 checksum;
735};
736
737#define E1000_HI_MAX_DATA_LENGTH 252
738struct e1000_host_command_info {
739 struct e1000_host_command_header command_header;
740 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
741};
742
743
744struct e1000_host_mng_command_header {
745 u8 command_id;
746 u8 checksum;
747 u16 reserved1;
748 u16 reserved2;
749 u16 command_length;
750};
751
752#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
753struct e1000_host_mng_command_info {
754 struct e1000_host_mng_command_header command_header;
755 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
756};
757
758
759struct e1000_mac_operations {
760 s32 (*id_led_init)(struct e1000_hw *);
761 s32 (*blink_led)(struct e1000_hw *);
762 bool (*check_mng_mode)(struct e1000_hw *);
763 s32 (*check_for_link)(struct e1000_hw *);
764 s32 (*cleanup_led)(struct e1000_hw *);
765 void (*clear_hw_cntrs)(struct e1000_hw *);
766 void (*clear_vfta)(struct e1000_hw *);
767 s32 (*get_bus_info)(struct e1000_hw *);
768 void (*set_lan_id)(struct e1000_hw *);
769 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
770 s32 (*led_on)(struct e1000_hw *);
771 s32 (*led_off)(struct e1000_hw *);
772 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
773 s32 (*reset_hw)(struct e1000_hw *);
774 s32 (*init_hw)(struct e1000_hw *);
775 s32 (*setup_link)(struct e1000_hw *);
776 s32 (*setup_physical_interface)(struct e1000_hw *);
777 s32 (*setup_led)(struct e1000_hw *);
778 void (*write_vfta)(struct e1000_hw *, u32, u32);
779 s32 (*read_mac_addr)(struct e1000_hw *);
780};
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797struct e1000_phy_operations {
798 s32 (*acquire)(struct e1000_hw *);
799 s32 (*cfg_on_link_up)(struct e1000_hw *);
800 s32 (*check_polarity)(struct e1000_hw *);
801 s32 (*check_reset_block)(struct e1000_hw *);
802 s32 (*commit)(struct e1000_hw *);
803 s32 (*force_speed_duplex)(struct e1000_hw *);
804 s32 (*get_cfg_done)(struct e1000_hw *hw);
805 s32 (*get_cable_length)(struct e1000_hw *);
806 s32 (*get_info)(struct e1000_hw *);
807 s32 (*set_page)(struct e1000_hw *, u16);
808 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
809 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
810 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
811 void (*release)(struct e1000_hw *);
812 s32 (*reset)(struct e1000_hw *);
813 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
814 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
815 s32 (*write_reg)(struct e1000_hw *, u32, u16);
816 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
817 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
818 void (*power_up)(struct e1000_hw *);
819 void (*power_down)(struct e1000_hw *);
820};
821
822
823struct e1000_nvm_operations {
824 s32 (*acquire)(struct e1000_hw *);
825 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
826 void (*release)(struct e1000_hw *);
827 s32 (*update)(struct e1000_hw *);
828 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
829 s32 (*validate)(struct e1000_hw *);
830 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
831};
832
833struct e1000_mac_info {
834 struct e1000_mac_operations ops;
835 u8 addr[ETH_ALEN];
836 u8 perm_addr[ETH_ALEN];
837
838 enum e1000_mac_type type;
839
840 u32 collision_delta;
841 u32 ledctl_default;
842 u32 ledctl_mode1;
843 u32 ledctl_mode2;
844 u32 mc_filter_type;
845 u32 tx_packet_delta;
846 u32 txcw;
847
848 u16 current_ifs_val;
849 u16 ifs_max_val;
850 u16 ifs_min_val;
851 u16 ifs_ratio;
852 u16 ifs_step_size;
853 u16 mta_reg_count;
854
855
856 #define MAX_MTA_REG 128
857 u32 mta_shadow[MAX_MTA_REG];
858 u16 rar_entry_count;
859
860 u8 forced_speed_duplex;
861
862 bool adaptive_ifs;
863 bool has_fwsm;
864 bool arc_subsystem_valid;
865 bool autoneg;
866 bool autoneg_failed;
867 bool get_link_status;
868 bool in_ifs_mode;
869 bool serdes_has_link;
870 bool tx_pkt_filtering;
871 enum e1000_serdes_link_state serdes_link_state;
872};
873
874struct e1000_phy_info {
875 struct e1000_phy_operations ops;
876
877 enum e1000_phy_type type;
878
879 enum e1000_1000t_rx_status local_rx;
880 enum e1000_1000t_rx_status remote_rx;
881 enum e1000_ms_type ms_type;
882 enum e1000_ms_type original_ms_type;
883 enum e1000_rev_polarity cable_polarity;
884 enum e1000_smart_speed smart_speed;
885
886 u32 addr;
887 u32 id;
888 u32 reset_delay_us;
889 u32 revision;
890
891 enum e1000_media_type media_type;
892
893 u16 autoneg_advertised;
894 u16 autoneg_mask;
895 u16 cable_length;
896 u16 max_cable_length;
897 u16 min_cable_length;
898
899 u8 mdix;
900
901 bool disable_polarity_correction;
902 bool is_mdix;
903 bool polarity_correction;
904 bool speed_downgraded;
905 bool autoneg_wait_to_complete;
906};
907
908struct e1000_nvm_info {
909 struct e1000_nvm_operations ops;
910
911 enum e1000_nvm_type type;
912 enum e1000_nvm_override override;
913
914 u32 flash_bank_size;
915 u32 flash_base_addr;
916
917 u16 word_size;
918 u16 delay_usec;
919 u16 address_bits;
920 u16 opcode_bits;
921 u16 page_size;
922};
923
924struct e1000_bus_info {
925 enum e1000_bus_width width;
926
927 u16 func;
928};
929
930struct e1000_fc_info {
931 u32 high_water;
932 u32 low_water;
933 u16 pause_time;
934 u16 refresh_time;
935 bool send_xon;
936 bool strict_ieee;
937 enum e1000_fc_mode current_mode;
938 enum e1000_fc_mode requested_mode;
939};
940
941struct e1000_dev_spec_82571 {
942 bool laa_is_present;
943 u32 smb_counter;
944};
945
946struct e1000_dev_spec_80003es2lan {
947 bool mdic_wa_enable;
948};
949
950struct e1000_shadow_ram {
951 u16 value;
952 bool modified;
953};
954
955#define E1000_ICH8_SHADOW_RAM_WORDS 2048
956
957struct e1000_dev_spec_ich8lan {
958 bool kmrn_lock_loss_workaround_enabled;
959 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
960 bool nvm_k1_enabled;
961 bool eee_disable;
962};
963
964struct e1000_hw {
965 struct e1000_adapter *adapter;
966
967 u8 __iomem *hw_addr;
968 u8 __iomem *flash_address;
969
970 struct e1000_mac_info mac;
971 struct e1000_fc_info fc;
972 struct e1000_phy_info phy;
973 struct e1000_nvm_info nvm;
974 struct e1000_bus_info bus;
975 struct e1000_host_mng_dhcp_cookie mng_cookie;
976
977 union {
978 struct e1000_dev_spec_82571 e82571;
979 struct e1000_dev_spec_80003es2lan e80003es2lan;
980 struct e1000_dev_spec_ich8lan ich8lan;
981 } dev_spec;
982};
983
984#endif
985