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28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31#include <linux/netdevice.h>
32
33#include "ixgbe.h"
34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
48
49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
50static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
51static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
52static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
53static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
54static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
58static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
61 u16 words, u16 *data);
62static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 u16 offset);
64
65
66
67
68
69
70
71
72
73
74s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
75{
76 u32 ctrl_ext;
77
78
79 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
80
81
82 hw->phy.ops.identify(hw);
83
84
85 hw->mac.ops.clear_vfta(hw);
86
87
88 hw->mac.ops.clear_hw_cntrs(hw);
89
90
91 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
92 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
93 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
94 IXGBE_WRITE_FLUSH(hw);
95
96
97 ixgbe_setup_fc(hw, 0);
98
99
100 hw->adapter_stopped = false;
101
102 return 0;
103}
104
105
106
107
108
109
110
111
112
113
114
115s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
116{
117 u32 i;
118 u32 regval;
119
120
121 for (i = 0; i < hw->mac.max_tx_queues; i++) {
122 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
123 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
124 }
125 IXGBE_WRITE_FLUSH(hw);
126
127
128 for (i = 0; i < hw->mac.max_tx_queues; i++) {
129 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
130 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
131 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
132 }
133
134 for (i = 0; i < hw->mac.max_rx_queues; i++) {
135 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
136 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
137 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
138 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
139 }
140
141 return 0;
142}
143
144
145
146
147
148
149
150
151
152
153
154s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
155{
156 s32 status;
157
158
159 status = hw->mac.ops.reset_hw(hw);
160
161 if (status == 0) {
162
163 status = hw->mac.ops.start_hw(hw);
164 }
165
166 return status;
167}
168
169
170
171
172
173
174
175
176s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
177{
178 u16 i = 0;
179
180 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
181 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
182 IXGBE_READ_REG(hw, IXGBE_ERRBC);
183 IXGBE_READ_REG(hw, IXGBE_MSPDC);
184 for (i = 0; i < 8; i++)
185 IXGBE_READ_REG(hw, IXGBE_MPC(i));
186
187 IXGBE_READ_REG(hw, IXGBE_MLFC);
188 IXGBE_READ_REG(hw, IXGBE_MRFC);
189 IXGBE_READ_REG(hw, IXGBE_RLEC);
190 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
191 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
192 if (hw->mac.type >= ixgbe_mac_82599EB) {
193 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
194 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
195 } else {
196 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
197 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
198 }
199
200 for (i = 0; i < 8; i++) {
201 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
202 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
203 if (hw->mac.type >= ixgbe_mac_82599EB) {
204 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
205 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
206 } else {
207 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
208 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
209 }
210 }
211 if (hw->mac.type >= ixgbe_mac_82599EB)
212 for (i = 0; i < 8; i++)
213 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
214 IXGBE_READ_REG(hw, IXGBE_PRC64);
215 IXGBE_READ_REG(hw, IXGBE_PRC127);
216 IXGBE_READ_REG(hw, IXGBE_PRC255);
217 IXGBE_READ_REG(hw, IXGBE_PRC511);
218 IXGBE_READ_REG(hw, IXGBE_PRC1023);
219 IXGBE_READ_REG(hw, IXGBE_PRC1522);
220 IXGBE_READ_REG(hw, IXGBE_GPRC);
221 IXGBE_READ_REG(hw, IXGBE_BPRC);
222 IXGBE_READ_REG(hw, IXGBE_MPRC);
223 IXGBE_READ_REG(hw, IXGBE_GPTC);
224 IXGBE_READ_REG(hw, IXGBE_GORCL);
225 IXGBE_READ_REG(hw, IXGBE_GORCH);
226 IXGBE_READ_REG(hw, IXGBE_GOTCL);
227 IXGBE_READ_REG(hw, IXGBE_GOTCH);
228 for (i = 0; i < 8; i++)
229 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
230 IXGBE_READ_REG(hw, IXGBE_RUC);
231 IXGBE_READ_REG(hw, IXGBE_RFC);
232 IXGBE_READ_REG(hw, IXGBE_ROC);
233 IXGBE_READ_REG(hw, IXGBE_RJC);
234 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
235 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
236 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
237 IXGBE_READ_REG(hw, IXGBE_TORL);
238 IXGBE_READ_REG(hw, IXGBE_TORH);
239 IXGBE_READ_REG(hw, IXGBE_TPR);
240 IXGBE_READ_REG(hw, IXGBE_TPT);
241 IXGBE_READ_REG(hw, IXGBE_PTC64);
242 IXGBE_READ_REG(hw, IXGBE_PTC127);
243 IXGBE_READ_REG(hw, IXGBE_PTC255);
244 IXGBE_READ_REG(hw, IXGBE_PTC511);
245 IXGBE_READ_REG(hw, IXGBE_PTC1023);
246 IXGBE_READ_REG(hw, IXGBE_PTC1522);
247 IXGBE_READ_REG(hw, IXGBE_MPTC);
248 IXGBE_READ_REG(hw, IXGBE_BPTC);
249 for (i = 0; i < 16; i++) {
250 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
251 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
252 if (hw->mac.type >= ixgbe_mac_82599EB) {
253 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
254 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
255 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
256 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
257 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
258 } else {
259 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
260 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
261 }
262 }
263
264 if (hw->mac.type == ixgbe_mac_X540) {
265 if (hw->phy.id == 0)
266 hw->phy.ops.identify(hw);
267 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i);
268 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i);
269 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i);
270 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i);
271 }
272
273 return 0;
274}
275
276
277
278
279
280
281
282
283
284s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
285 u32 pba_num_size)
286{
287 s32 ret_val;
288 u16 data;
289 u16 pba_ptr;
290 u16 offset;
291 u16 length;
292
293 if (pba_num == NULL) {
294 hw_dbg(hw, "PBA string buffer was null\n");
295 return IXGBE_ERR_INVALID_ARGUMENT;
296 }
297
298 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
299 if (ret_val) {
300 hw_dbg(hw, "NVM Read Error\n");
301 return ret_val;
302 }
303
304 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
305 if (ret_val) {
306 hw_dbg(hw, "NVM Read Error\n");
307 return ret_val;
308 }
309
310
311
312
313
314
315 if (data != IXGBE_PBANUM_PTR_GUARD) {
316 hw_dbg(hw, "NVM PBA number is not stored as string\n");
317
318
319 if (pba_num_size < 11) {
320 hw_dbg(hw, "PBA string buffer too small\n");
321 return IXGBE_ERR_NO_SPACE;
322 }
323
324
325 pba_num[0] = (data >> 12) & 0xF;
326 pba_num[1] = (data >> 8) & 0xF;
327 pba_num[2] = (data >> 4) & 0xF;
328 pba_num[3] = data & 0xF;
329 pba_num[4] = (pba_ptr >> 12) & 0xF;
330 pba_num[5] = (pba_ptr >> 8) & 0xF;
331 pba_num[6] = '-';
332 pba_num[7] = 0;
333 pba_num[8] = (pba_ptr >> 4) & 0xF;
334 pba_num[9] = pba_ptr & 0xF;
335
336
337 pba_num[10] = '\0';
338
339
340 for (offset = 0; offset < 10; offset++) {
341 if (pba_num[offset] < 0xA)
342 pba_num[offset] += '0';
343 else if (pba_num[offset] < 0x10)
344 pba_num[offset] += 'A' - 0xA;
345 }
346
347 return 0;
348 }
349
350 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
351 if (ret_val) {
352 hw_dbg(hw, "NVM Read Error\n");
353 return ret_val;
354 }
355
356 if (length == 0xFFFF || length == 0) {
357 hw_dbg(hw, "NVM PBA number section invalid length\n");
358 return IXGBE_ERR_PBA_SECTION;
359 }
360
361
362 if (pba_num_size < (((u32)length * 2) - 1)) {
363 hw_dbg(hw, "PBA string buffer too small\n");
364 return IXGBE_ERR_NO_SPACE;
365 }
366
367
368 pba_ptr++;
369 length--;
370
371 for (offset = 0; offset < length; offset++) {
372 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
373 if (ret_val) {
374 hw_dbg(hw, "NVM Read Error\n");
375 return ret_val;
376 }
377 pba_num[offset * 2] = (u8)(data >> 8);
378 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
379 }
380 pba_num[offset * 2] = '\0';
381
382 return 0;
383}
384
385
386
387
388
389
390
391
392
393
394s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
395{
396 u32 rar_high;
397 u32 rar_low;
398 u16 i;
399
400 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
401 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
402
403 for (i = 0; i < 4; i++)
404 mac_addr[i] = (u8)(rar_low >> (i*8));
405
406 for (i = 0; i < 2; i++)
407 mac_addr[i+4] = (u8)(rar_high >> (i*8));
408
409 return 0;
410}
411
412
413
414
415
416
417
418s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
419{
420 struct ixgbe_adapter *adapter = hw->back;
421 struct ixgbe_mac_info *mac = &hw->mac;
422 u16 link_status;
423
424 hw->bus.type = ixgbe_bus_type_pci_express;
425
426
427 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
428 &link_status);
429
430 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
431 case IXGBE_PCI_LINK_WIDTH_1:
432 hw->bus.width = ixgbe_bus_width_pcie_x1;
433 break;
434 case IXGBE_PCI_LINK_WIDTH_2:
435 hw->bus.width = ixgbe_bus_width_pcie_x2;
436 break;
437 case IXGBE_PCI_LINK_WIDTH_4:
438 hw->bus.width = ixgbe_bus_width_pcie_x4;
439 break;
440 case IXGBE_PCI_LINK_WIDTH_8:
441 hw->bus.width = ixgbe_bus_width_pcie_x8;
442 break;
443 default:
444 hw->bus.width = ixgbe_bus_width_unknown;
445 break;
446 }
447
448 switch (link_status & IXGBE_PCI_LINK_SPEED) {
449 case IXGBE_PCI_LINK_SPEED_2500:
450 hw->bus.speed = ixgbe_bus_speed_2500;
451 break;
452 case IXGBE_PCI_LINK_SPEED_5000:
453 hw->bus.speed = ixgbe_bus_speed_5000;
454 break;
455 default:
456 hw->bus.speed = ixgbe_bus_speed_unknown;
457 break;
458 }
459
460 mac->ops.set_lan_id(hw);
461
462 return 0;
463}
464
465
466
467
468
469
470
471
472void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
473{
474 struct ixgbe_bus_info *bus = &hw->bus;
475 u32 reg;
476
477 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
478 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
479 bus->lan_id = bus->func;
480
481
482 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
483 if (reg & IXGBE_FACTPS_LFS)
484 bus->func ^= 0x1;
485}
486
487
488
489
490
491
492
493
494
495
496s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
497{
498 u32 number_of_queues;
499 u32 reg_val;
500 u16 i;
501
502
503
504
505
506 hw->adapter_stopped = true;
507
508
509 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
510 reg_val &= ~(IXGBE_RXCTRL_RXEN);
511 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
512 IXGBE_WRITE_FLUSH(hw);
513 usleep_range(2000, 4000);
514
515
516 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
517
518
519 IXGBE_READ_REG(hw, IXGBE_EICR);
520
521
522 number_of_queues = hw->mac.max_tx_queues;
523 for (i = 0; i < number_of_queues; i++) {
524 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
525 if (reg_val & IXGBE_TXDCTL_ENABLE) {
526 reg_val &= ~IXGBE_TXDCTL_ENABLE;
527 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
528 }
529 }
530
531
532
533
534
535 ixgbe_disable_pcie_master(hw);
536
537 return 0;
538}
539
540
541
542
543
544
545s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
546{
547 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
548
549
550 led_reg &= ~IXGBE_LED_MODE_MASK(index);
551 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
552 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
553 IXGBE_WRITE_FLUSH(hw);
554
555 return 0;
556}
557
558
559
560
561
562
563s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
564{
565 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
566
567
568 led_reg &= ~IXGBE_LED_MODE_MASK(index);
569 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
570 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
571 IXGBE_WRITE_FLUSH(hw);
572
573 return 0;
574}
575
576
577
578
579
580
581
582
583s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
584{
585 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
586 u32 eec;
587 u16 eeprom_size;
588
589 if (eeprom->type == ixgbe_eeprom_uninitialized) {
590 eeprom->type = ixgbe_eeprom_none;
591
592
593 eeprom->semaphore_delay = 10;
594
595 eeprom->word_page_size = 0;
596
597
598
599
600
601 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
602 if (eec & IXGBE_EEC_PRES) {
603 eeprom->type = ixgbe_eeprom_spi;
604
605
606
607
608
609 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
610 IXGBE_EEC_SIZE_SHIFT);
611 eeprom->word_size = 1 << (eeprom_size +
612 IXGBE_EEPROM_WORD_SIZE_SHIFT);
613 }
614
615 if (eec & IXGBE_EEC_ADDR_SIZE)
616 eeprom->address_bits = 16;
617 else
618 eeprom->address_bits = 8;
619 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
620 "%d\n", eeprom->type, eeprom->word_size,
621 eeprom->address_bits);
622 }
623
624 return 0;
625}
626
627
628
629
630
631
632
633
634
635
636s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
637 u16 words, u16 *data)
638{
639 s32 status = 0;
640 u16 i, count;
641
642 hw->eeprom.ops.init_params(hw);
643
644 if (words == 0) {
645 status = IXGBE_ERR_INVALID_ARGUMENT;
646 goto out;
647 }
648
649 if (offset + words > hw->eeprom.word_size) {
650 status = IXGBE_ERR_EEPROM;
651 goto out;
652 }
653
654
655
656
657
658 if ((hw->eeprom.word_page_size == 0) &&
659 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
660 ixgbe_detect_eeprom_page_size_generic(hw, offset);
661
662
663
664
665
666
667 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
668 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
669 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
670 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
671 count, &data[i]);
672
673 if (status != 0)
674 break;
675 }
676
677out:
678 return status;
679}
680
681
682
683
684
685
686
687
688
689
690
691static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
692 u16 words, u16 *data)
693{
694 s32 status;
695 u16 word;
696 u16 page_size;
697 u16 i;
698 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
699
700
701 status = ixgbe_acquire_eeprom(hw);
702
703 if (status == 0) {
704 if (ixgbe_ready_eeprom(hw) != 0) {
705 ixgbe_release_eeprom(hw);
706 status = IXGBE_ERR_EEPROM;
707 }
708 }
709
710 if (status == 0) {
711 for (i = 0; i < words; i++) {
712 ixgbe_standby_eeprom(hw);
713
714
715 ixgbe_shift_out_eeprom_bits(hw,
716 IXGBE_EEPROM_WREN_OPCODE_SPI,
717 IXGBE_EEPROM_OPCODE_BITS);
718
719 ixgbe_standby_eeprom(hw);
720
721
722
723
724
725 if ((hw->eeprom.address_bits == 8) &&
726 ((offset + i) >= 128))
727 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
728
729
730 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
731 IXGBE_EEPROM_OPCODE_BITS);
732 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
733 hw->eeprom.address_bits);
734
735 page_size = hw->eeprom.word_page_size;
736
737
738 do {
739 word = data[i];
740 word = (word >> 8) | (word << 8);
741 ixgbe_shift_out_eeprom_bits(hw, word, 16);
742
743 if (page_size == 0)
744 break;
745
746
747 if (((offset + i) & (page_size - 1)) ==
748 (page_size - 1))
749 break;
750 } while (++i < words);
751
752 ixgbe_standby_eeprom(hw);
753 usleep_range(10000, 20000);
754 }
755
756 ixgbe_release_eeprom(hw);
757 }
758
759 return status;
760}
761
762
763
764
765
766
767
768
769
770
771s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
772{
773 s32 status;
774
775 hw->eeprom.ops.init_params(hw);
776
777 if (offset >= hw->eeprom.word_size) {
778 status = IXGBE_ERR_EEPROM;
779 goto out;
780 }
781
782 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
783
784out:
785 return status;
786}
787
788
789
790
791
792
793
794
795
796
797s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
798 u16 words, u16 *data)
799{
800 s32 status = 0;
801 u16 i, count;
802
803 hw->eeprom.ops.init_params(hw);
804
805 if (words == 0) {
806 status = IXGBE_ERR_INVALID_ARGUMENT;
807 goto out;
808 }
809
810 if (offset + words > hw->eeprom.word_size) {
811 status = IXGBE_ERR_EEPROM;
812 goto out;
813 }
814
815
816
817
818
819
820 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
821 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
822 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
823
824 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
825 count, &data[i]);
826
827 if (status != 0)
828 break;
829 }
830
831out:
832 return status;
833}
834
835
836
837
838
839
840
841
842
843
844static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
845 u16 words, u16 *data)
846{
847 s32 status;
848 u16 word_in;
849 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
850 u16 i;
851
852
853 status = ixgbe_acquire_eeprom(hw);
854
855 if (status == 0) {
856 if (ixgbe_ready_eeprom(hw) != 0) {
857 ixgbe_release_eeprom(hw);
858 status = IXGBE_ERR_EEPROM;
859 }
860 }
861
862 if (status == 0) {
863 for (i = 0; i < words; i++) {
864 ixgbe_standby_eeprom(hw);
865
866
867
868
869 if ((hw->eeprom.address_bits == 8) &&
870 ((offset + i) >= 128))
871 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
872
873
874 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
875 IXGBE_EEPROM_OPCODE_BITS);
876 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
877 hw->eeprom.address_bits);
878
879
880 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
881 data[i] = (word_in >> 8) | (word_in << 8);
882 }
883
884
885 ixgbe_release_eeprom(hw);
886 }
887
888 return status;
889}
890
891
892
893
894
895
896
897
898
899s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
900 u16 *data)
901{
902 s32 status;
903
904 hw->eeprom.ops.init_params(hw);
905
906 if (offset >= hw->eeprom.word_size) {
907 status = IXGBE_ERR_EEPROM;
908 goto out;
909 }
910
911 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
912
913out:
914 return status;
915}
916
917
918
919
920
921
922
923
924
925
926s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
927 u16 words, u16 *data)
928{
929 u32 eerd;
930 s32 status = 0;
931 u32 i;
932
933 hw->eeprom.ops.init_params(hw);
934
935 if (words == 0) {
936 status = IXGBE_ERR_INVALID_ARGUMENT;
937 goto out;
938 }
939
940 if (offset >= hw->eeprom.word_size) {
941 status = IXGBE_ERR_EEPROM;
942 goto out;
943 }
944
945 for (i = 0; i < words; i++) {
946 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
947 IXGBE_EEPROM_RW_REG_START;
948
949 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
950 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
951
952 if (status == 0) {
953 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
954 IXGBE_EEPROM_RW_REG_DATA);
955 } else {
956 hw_dbg(hw, "Eeprom read timed out\n");
957 goto out;
958 }
959 }
960out:
961 return status;
962}
963
964
965
966
967
968
969
970
971
972
973static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
974 u16 offset)
975{
976 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
977 s32 status = 0;
978 u16 i;
979
980 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
981 data[i] = i;
982
983 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
984 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
985 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
986 hw->eeprom.word_page_size = 0;
987 if (status != 0)
988 goto out;
989
990 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
991 if (status != 0)
992 goto out;
993
994
995
996
997
998 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
999
1000 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1001 hw->eeprom.word_page_size);
1002out:
1003 return status;
1004}
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1015{
1016 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1017}
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1029 u16 words, u16 *data)
1030{
1031 u32 eewr;
1032 s32 status = 0;
1033 u16 i;
1034
1035 hw->eeprom.ops.init_params(hw);
1036
1037 if (words == 0) {
1038 status = IXGBE_ERR_INVALID_ARGUMENT;
1039 goto out;
1040 }
1041
1042 if (offset >= hw->eeprom.word_size) {
1043 status = IXGBE_ERR_EEPROM;
1044 goto out;
1045 }
1046
1047 for (i = 0; i < words; i++) {
1048 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1049 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1050 IXGBE_EEPROM_RW_REG_START;
1051
1052 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1053 if (status != 0) {
1054 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1055 goto out;
1056 }
1057
1058 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1059
1060 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1061 if (status != 0) {
1062 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1063 goto out;
1064 }
1065 }
1066
1067out:
1068 return status;
1069}
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1080{
1081 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1082}
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1093{
1094 u32 i;
1095 u32 reg;
1096 s32 status = IXGBE_ERR_EEPROM;
1097
1098 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1099 if (ee_reg == IXGBE_NVM_POLL_READ)
1100 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1101 else
1102 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1103
1104 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1105 status = 0;
1106 break;
1107 }
1108 udelay(5);
1109 }
1110 return status;
1111}
1112
1113
1114
1115
1116
1117
1118
1119
1120static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1121{
1122 s32 status = 0;
1123 u32 eec;
1124 u32 i;
1125
1126 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1127 status = IXGBE_ERR_SWFW_SYNC;
1128
1129 if (status == 0) {
1130 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1131
1132
1133 eec |= IXGBE_EEC_REQ;
1134 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1135
1136 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1137 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1138 if (eec & IXGBE_EEC_GNT)
1139 break;
1140 udelay(5);
1141 }
1142
1143
1144 if (!(eec & IXGBE_EEC_GNT)) {
1145 eec &= ~IXGBE_EEC_REQ;
1146 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1147 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1148
1149 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1150 status = IXGBE_ERR_EEPROM;
1151 }
1152
1153
1154 if (status == 0) {
1155
1156 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1157 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1158 IXGBE_WRITE_FLUSH(hw);
1159 udelay(1);
1160 }
1161 }
1162 return status;
1163}
1164
1165
1166
1167
1168
1169
1170
1171static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1172{
1173 s32 status = IXGBE_ERR_EEPROM;
1174 u32 timeout = 2000;
1175 u32 i;
1176 u32 swsm;
1177
1178
1179 for (i = 0; i < timeout; i++) {
1180
1181
1182
1183
1184 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1185 if (!(swsm & IXGBE_SWSM_SMBI)) {
1186 status = 0;
1187 break;
1188 }
1189 udelay(50);
1190 }
1191
1192 if (i == timeout) {
1193 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1194 "not granted.\n");
1195
1196
1197
1198
1199
1200
1201 ixgbe_release_eeprom_semaphore(hw);
1202
1203 udelay(50);
1204
1205
1206
1207
1208
1209 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1210 if (!(swsm & IXGBE_SWSM_SMBI))
1211 status = 0;
1212 }
1213
1214
1215 if (status == 0) {
1216 for (i = 0; i < timeout; i++) {
1217 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1218
1219
1220 swsm |= IXGBE_SWSM_SWESMBI;
1221 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1222
1223
1224
1225
1226
1227 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1228 if (swsm & IXGBE_SWSM_SWESMBI)
1229 break;
1230
1231 udelay(50);
1232 }
1233
1234
1235
1236
1237
1238 if (i >= timeout) {
1239 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
1240 "not granted.\n");
1241 ixgbe_release_eeprom_semaphore(hw);
1242 status = IXGBE_ERR_EEPROM;
1243 }
1244 } else {
1245 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1246 "not granted.\n");
1247 }
1248
1249 return status;
1250}
1251
1252
1253
1254
1255
1256
1257
1258static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1259{
1260 u32 swsm;
1261
1262 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1263
1264
1265 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1266 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1267 IXGBE_WRITE_FLUSH(hw);
1268}
1269
1270
1271
1272
1273
1274static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1275{
1276 s32 status = 0;
1277 u16 i;
1278 u8 spi_stat_reg;
1279
1280
1281
1282
1283
1284
1285
1286 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1287 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1288 IXGBE_EEPROM_OPCODE_BITS);
1289 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1290 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1291 break;
1292
1293 udelay(5);
1294 ixgbe_standby_eeprom(hw);
1295 }
1296
1297
1298
1299
1300
1301 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1302 hw_dbg(hw, "SPI EEPROM Status error\n");
1303 status = IXGBE_ERR_EEPROM;
1304 }
1305
1306 return status;
1307}
1308
1309
1310
1311
1312
1313static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1314{
1315 u32 eec;
1316
1317 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1318
1319
1320 eec |= IXGBE_EEC_CS;
1321 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1322 IXGBE_WRITE_FLUSH(hw);
1323 udelay(1);
1324 eec &= ~IXGBE_EEC_CS;
1325 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1326 IXGBE_WRITE_FLUSH(hw);
1327 udelay(1);
1328}
1329
1330
1331
1332
1333
1334
1335
1336static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1337 u16 count)
1338{
1339 u32 eec;
1340 u32 mask;
1341 u32 i;
1342
1343 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1344
1345
1346
1347
1348
1349 mask = 0x01 << (count - 1);
1350
1351 for (i = 0; i < count; i++) {
1352
1353
1354
1355
1356
1357
1358
1359 if (data & mask)
1360 eec |= IXGBE_EEC_DI;
1361 else
1362 eec &= ~IXGBE_EEC_DI;
1363
1364 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1365 IXGBE_WRITE_FLUSH(hw);
1366
1367 udelay(1);
1368
1369 ixgbe_raise_eeprom_clk(hw, &eec);
1370 ixgbe_lower_eeprom_clk(hw, &eec);
1371
1372
1373
1374
1375
1376 mask = mask >> 1;
1377 }
1378
1379
1380 eec &= ~IXGBE_EEC_DI;
1381 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1382 IXGBE_WRITE_FLUSH(hw);
1383}
1384
1385
1386
1387
1388
1389static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1390{
1391 u32 eec;
1392 u32 i;
1393 u16 data = 0;
1394
1395
1396
1397
1398
1399
1400
1401
1402 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1403
1404 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1405
1406 for (i = 0; i < count; i++) {
1407 data = data << 1;
1408 ixgbe_raise_eeprom_clk(hw, &eec);
1409
1410 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1411
1412 eec &= ~(IXGBE_EEC_DI);
1413 if (eec & IXGBE_EEC_DO)
1414 data |= 1;
1415
1416 ixgbe_lower_eeprom_clk(hw, &eec);
1417 }
1418
1419 return data;
1420}
1421
1422
1423
1424
1425
1426
1427static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1428{
1429
1430
1431
1432
1433 *eec = *eec | IXGBE_EEC_SK;
1434 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1435 IXGBE_WRITE_FLUSH(hw);
1436 udelay(1);
1437}
1438
1439
1440
1441
1442
1443
1444static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1445{
1446
1447
1448
1449
1450 *eec = *eec & ~IXGBE_EEC_SK;
1451 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1452 IXGBE_WRITE_FLUSH(hw);
1453 udelay(1);
1454}
1455
1456
1457
1458
1459
1460static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1461{
1462 u32 eec;
1463
1464 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1465
1466 eec |= IXGBE_EEC_CS;
1467 eec &= ~IXGBE_EEC_SK;
1468
1469 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1470 IXGBE_WRITE_FLUSH(hw);
1471
1472 udelay(1);
1473
1474
1475 eec &= ~IXGBE_EEC_REQ;
1476 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1477
1478 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1479
1480
1481
1482
1483
1484 usleep_range(hw->eeprom.semaphore_delay * 1000,
1485 hw->eeprom.semaphore_delay * 2000);
1486}
1487
1488
1489
1490
1491
1492u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1493{
1494 u16 i;
1495 u16 j;
1496 u16 checksum = 0;
1497 u16 length = 0;
1498 u16 pointer = 0;
1499 u16 word = 0;
1500
1501
1502 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1503 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1504 hw_dbg(hw, "EEPROM read failed\n");
1505 break;
1506 }
1507 checksum += word;
1508 }
1509
1510
1511 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1512 hw->eeprom.ops.read(hw, i, &pointer);
1513
1514
1515 if (pointer != 0xFFFF && pointer != 0) {
1516 hw->eeprom.ops.read(hw, pointer, &length);
1517
1518 if (length != 0xFFFF && length != 0) {
1519 for (j = pointer+1; j <= pointer+length; j++) {
1520 hw->eeprom.ops.read(hw, j, &word);
1521 checksum += word;
1522 }
1523 }
1524 }
1525 }
1526
1527 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1528
1529 return checksum;
1530}
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1541 u16 *checksum_val)
1542{
1543 s32 status;
1544 u16 checksum;
1545 u16 read_checksum = 0;
1546
1547
1548
1549
1550
1551
1552 status = hw->eeprom.ops.read(hw, 0, &checksum);
1553
1554 if (status == 0) {
1555 checksum = hw->eeprom.ops.calc_checksum(hw);
1556
1557 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1558
1559
1560
1561
1562
1563 if (read_checksum != checksum)
1564 status = IXGBE_ERR_EEPROM_CHECKSUM;
1565
1566
1567 if (checksum_val)
1568 *checksum_val = checksum;
1569 } else {
1570 hw_dbg(hw, "EEPROM read failed\n");
1571 }
1572
1573 return status;
1574}
1575
1576
1577
1578
1579
1580s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1581{
1582 s32 status;
1583 u16 checksum;
1584
1585
1586
1587
1588
1589
1590 status = hw->eeprom.ops.read(hw, 0, &checksum);
1591
1592 if (status == 0) {
1593 checksum = hw->eeprom.ops.calc_checksum(hw);
1594 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1595 checksum);
1596 } else {
1597 hw_dbg(hw, "EEPROM read failed\n");
1598 }
1599
1600 return status;
1601}
1602
1603
1604
1605
1606
1607
1608
1609s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1610{
1611 s32 status = 0;
1612
1613
1614 if (IXGBE_IS_MULTICAST(mac_addr))
1615 status = IXGBE_ERR_INVALID_MAC_ADDR;
1616
1617 else if (IXGBE_IS_BROADCAST(mac_addr))
1618 status = IXGBE_ERR_INVALID_MAC_ADDR;
1619
1620 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1621 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1622 status = IXGBE_ERR_INVALID_MAC_ADDR;
1623
1624 return status;
1625}
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1638 u32 enable_addr)
1639{
1640 u32 rar_low, rar_high;
1641 u32 rar_entries = hw->mac.num_rar_entries;
1642
1643
1644 if (index >= rar_entries) {
1645 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1646 return IXGBE_ERR_INVALID_ARGUMENT;
1647 }
1648
1649
1650 hw->mac.ops.set_vmdq(hw, index, vmdq);
1651
1652
1653
1654
1655
1656 rar_low = ((u32)addr[0] |
1657 ((u32)addr[1] << 8) |
1658 ((u32)addr[2] << 16) |
1659 ((u32)addr[3] << 24));
1660
1661
1662
1663
1664
1665 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1666 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1667 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1668
1669 if (enable_addr != 0)
1670 rar_high |= IXGBE_RAH_AV;
1671
1672 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1673 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1674
1675 return 0;
1676}
1677
1678
1679
1680
1681
1682
1683
1684
1685s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1686{
1687 u32 rar_high;
1688 u32 rar_entries = hw->mac.num_rar_entries;
1689
1690
1691 if (index >= rar_entries) {
1692 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1693 return IXGBE_ERR_INVALID_ARGUMENT;
1694 }
1695
1696
1697
1698
1699
1700
1701 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1702 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1703
1704 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1705 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1706
1707
1708 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1709
1710 return 0;
1711}
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1722{
1723 u32 i;
1724 u32 rar_entries = hw->mac.num_rar_entries;
1725
1726
1727
1728
1729
1730
1731 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1732 IXGBE_ERR_INVALID_MAC_ADDR) {
1733
1734 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1735
1736 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1737 } else {
1738
1739 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1740 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1741
1742 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1743
1744
1745 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1746 }
1747 hw->addr_ctrl.overflow_promisc = 0;
1748
1749 hw->addr_ctrl.rar_used_count = 1;
1750
1751
1752 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1753 for (i = 1; i < rar_entries; i++) {
1754 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1755 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1756 }
1757
1758
1759 hw->addr_ctrl.mta_in_use = 0;
1760 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1761
1762 hw_dbg(hw, " Clearing MTA\n");
1763 for (i = 0; i < hw->mac.mcft_size; i++)
1764 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1765
1766 if (hw->mac.ops.init_uta_tables)
1767 hw->mac.ops.init_uta_tables(hw);
1768
1769 return 0;
1770}
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1785{
1786 u32 vector = 0;
1787
1788 switch (hw->mac.mc_filter_type) {
1789 case 0:
1790 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1791 break;
1792 case 1:
1793 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1794 break;
1795 case 2:
1796 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1797 break;
1798 case 3:
1799 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1800 break;
1801 default:
1802 hw_dbg(hw, "MC filter type param set incorrectly\n");
1803 break;
1804 }
1805
1806
1807 vector &= 0xFFF;
1808 return vector;
1809}
1810
1811
1812
1813
1814
1815
1816
1817
1818static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1819{
1820 u32 vector;
1821 u32 vector_bit;
1822 u32 vector_reg;
1823
1824 hw->addr_ctrl.mta_in_use++;
1825
1826 vector = ixgbe_mta_vector(hw, mc_addr);
1827 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838 vector_reg = (vector >> 5) & 0x7F;
1839 vector_bit = vector & 0x1F;
1840 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
1841}
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1854 struct net_device *netdev)
1855{
1856 struct netdev_hw_addr *ha;
1857 u32 i;
1858
1859
1860
1861
1862
1863 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1864 hw->addr_ctrl.mta_in_use = 0;
1865
1866
1867 hw_dbg(hw, " Clearing MTA\n");
1868 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
1869
1870
1871 netdev_for_each_mc_addr(ha, netdev) {
1872 hw_dbg(hw, " Adding the multicast addresses:\n");
1873 ixgbe_set_mta(hw, ha->addr);
1874 }
1875
1876
1877 for (i = 0; i < hw->mac.mcft_size; i++)
1878 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1879 hw->mac.mta_shadow[i]);
1880
1881 if (hw->addr_ctrl.mta_in_use > 0)
1882 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1883 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1884
1885 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1886 return 0;
1887}
1888
1889
1890
1891
1892
1893
1894
1895s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1896{
1897 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1898
1899 if (a->mta_in_use > 0)
1900 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1901 hw->mac.mc_filter_type);
1902
1903 return 0;
1904}
1905
1906
1907
1908
1909
1910
1911
1912s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1913{
1914 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1915
1916 if (a->mta_in_use > 0)
1917 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1918
1919 return 0;
1920}
1921
1922
1923
1924
1925
1926
1927
1928
1929s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1930{
1931 s32 ret_val = 0;
1932 u32 mflcn_reg, fccfg_reg;
1933 u32 reg;
1934 u32 rx_pba_size;
1935 u32 fcrtl, fcrth;
1936
1937#ifdef CONFIG_DCB
1938 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1939 goto out;
1940
1941#endif
1942
1943 ret_val = ixgbe_fc_autoneg(hw);
1944 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
1945 goto out;
1946
1947
1948 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1949 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1950
1951 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1952 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967 switch (hw->fc.current_mode) {
1968 case ixgbe_fc_none:
1969
1970
1971
1972
1973 break;
1974 case ixgbe_fc_rx_pause:
1975
1976
1977
1978
1979
1980
1981
1982
1983 mflcn_reg |= IXGBE_MFLCN_RFCE;
1984 break;
1985 case ixgbe_fc_tx_pause:
1986
1987
1988
1989
1990 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1991 break;
1992 case ixgbe_fc_full:
1993
1994 mflcn_reg |= IXGBE_MFLCN_RFCE;
1995 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1996 break;
1997#ifdef CONFIG_DCB
1998 case ixgbe_fc_pfc:
1999 goto out;
2000 break;
2001#endif
2002 default:
2003 hw_dbg(hw, "Flow control param set incorrectly\n");
2004 ret_val = IXGBE_ERR_CONFIG;
2005 goto out;
2006 break;
2007 }
2008
2009
2010 mflcn_reg |= IXGBE_MFLCN_DPF;
2011 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2012 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2013
2014 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
2015 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
2016
2017 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
2018 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
2019
2020 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2021 fcrth |= IXGBE_FCRTH_FCEN;
2022 if (hw->fc.send_xon)
2023 fcrtl |= IXGBE_FCRTL_XONE;
2024 }
2025
2026 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
2027 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
2028
2029
2030 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
2031 if ((packetbuf_num & 1) == 0)
2032 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
2033 else
2034 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
2035 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
2036
2037 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
2038
2039out:
2040 return ret_val;
2041}
2042
2043
2044
2045
2046
2047
2048
2049
2050s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2051{
2052 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2053 ixgbe_link_speed speed;
2054 bool link_up;
2055
2056 if (hw->fc.disable_fc_autoneg)
2057 goto out;
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2069 if (!link_up) {
2070 ret_val = IXGBE_ERR_FLOW_CONTROL;
2071 goto out;
2072 }
2073
2074 switch (hw->phy.media_type) {
2075
2076 case ixgbe_media_type_fiber:
2077 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2078 ret_val = ixgbe_fc_autoneg_fiber(hw);
2079 break;
2080
2081
2082 case ixgbe_media_type_backplane:
2083 ret_val = ixgbe_fc_autoneg_backplane(hw);
2084 break;
2085
2086
2087 case ixgbe_media_type_copper:
2088 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2089 ret_val = ixgbe_fc_autoneg_copper(hw);
2090 break;
2091
2092 default:
2093 break;
2094 }
2095
2096out:
2097 if (ret_val == 0) {
2098 hw->fc.fc_was_autonegged = true;
2099 } else {
2100 hw->fc.fc_was_autonegged = false;
2101 hw->fc.current_mode = hw->fc.requested_mode;
2102 }
2103 return ret_val;
2104}
2105
2106
2107
2108
2109
2110
2111
2112static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2113{
2114 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2115 s32 ret_val;
2116
2117
2118
2119
2120
2121
2122
2123 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2124 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2125 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2126 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2127 goto out;
2128 }
2129
2130 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2131 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2132
2133 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2134 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2135 IXGBE_PCS1GANA_ASM_PAUSE,
2136 IXGBE_PCS1GANA_SYM_PAUSE,
2137 IXGBE_PCS1GANA_ASM_PAUSE);
2138
2139out:
2140 return ret_val;
2141}
2142
2143
2144
2145
2146
2147
2148
2149static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2150{
2151 u32 links2, anlp1_reg, autoc_reg, links;
2152 s32 ret_val;
2153
2154
2155
2156
2157
2158
2159 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2160 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2161 hw->fc.fc_was_autonegged = false;
2162 hw->fc.current_mode = hw->fc.requested_mode;
2163 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2164 goto out;
2165 }
2166
2167 if (hw->mac.type == ixgbe_mac_82599EB) {
2168 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2169 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2170 hw->fc.fc_was_autonegged = false;
2171 hw->fc.current_mode = hw->fc.requested_mode;
2172 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2173 goto out;
2174 }
2175 }
2176
2177
2178
2179
2180 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2181 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2182
2183 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2184 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2185 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2186
2187out:
2188 return ret_val;
2189}
2190
2191
2192
2193
2194
2195
2196
2197static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2198{
2199 u16 technology_ability_reg = 0;
2200 u16 lp_technology_ability_reg = 0;
2201
2202 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2203 MDIO_MMD_AN,
2204 &technology_ability_reg);
2205 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2206 MDIO_MMD_AN,
2207 &lp_technology_ability_reg);
2208
2209 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2210 (u32)lp_technology_ability_reg,
2211 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2212 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2213}
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2229 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2230{
2231 if ((!(adv_reg)) || (!(lp_reg)))
2232 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2233
2234 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2235
2236
2237
2238
2239
2240
2241
2242 if (hw->fc.requested_mode == ixgbe_fc_full) {
2243 hw->fc.current_mode = ixgbe_fc_full;
2244 hw_dbg(hw, "Flow Control = FULL.\n");
2245 } else {
2246 hw->fc.current_mode = ixgbe_fc_rx_pause;
2247 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2248 }
2249 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2250 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2251 hw->fc.current_mode = ixgbe_fc_tx_pause;
2252 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2253 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2254 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2255 hw->fc.current_mode = ixgbe_fc_rx_pause;
2256 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2257 } else {
2258 hw->fc.current_mode = ixgbe_fc_none;
2259 hw_dbg(hw, "Flow Control = NONE.\n");
2260 }
2261 return 0;
2262}
2263
2264
2265
2266
2267
2268
2269
2270static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
2271{
2272 s32 ret_val = 0;
2273 u32 reg = 0, reg_bp = 0;
2274 u16 reg_cu = 0;
2275
2276#ifdef CONFIG_DCB
2277 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
2278 hw->fc.current_mode = hw->fc.requested_mode;
2279 goto out;
2280 }
2281
2282#endif
2283
2284 if (packetbuf_num < 0 || packetbuf_num > 7) {
2285 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
2286 "is 0-7\n", packetbuf_num);
2287 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2288 goto out;
2289 }
2290
2291
2292
2293
2294
2295 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
2296 hw_dbg(hw, "Invalid water mark configuration\n");
2297 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2298 goto out;
2299 }
2300
2301
2302
2303
2304
2305 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2306 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
2307 "IEEE mode\n");
2308 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2309 goto out;
2310 }
2311
2312
2313
2314
2315
2316 if (hw->fc.requested_mode == ixgbe_fc_default)
2317 hw->fc.requested_mode = ixgbe_fc_full;
2318
2319
2320
2321
2322
2323
2324
2325 switch (hw->phy.media_type) {
2326 case ixgbe_media_type_fiber:
2327 case ixgbe_media_type_backplane:
2328 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2329 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2330 break;
2331
2332 case ixgbe_media_type_copper:
2333 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2334 MDIO_MMD_AN, ®_cu);
2335 break;
2336
2337 default:
2338 ;
2339 }
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354 switch (hw->fc.requested_mode) {
2355 case ixgbe_fc_none:
2356
2357 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2358 if (hw->phy.media_type == ixgbe_media_type_backplane)
2359 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2360 IXGBE_AUTOC_ASM_PAUSE);
2361 else if (hw->phy.media_type == ixgbe_media_type_copper)
2362 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2363 break;
2364 case ixgbe_fc_rx_pause:
2365
2366
2367
2368
2369
2370
2371
2372
2373 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2374 if (hw->phy.media_type == ixgbe_media_type_backplane)
2375 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2376 IXGBE_AUTOC_ASM_PAUSE);
2377 else if (hw->phy.media_type == ixgbe_media_type_copper)
2378 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2379 break;
2380 case ixgbe_fc_tx_pause:
2381
2382
2383
2384
2385 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2386 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
2387 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2388 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2389 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2390 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2391 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2392 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2393 }
2394 break;
2395 case ixgbe_fc_full:
2396
2397 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2398 if (hw->phy.media_type == ixgbe_media_type_backplane)
2399 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2400 IXGBE_AUTOC_ASM_PAUSE);
2401 else if (hw->phy.media_type == ixgbe_media_type_copper)
2402 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2403 break;
2404#ifdef CONFIG_DCB
2405 case ixgbe_fc_pfc:
2406 goto out;
2407 break;
2408#endif
2409 default:
2410 hw_dbg(hw, "Flow control param set incorrectly\n");
2411 ret_val = IXGBE_ERR_CONFIG;
2412 goto out;
2413 break;
2414 }
2415
2416 if (hw->mac.type != ixgbe_mac_X540) {
2417
2418
2419
2420
2421 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2422 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2423
2424
2425 if (hw->fc.strict_ieee)
2426 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2427
2428 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2429 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2430 }
2431
2432
2433
2434
2435
2436
2437 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2438 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2439 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2440 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2441 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
2442 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
2443 MDIO_MMD_AN, reg_cu);
2444 }
2445
2446 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2447out:
2448 return ret_val;
2449}
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2461{
2462 struct ixgbe_adapter *adapter = hw->back;
2463 u32 i;
2464 u32 reg_val;
2465 u32 number_of_queues;
2466 s32 status = 0;
2467 u16 dev_status = 0;
2468
2469
2470 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2471 goto out;
2472
2473
2474 number_of_queues = hw->mac.max_rx_queues;
2475 for (i = 0; i < number_of_queues; i++) {
2476 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2477 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2478 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2479 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2480 }
2481 }
2482
2483 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2484 reg_val |= IXGBE_CTRL_GIO_DIS;
2485 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2486
2487 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2488 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2489 goto check_device_status;
2490 udelay(100);
2491 }
2492
2493 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2494 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2495
2496
2497
2498
2499
2500check_device_status:
2501 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2502 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2503 &dev_status);
2504 if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2505 break;
2506 udelay(100);
2507 }
2508
2509 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2510 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2511 else
2512 goto out;
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2523
2524out:
2525 return status;
2526}
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2538{
2539 u32 gssr;
2540 u32 swmask = mask;
2541 u32 fwmask = mask << 5;
2542 s32 timeout = 200;
2543
2544 while (timeout) {
2545
2546
2547
2548
2549 if (ixgbe_get_eeprom_semaphore(hw))
2550 return IXGBE_ERR_SWFW_SYNC;
2551
2552 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2553 if (!(gssr & (fwmask | swmask)))
2554 break;
2555
2556
2557
2558
2559
2560 ixgbe_release_eeprom_semaphore(hw);
2561 usleep_range(5000, 10000);
2562 timeout--;
2563 }
2564
2565 if (!timeout) {
2566 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2567 return IXGBE_ERR_SWFW_SYNC;
2568 }
2569
2570 gssr |= swmask;
2571 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2572
2573 ixgbe_release_eeprom_semaphore(hw);
2574 return 0;
2575}
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2586{
2587 u32 gssr;
2588 u32 swmask = mask;
2589
2590 ixgbe_get_eeprom_semaphore(hw);
2591
2592 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2593 gssr &= ~swmask;
2594 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2595
2596 ixgbe_release_eeprom_semaphore(hw);
2597}
2598
2599
2600
2601
2602
2603
2604
2605
2606s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2607{
2608 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2609
2610 return 0;
2611}
2612
2613
2614
2615
2616
2617
2618s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2619{
2620 ixgbe_link_speed speed = 0;
2621 bool link_up = 0;
2622 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2623 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2624
2625
2626
2627
2628
2629 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2630
2631 if (!link_up) {
2632 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2633 autoc_reg |= IXGBE_AUTOC_FLU;
2634 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2635 IXGBE_WRITE_FLUSH(hw);
2636 usleep_range(10000, 20000);
2637 }
2638
2639 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2640 led_reg |= IXGBE_LED_BLINK(index);
2641 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2642 IXGBE_WRITE_FLUSH(hw);
2643
2644 return 0;
2645}
2646
2647
2648
2649
2650
2651
2652s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2653{
2654 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2655 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2656
2657 autoc_reg &= ~IXGBE_AUTOC_FLU;
2658 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2659 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2660
2661 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2662 led_reg &= ~IXGBE_LED_BLINK(index);
2663 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2664 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2665 IXGBE_WRITE_FLUSH(hw);
2666
2667 return 0;
2668}
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2680 u16 *san_mac_offset)
2681{
2682
2683
2684
2685
2686 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2687
2688 return 0;
2689}
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2702{
2703 u16 san_mac_data, san_mac_offset;
2704 u8 i;
2705
2706
2707
2708
2709
2710 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2711
2712 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2713
2714
2715
2716
2717 for (i = 0; i < 6; i++)
2718 san_mac_addr[i] = 0xFF;
2719
2720 goto san_mac_addr_out;
2721 }
2722
2723
2724 hw->mac.ops.set_lan_id(hw);
2725
2726 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2727 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2728 for (i = 0; i < 3; i++) {
2729 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2730 san_mac_addr[i * 2] = (u8)(san_mac_data);
2731 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2732 san_mac_offset++;
2733 }
2734
2735san_mac_addr_out:
2736 return 0;
2737}
2738
2739
2740
2741
2742
2743
2744
2745
2746u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2747{
2748 struct ixgbe_adapter *adapter = hw->back;
2749 u16 msix_count;
2750 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2751 &msix_count);
2752 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2753
2754
2755 msix_count++;
2756
2757 return msix_count;
2758}
2759
2760
2761
2762
2763
2764
2765
2766s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2767{
2768 u32 mpsar_lo, mpsar_hi;
2769 u32 rar_entries = hw->mac.num_rar_entries;
2770
2771
2772 if (rar >= rar_entries) {
2773 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2774 return IXGBE_ERR_INVALID_ARGUMENT;
2775 }
2776
2777 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2778 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2779
2780 if (!mpsar_lo && !mpsar_hi)
2781 goto done;
2782
2783 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2784 if (mpsar_lo) {
2785 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2786 mpsar_lo = 0;
2787 }
2788 if (mpsar_hi) {
2789 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2790 mpsar_hi = 0;
2791 }
2792 } else if (vmdq < 32) {
2793 mpsar_lo &= ~(1 << vmdq);
2794 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2795 } else {
2796 mpsar_hi &= ~(1 << (vmdq - 32));
2797 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2798 }
2799
2800
2801 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2802 hw->mac.ops.clear_rar(hw, rar);
2803done:
2804 return 0;
2805}
2806
2807
2808
2809
2810
2811
2812
2813s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2814{
2815 u32 mpsar;
2816 u32 rar_entries = hw->mac.num_rar_entries;
2817
2818
2819 if (rar >= rar_entries) {
2820 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2821 return IXGBE_ERR_INVALID_ARGUMENT;
2822 }
2823
2824 if (vmdq < 32) {
2825 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2826 mpsar |= 1 << vmdq;
2827 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2828 } else {
2829 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2830 mpsar |= 1 << (vmdq - 32);
2831 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2832 }
2833 return 0;
2834}
2835
2836
2837
2838
2839
2840s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2841{
2842 int i;
2843
2844 for (i = 0; i < 128; i++)
2845 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2846
2847 return 0;
2848}
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2859{
2860 u32 bits = 0;
2861 u32 first_empty_slot = 0;
2862 s32 regindex;
2863
2864
2865 if (vlan == 0)
2866 return 0;
2867
2868
2869
2870
2871
2872 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2873 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2874 if (!bits && !(first_empty_slot))
2875 first_empty_slot = regindex;
2876 else if ((bits & 0x0FFF) == vlan)
2877 break;
2878 }
2879
2880
2881
2882
2883
2884
2885 if (regindex >= IXGBE_VLVF_ENTRIES) {
2886 if (first_empty_slot)
2887 regindex = first_empty_slot;
2888 else {
2889 hw_dbg(hw, "No space in VLVF.\n");
2890 regindex = IXGBE_ERR_NO_SPACE;
2891 }
2892 }
2893
2894 return regindex;
2895}
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2907 bool vlan_on)
2908{
2909 s32 regindex;
2910 u32 bitindex;
2911 u32 vfta;
2912 u32 bits;
2913 u32 vt;
2914 u32 targetbit;
2915 bool vfta_changed = false;
2916
2917 if (vlan > 4095)
2918 return IXGBE_ERR_PARAM;
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932 regindex = (vlan >> 5) & 0x7F;
2933 bitindex = vlan & 0x1F;
2934 targetbit = (1 << bitindex);
2935 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2936
2937 if (vlan_on) {
2938 if (!(vfta & targetbit)) {
2939 vfta |= targetbit;
2940 vfta_changed = true;
2941 }
2942 } else {
2943 if ((vfta & targetbit)) {
2944 vfta &= ~targetbit;
2945 vfta_changed = true;
2946 }
2947 }
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2958 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2959 s32 vlvf_index;
2960
2961 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2962 if (vlvf_index < 0)
2963 return vlvf_index;
2964
2965 if (vlan_on) {
2966
2967 if (vind < 32) {
2968 bits = IXGBE_READ_REG(hw,
2969 IXGBE_VLVFB(vlvf_index*2));
2970 bits |= (1 << vind);
2971 IXGBE_WRITE_REG(hw,
2972 IXGBE_VLVFB(vlvf_index*2),
2973 bits);
2974 } else {
2975 bits = IXGBE_READ_REG(hw,
2976 IXGBE_VLVFB((vlvf_index*2)+1));
2977 bits |= (1 << (vind-32));
2978 IXGBE_WRITE_REG(hw,
2979 IXGBE_VLVFB((vlvf_index*2)+1),
2980 bits);
2981 }
2982 } else {
2983
2984 if (vind < 32) {
2985 bits = IXGBE_READ_REG(hw,
2986 IXGBE_VLVFB(vlvf_index*2));
2987 bits &= ~(1 << vind);
2988 IXGBE_WRITE_REG(hw,
2989 IXGBE_VLVFB(vlvf_index*2),
2990 bits);
2991 bits |= IXGBE_READ_REG(hw,
2992 IXGBE_VLVFB((vlvf_index*2)+1));
2993 } else {
2994 bits = IXGBE_READ_REG(hw,
2995 IXGBE_VLVFB((vlvf_index*2)+1));
2996 bits &= ~(1 << (vind-32));
2997 IXGBE_WRITE_REG(hw,
2998 IXGBE_VLVFB((vlvf_index*2)+1),
2999 bits);
3000 bits |= IXGBE_READ_REG(hw,
3001 IXGBE_VLVFB(vlvf_index*2));
3002 }
3003 }
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020 if (bits) {
3021 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3022 (IXGBE_VLVF_VIEN | vlan));
3023 if (!vlan_on) {
3024
3025
3026
3027 vfta_changed = false;
3028 }
3029 }
3030 else
3031 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3032 }
3033
3034 if (vfta_changed)
3035 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3036
3037 return 0;
3038}
3039
3040
3041
3042
3043
3044
3045
3046s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3047{
3048 u32 offset;
3049
3050 for (offset = 0; offset < hw->mac.vft_size; offset++)
3051 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3052
3053 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3054 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3055 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3056 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3057 }
3058
3059 return 0;
3060}
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3072 bool *link_up, bool link_up_wait_to_complete)
3073{
3074 u32 links_reg, links_orig;
3075 u32 i;
3076
3077
3078 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3079
3080 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3081
3082 if (links_orig != links_reg) {
3083 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3084 links_orig, links_reg);
3085 }
3086
3087 if (link_up_wait_to_complete) {
3088 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3089 if (links_reg & IXGBE_LINKS_UP) {
3090 *link_up = true;
3091 break;
3092 } else {
3093 *link_up = false;
3094 }
3095 msleep(100);
3096 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3097 }
3098 } else {
3099 if (links_reg & IXGBE_LINKS_UP)
3100 *link_up = true;
3101 else
3102 *link_up = false;
3103 }
3104
3105 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3106 IXGBE_LINKS_SPEED_10G_82599)
3107 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3108 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3109 IXGBE_LINKS_SPEED_1G_82599)
3110 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3111 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3112 IXGBE_LINKS_SPEED_100_82599)
3113 *speed = IXGBE_LINK_SPEED_100_FULL;
3114 else
3115 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3116
3117
3118 if (*link_up == false) {
3119 hw->fc.current_mode = ixgbe_fc_none;
3120 hw->fc.fc_was_autonegged = false;
3121 }
3122
3123 return 0;
3124}
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3137 u16 *wwpn_prefix)
3138{
3139 u16 offset, caps;
3140 u16 alt_san_mac_blk_offset;
3141
3142
3143 *wwnn_prefix = 0xFFFF;
3144 *wwpn_prefix = 0xFFFF;
3145
3146
3147 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3148 &alt_san_mac_blk_offset);
3149
3150 if ((alt_san_mac_blk_offset == 0) ||
3151 (alt_san_mac_blk_offset == 0xFFFF))
3152 goto wwn_prefix_out;
3153
3154
3155 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3156 hw->eeprom.ops.read(hw, offset, &caps);
3157 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3158 goto wwn_prefix_out;
3159
3160
3161 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3162 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3163
3164 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3165 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3166
3167wwn_prefix_out:
3168 return 0;
3169}
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
3181{
3182
3183 switch (hw->device_id) {
3184 case IXGBE_DEV_ID_X540T:
3185 return 0;
3186 case IXGBE_DEV_ID_82599_T3_LOM:
3187 return 0;
3188 default:
3189 return IXGBE_ERR_FC_NOT_SUPPORTED;
3190 }
3191}
3192
3193
3194
3195
3196
3197
3198
3199
3200void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3201{
3202 int j;
3203 int pf_target_reg = pf >> 3;
3204 int pf_target_shift = pf % 8;
3205 u32 pfvfspoof = 0;
3206
3207 if (hw->mac.type == ixgbe_mac_82598EB)
3208 return;
3209
3210 if (enable)
3211 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3212
3213
3214
3215
3216
3217 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3218 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3219
3220
3221 if (!enable)
3222 return;
3223
3224
3225
3226
3227
3228 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3229 pfvfspoof ^= (1 << pf_target_shift);
3230 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3231}
3232
3233
3234
3235
3236
3237
3238
3239
3240void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3241{
3242 int vf_target_reg = vf >> 3;
3243 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3244 u32 pfvfspoof;
3245
3246 if (hw->mac.type == ixgbe_mac_82598EB)
3247 return;
3248
3249 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3250 if (enable)
3251 pfvfspoof |= (1 << vf_target_shift);
3252 else
3253 pfvfspoof &= ~(1 << vf_target_shift);
3254 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3255}
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3266{
3267 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3268
3269 return 0;
3270}
3271
3272
3273
3274
3275
3276
3277
3278
3279void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3280 int num_pb,
3281 u32 headroom,
3282 int strategy)
3283{
3284 u32 pbsize = hw->mac.rx_pb_size;
3285 int i = 0;
3286 u32 rxpktsize, txpktsize, txpbthresh;
3287
3288
3289 pbsize -= headroom;
3290
3291 if (!num_pb)
3292 num_pb = 1;
3293
3294
3295
3296
3297 switch (strategy) {
3298 case (PBA_STRATEGY_WEIGHTED):
3299
3300
3301
3302 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3303 pbsize -= rxpktsize * (num_pb / 2);
3304 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3305 for (; i < (num_pb / 2); i++)
3306 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3307
3308 case (PBA_STRATEGY_EQUAL):
3309
3310 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3311 for (; i < num_pb; i++)
3312 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3313 break;
3314 default:
3315 break;
3316 }
3317
3318
3319
3320
3321
3322
3323 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3324 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3325 for (i = 0; i < num_pb; i++) {
3326 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3327 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3328 }
3329
3330
3331 for (; i < IXGBE_MAX_PB; i++) {
3332 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3333 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3334 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3335 }
3336}
3337
3338
3339
3340
3341
3342
3343
3344
3345static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3346{
3347 u32 i;
3348 u8 sum = 0;
3349
3350 if (!buffer)
3351 return 0;
3352
3353 for (i = 0; i < length; i++)
3354 sum += buffer[i];
3355
3356 return (u8) (0 - sum);
3357}
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u8 *buffer,
3370 u32 length)
3371{
3372 u32 hicr, i;
3373 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3374 u8 buf_len, dword_len;
3375
3376 s32 ret_val = 0;
3377
3378 if (length == 0 || length & 0x3 ||
3379 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3380 hw_dbg(hw, "Buffer length failure.\n");
3381 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3382 goto out;
3383 }
3384
3385
3386 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3387 if ((hicr & IXGBE_HICR_EN) == 0) {
3388 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3389 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3390 goto out;
3391 }
3392
3393
3394 dword_len = length >> 2;
3395
3396
3397
3398
3399
3400 for (i = 0; i < dword_len; i++)
3401 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3402 i, *((u32 *)buffer + i));
3403
3404
3405 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3406
3407 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3408 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3409 if (!(hicr & IXGBE_HICR_C))
3410 break;
3411 usleep_range(1000, 2000);
3412 }
3413
3414
3415 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3416 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3417 hw_dbg(hw, "Command has failed with no status valid.\n");
3418 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3419 goto out;
3420 }
3421
3422
3423 dword_len = hdr_size >> 2;
3424
3425
3426 for (i = 0; i < dword_len; i++)
3427 *((u32 *)buffer + i) =
3428 IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
3429
3430
3431 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3432 if (buf_len == 0)
3433 goto out;
3434
3435 if (length < (buf_len + hdr_size)) {
3436 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3437 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3438 goto out;
3439 }
3440
3441
3442 dword_len = (buf_len + 1) >> 2;
3443
3444
3445 for (; i < buf_len; i++)
3446 *((u32 *)buffer + i) =
3447 IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
3448
3449out:
3450 return ret_val;
3451}
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3467 u8 build, u8 sub)
3468{
3469 struct ixgbe_hic_drv_info fw_cmd;
3470 int i;
3471 s32 ret_val = 0;
3472
3473 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3474 ret_val = IXGBE_ERR_SWFW_SYNC;
3475 goto out;
3476 }
3477
3478 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3479 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3480 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3481 fw_cmd.port_num = (u8)hw->bus.func;
3482 fw_cmd.ver_maj = maj;
3483 fw_cmd.ver_min = min;
3484 fw_cmd.ver_build = build;
3485 fw_cmd.ver_sub = sub;
3486 fw_cmd.hdr.checksum = 0;
3487 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3488 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3489 fw_cmd.pad = 0;
3490 fw_cmd.pad2 = 0;
3491
3492 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3493 ret_val = ixgbe_host_interface_command(hw, (u8 *)&fw_cmd,
3494 sizeof(fw_cmd));
3495 if (ret_val != 0)
3496 continue;
3497
3498 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3499 FW_CEM_RESP_STATUS_SUCCESS)
3500 ret_val = 0;
3501 else
3502 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3503
3504 break;
3505 }
3506
3507 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3508out:
3509 return ret_val;
3510}
3511