LXR linux/drivers/net/wan/hd64570.c

   1/*
   2 * Hitachi SCA HD64570 driver for Linux
   3 *
   4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * Source of information: Hitachi HD64570 SCA User's Manual
  11 *
  12 * We use the following SCA memory map:
  13 *
  14 * Packet buffer descriptor rings - starting from winbase or win0base:
  15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
  16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
  17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
  18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
  19 *
  20 * Packet data buffers - starting from winbase + buff_offset:
  21 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers
  22 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers
  23 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers (if used)
  24 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers (if used)
  25 */
  26
  27#include <linux/bitops.h>
  28#include <linux/errno.h>
  29#include <linux/fcntl.h>
  30#include <linux/hdlc.h>
  31#include <linux/in.h>
  32#include <linux/init.h>
  33#include <linux/interrupt.h>
  34#include <linux/ioport.h>
  35#include <linux/jiffies.h>
  36#include <linux/kernel.h>
  37#include <linux/module.h>
  38#include <linux/netdevice.h>
  39#include <linux/skbuff.h>
  40#include <linux/string.h>
  41#include <linux/types.h>
  42#include <asm/io.h>
  43#include <asm/system.h>
  44#include <asm/uaccess.h>
  45#include "hd64570.h"
  46
  47#define get_msci(port)    (phy_node(port) ?   MSCI1_OFFSET :   MSCI0_OFFSET)
  48#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
  49#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
  50
  51#define SCA_INTR_MSCI(node)    (node ? 0x10 : 0x01)
  52#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
  53#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
  54
  55
  56static inline struct net_device *port_to_dev(port_t *port)
  57{
  58        return port->dev;
  59}
  60
  61static inline int sca_intr_status(card_t *card)
  62{
  63        u8 result = 0;
  64        u8 isr0 = sca_in(ISR0, card);
  65        u8 isr1 = sca_in(ISR1, card);
  66
  67        if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
  68        if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
  69        if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
  70        if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
  71        if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
  72        if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
  73
  74        if (!(result & SCA_INTR_DMAC_TX(0)))
  75                if (sca_in(DSR_TX(0), card) & DSR_EOM)
  76                        result |= SCA_INTR_DMAC_TX(0);
  77        if (!(result & SCA_INTR_DMAC_TX(1)))
  78                if (sca_in(DSR_TX(1), card) & DSR_EOM)
  79                        result |= SCA_INTR_DMAC_TX(1);
  80
  81        return result;
  82}
  83
  84static inline port_t* dev_to_port(struct net_device *dev)
  85{
  86        return dev_to_hdlc(dev)->priv;
  87}
  88
  89static inline u16 next_desc(port_t *port, u16 desc, int transmit)
  90{
  91        return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
  92                             : port_to_card(port)->rx_ring_buffers);
  93}
  94
  95
  96static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
  97{
  98        u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
  99        u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
 100
 101        desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
 102        return log_node(port) * (rx_buffs + tx_buffs) +
 103                transmit * rx_buffs + desc;
 104}
 105
 106
 107static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
 108{
 109        /* Descriptor offset always fits in 16 bits */
 110        return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
 111}
 112
 113
 114static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
 115                                             int transmit)
 116{
 117#ifdef PAGE0_ALWAYS_MAPPED
 118        return (pkt_desc __iomem *)(win0base(port_to_card(port))
 119                                    + desc_offset(port, desc, transmit));
 120#else
 121        return (pkt_desc __iomem *)(winbase(port_to_card(port))
 122                                    + desc_offset(port, desc, transmit));
 123#endif
 124}
 125
 126
 127static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
 128{
 129        return port_to_card(port)->buff_offset +
 130                desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
 131}
 132
 133
 134static inline void sca_set_carrier(port_t *port)
 135{
 136        if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
 137#ifdef DEBUG_LINK
 138                printk(KERN_DEBUG "%s: sca_set_carrier on\n",
 139                       port_to_dev(port)->name);
 140#endif
 141                netif_carrier_on(port_to_dev(port));
 142        } else {
 143#ifdef DEBUG_LINK
 144                printk(KERN_DEBUG "%s: sca_set_carrier off\n",
 145                       port_to_dev(port)->name);
 146#endif
 147                netif_carrier_off(port_to_dev(port));
 148        }
 149}
 150
 151
 152static void sca_init_port(port_t *port)
 153{
 154        card_t *card = port_to_card(port);
 155        int transmit, i;
 156
 157        port->rxin = 0;
 158        port->txin = 0;
 159        port->txlast = 0;
 160
 161#ifndef PAGE0_ALWAYS_MAPPED
 162        openwin(card, 0);
 163#endif
 164
 165        for (transmit = 0; transmit < 2; transmit++) {
 166                u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
 167                u16 buffs = transmit ? card->tx_ring_buffers
 168                        : card->rx_ring_buffers;
 169
 170                for (i = 0; i < buffs; i++) {
 171                        pkt_desc __iomem *desc = desc_address(port, i, transmit);
 172                        u16 chain_off = desc_offset(port, i + 1, transmit);
 173                        u32 buff_off = buffer_offset(port, i, transmit);
 174
 175                        writew(chain_off, &desc->cp);
 176                        writel(buff_off, &desc->bp);
 177                        writew(0, &desc->len);
 178                        writeb(0, &desc->stat);
 179                }
 180
 181                /* DMA disable - to halt state */
 182                sca_out(0, transmit ? DSR_TX(phy_node(port)) :
 183                        DSR_RX(phy_node(port)), card);
 184                /* software ABORT - to initial state */
 185                sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
 186                        DCR_RX(phy_node(port)), card);
 187
 188                /* current desc addr */
 189                sca_out(0, dmac + CPB, card); /* pointer base */
 190                sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
 191                if (!transmit)
 192                        sca_outw(desc_offset(port, buffs - 1, transmit),
 193                                 dmac + EDAL, card);
 194                else
 195                        sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
 196                                 card);
 197
 198                /* clear frame end interrupt counter */
 199                sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
 200                        DCR_RX(phy_node(port)), card);
 201
 202                if (!transmit) { /* Receive */
 203                        /* set buffer length */
 204                        sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
 205                        /* Chain mode, Multi-frame */
 206                        sca_out(0x14, DMR_RX(phy_node(port)), card);
 207                        sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
 208                                card);
 209                        /* DMA enable */
 210                        sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
 211                } else {        /* Transmit */
 212                        /* Chain mode, Multi-frame */
 213                        sca_out(0x14, DMR_TX(phy_node(port)), card);
 214                        /* enable underflow interrupts */
 215                        sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
 216                }
 217        }
 218        sca_set_carrier(port);
 219}
 220
 221
 222#ifdef NEED_SCA_MSCI_INTR
 223/* MSCI interrupt service */
 224static inline void sca_msci_intr(port_t *port)
 225{
 226        u16 msci = get_msci(port);
 227        card_t* card = port_to_card(port);
 228        u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
 229
 230        /* Reset MSCI TX underrun and CDCD status bit */
 231        sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
 232
 233        if (stat & ST1_UDRN) {
 234                /* TX Underrun error detected */
 235                port_to_dev(port)->stats.tx_errors++;
 236                port_to_dev(port)->stats.tx_fifo_errors++;
 237        }
 238
 239        if (stat & ST1_CDCD)
 240                sca_set_carrier(port);
 241}
 242#endif
 243
 244
 245static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
 246                          u16 rxin)
 247{
 248        struct net_device *dev = port_to_dev(port);
 249        struct sk_buff *skb;
 250        u16 len;
 251        u32 buff;
 252        u32 maxlen;
 253        u8 page;
 254
 255        len = readw(&desc->len);
 256        skb = dev_alloc_skb(len);
 257        if (!skb) {
 258                dev->stats.rx_dropped++;
 259                return;
 260        }
 261
 262        buff = buffer_offset(port, rxin, 0);
 263        page = buff / winsize(card);
 264        buff = buff % winsize(card);
 265        maxlen = winsize(card) - buff;
 266
 267        openwin(card, page);
 268
 269        if (len > maxlen) {
 270                memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
 271                openwin(card, page + 1);
 272                memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
 273        } else
 274                memcpy_fromio(skb->data, winbase(card) + buff, len);
 275
 276#ifndef PAGE0_ALWAYS_MAPPED
 277        openwin(card, 0);       /* select pkt_desc table page back */
 278#endif
 279        skb_put(skb, len);
 280#ifdef DEBUG_PKT
 281        printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
 282        debug_frame(skb);
 283#endif
 284        dev->stats.rx_packets++;
 285        dev->stats.rx_bytes += skb->len;
 286        skb->protocol = hdlc_type_trans(skb, dev);
 287        netif_rx(skb);
 288}
 289
 290
 291/* Receive DMA interrupt service */
 292static inline void sca_rx_intr(port_t *port)
 293{
 294        struct net_device *dev = port_to_dev(port);
 295        u16 dmac = get_dmac_rx(port);
 296        card_t *card = port_to_card(port);
 297        u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
 298
 299        /* Reset DSR status bits */
 300        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 301                DSR_RX(phy_node(port)), card);
 302
 303        if (stat & DSR_BOF)
 304                /* Dropped one or more frames */
 305                dev->stats.rx_over_errors++;
 306
 307        while (1) {
 308                u32 desc_off = desc_offset(port, port->rxin, 0);
 309                pkt_desc __iomem *desc;
 310                u32 cda = sca_inw(dmac + CDAL, card);
 311
 312                if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
 313                        break;  /* No frame received */
 314
 315                desc = desc_address(port, port->rxin, 0);
 316                stat = readb(&desc->stat);
 317                if (!(stat & ST_RX_EOM))
 318                        port->rxpart = 1; /* partial frame received */
 319                else if ((stat & ST_ERROR_MASK) || port->rxpart) {
 320                        dev->stats.rx_errors++;
 321                        if (stat & ST_RX_OVERRUN)
 322                                dev->stats.rx_fifo_errors++;
 323                        else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
 324                                          ST_RX_RESBIT)) || port->rxpart)
 325                                dev->stats.rx_frame_errors++;
 326                        else if (stat & ST_RX_CRC)
 327                                dev->stats.rx_crc_errors++;
 328                        if (stat & ST_RX_EOM)
 329                                port->rxpart = 0; /* received last fragment */
 330                } else
 331                        sca_rx(card, port, desc, port->rxin);
 332
 333                /* Set new error descriptor address */
 334                sca_outw(desc_off, dmac + EDAL, card);
 335                port->rxin = next_desc(port, port->rxin, 0);
 336        }
 337
 338        /* make sure RX DMA is enabled */
 339        sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
 340}
 341
 342
 343/* Transmit DMA interrupt service */
 344static inline void sca_tx_intr(port_t *port)
 345{
 346        struct net_device *dev = port_to_dev(port);
 347        u16 dmac = get_dmac_tx(port);
 348        card_t* card = port_to_card(port);
 349        u8 stat;
 350
 351        spin_lock(&port->lock);
 352
 353        stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
 354
 355        /* Reset DSR status bits */
 356        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 357                DSR_TX(phy_node(port)), card);
 358
 359        while (1) {
 360                pkt_desc __iomem *desc;
 361
 362                u32 desc_off = desc_offset(port, port->txlast, 1);
 363                u32 cda = sca_inw(dmac + CDAL, card);
 364                if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
 365                        break;  /* Transmitter is/will_be sending this frame */
 366
 367                desc = desc_address(port, port->txlast, 1);
 368                dev->stats.tx_packets++;
 369                dev->stats.tx_bytes += readw(&desc->len);
 370                writeb(0, &desc->stat); /* Free descriptor */
 371                port->txlast = next_desc(port, port->txlast, 1);
 372        }
 373
 374        netif_wake_queue(dev);
 375        spin_unlock(&port->lock);
 376}
 377
 378
 379static irqreturn_t sca_intr(int irq, void* dev_id)
 380{
 381        card_t *card = dev_id;
 382        int i;
 383        u8 stat;
 384        int handled = 0;
 385        u8 page = sca_get_page(card);
 386
 387        while((stat = sca_intr_status(card)) != 0) {
 388                handled = 1;
 389                for (i = 0; i < 2; i++) {
 390                        port_t *port = get_port(card, i);
 391                        if (port) {
 392                                if (stat & SCA_INTR_MSCI(i))
 393                                        sca_msci_intr(port);
 394
 395                                if (stat & SCA_INTR_DMAC_RX(i))
 396                                        sca_rx_intr(port);
 397
 398                                if (stat & SCA_INTR_DMAC_TX(i))
 399                                        sca_tx_intr(port);
 400                        }
 401                }
 402        }
 403
 404        openwin(card, page);            /* Restore original page */
 405        return IRQ_RETVAL(handled);
 406}
 407
 408
 409static void sca_set_port(port_t *port)
 410{
 411        card_t* card = port_to_card(port);
 412        u16 msci = get_msci(port);
 413        u8 md2 = sca_in(msci + MD2, card);
 414        unsigned int tmc, br = 10, brv = 1024;
 415
 416
 417        if (port->settings.clock_rate > 0) {
 418                /* Try lower br for better accuracy*/
 419                do {
 420                        br--;
 421                        brv >>= 1; /* brv = 2^9 = 512 max in specs */
 422
 423                        /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
 424                        tmc = CLOCK_BASE / brv / port->settings.clock_rate;
 425                }while (br > 1 && tmc <= 128);
 426
 427                if (tmc < 1) {
 428                        tmc = 1;
 429                        br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
 430                        brv = 1;
 431                } else if (tmc > 255)
 432                        tmc = 256; /* tmc=0 means 256 - low baud rates */
 433
 434                port->settings.clock_rate = CLOCK_BASE / brv / tmc;
 435        } else {
 436                br = 9; /* Minimum clock rate */
 437                tmc = 256;      /* 8bit = 0 */
 438                port->settings.clock_rate = CLOCK_BASE / (256 * 512);
 439        }
 440
 441        port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
 442        port->txs = (port->txs & ~CLK_BRG_MASK) | br;
 443        port->tmc = tmc;
 444
 445        /* baud divisor - time constant*/
 446        sca_out(port->tmc, msci + TMC, card);
 447
 448        /* Set BRG bits */
 449        sca_out(port->rxs, msci + RXS, card);
 450        sca_out(port->txs, msci + TXS, card);
 451
 452        if (port->settings.loopback)
 453                md2 |= MD2_LOOPBACK;
 454        else
 455                md2 &= ~MD2_LOOPBACK;
 456
 457        sca_out(md2, msci + MD2, card);
 458
 459}
 460
 461
 462static void sca_open(struct net_device *dev)
 463{
 464        port_t *port = dev_to_port(dev);
 465        card_t* card = port_to_card(port);
 466        u16 msci = get_msci(port);
 467        u8 md0, md2;
 468
 469        switch(port->encoding) {
 470        case ENCODING_NRZ:      md2 = MD2_NRZ;          break;
 471        case ENCODING_NRZI:     md2 = MD2_NRZI;         break;
 472        case ENCODING_FM_MARK:  md2 = MD2_FM_MARK;      break;
 473        case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE;     break;
 474        default:                md2 = MD2_MANCHESTER;
 475        }
 476
 477        if (port->settings.loopback)
 478                md2 |= MD2_LOOPBACK;
 479
 480        switch(port->parity) {
 481        case PARITY_CRC16_PR0:       md0 = MD0_HDLC | MD0_CRC_16_0;  break;
 482        case PARITY_CRC16_PR1:       md0 = MD0_HDLC | MD0_CRC_16;    break;
 483        case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
 484        case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU;   break;
 485        default:                     md0 = MD0_HDLC | MD0_CRC_NONE;
 486        }
 487
 488        sca_out(CMD_RESET, msci + CMD, card);
 489        sca_out(md0, msci + MD0, card);
 490        sca_out(0x00, msci + MD1, card); /* no address field check */
 491        sca_out(md2, msci + MD2, card);
 492        sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
 493        sca_out(CTL_IDLE, msci + CTL, card);
 494
 495        /* Allow at least 8 bytes before requesting RX DMA operation */
 496        /* TX with higher priority and possibly with shorter transfers */
 497        sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
 498        sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
 499        sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
 500
 501/* We're using the following interrupts:
 502   - TXINT (DMAC completed all transmisions, underrun or DCD change)
 503   - all DMA interrupts
 504*/
 505        sca_set_carrier(port);
 506
 507        /* MSCI TX INT and RX INT A IRQ enable */
 508        sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
 509        sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
 510        sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
 511                IER0, card); /* TXINT and RXINT */
 512        /* enable DMA IRQ */
 513        sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
 514                IER1, card);
 515
 516        sca_out(port->tmc, msci + TMC, card); /* Restore registers */
 517        sca_out(port->rxs, msci + RXS, card);
 518        sca_out(port->txs, msci + TXS, card);
 519        sca_out(CMD_TX_ENABLE, msci + CMD, card);
 520        sca_out(CMD_RX_ENABLE, msci + CMD, card);
 521
 522        netif_start_queue(dev);
 523}
 524
 525
 526static void sca_close(struct net_device *dev)
 527{
 528        port_t *port = dev_to_port(dev);
 529        card_t* card = port_to_card(port);
 530
 531        /* reset channel */
 532        sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
 533        /* disable MSCI interrupts */
 534        sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
 535                IER0, card);
 536        /* disable DMA interrupts */
 537        sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
 538                IER1, card);
 539
 540        netif_stop_queue(dev);
 541}
 542
 543
 544static int sca_attach(struct net_device *dev, unsigned short encoding,
 545                      unsigned short parity)
 546{
 547        if (encoding != ENCODING_NRZ &&
 548            encoding != ENCODING_NRZI &&
 549            encoding != ENCODING_FM_MARK &&
 550            encoding != ENCODING_FM_SPACE &&
 551            encoding != ENCODING_MANCHESTER)
 552                return -EINVAL;
 553
 554        if (parity != PARITY_NONE &&
 555            parity != PARITY_CRC16_PR0 &&
 556            parity != PARITY_CRC16_PR1 &&
 557            parity != PARITY_CRC16_PR0_CCITT &&
 558            parity != PARITY_CRC16_PR1_CCITT)
 559                return -EINVAL;
 560
 561        dev_to_port(dev)->encoding = encoding;
 562        dev_to_port(dev)->parity = parity;
 563        return 0;
 564}
 565
 566
 567#ifdef DEBUG_RINGS
 568static void sca_dump_rings(struct net_device *dev)
 569{
 570        port_t *port = dev_to_port(dev);
 571        card_t *card = port_to_card(port);
 572        u16 cnt;
 573#ifndef PAGE0_ALWAYS_MAPPED
 574        u8 page = sca_get_page(card);
 575
 576        openwin(card, 0);
 577#endif
 578
 579        printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
 580               sca_inw(get_dmac_rx(port) + CDAL, card),
 581               sca_inw(get_dmac_rx(port) + EDAL, card),
 582               sca_in(DSR_RX(phy_node(port)), card), port->rxin,
 583               sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
 584        for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
 585                pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
 586        pr_cont("\n");
 587
 588        printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
 589               "last=%u %sactive",
 590               sca_inw(get_dmac_tx(port) + CDAL, card),
 591               sca_inw(get_dmac_tx(port) + EDAL, card),
 592               sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
 593               sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
 594
 595        for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
 596                pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
 597        pr_cont("\n");
 598
 599        printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x,"
 600               " FST: %02x CST: %02x %02x\n",
 601               sca_in(get_msci(port) + MD0, card),
 602               sca_in(get_msci(port) + MD1, card),
 603               sca_in(get_msci(port) + MD2, card),
 604               sca_in(get_msci(port) + ST0, card),
 605               sca_in(get_msci(port) + ST1, card),
 606               sca_in(get_msci(port) + ST2, card),
 607               sca_in(get_msci(port) + ST3, card),
 608               sca_in(get_msci(port) + FST, card),
 609               sca_in(get_msci(port) + CST0, card),
 610               sca_in(get_msci(port) + CST1, card));
 611
 612        printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
 613               sca_in(ISR1, card), sca_in(ISR2, card));
 614
 615#ifndef PAGE0_ALWAYS_MAPPED
 616        openwin(card, page); /* Restore original page */
 617#endif
 618}
 619#endif /* DEBUG_RINGS */
 620
 621
 622static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
 623{
 624        port_t *port = dev_to_port(dev);
 625        card_t *card = port_to_card(port);
 626        pkt_desc __iomem *desc;
 627        u32 buff, len;
 628        u8 page;
 629        u32 maxlen;
 630
 631        spin_lock_irq(&port->lock);
 632
 633        desc = desc_address(port, port->txin + 1, 1);
 634        BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
 635
 636#ifdef DEBUG_PKT
 637        printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
 638        debug_frame(skb);
 639#endif
 640
 641        desc = desc_address(port, port->txin, 1);
 642        buff = buffer_offset(port, port->txin, 1);
 643        len = skb->len;
 644        page = buff / winsize(card);
 645        buff = buff % winsize(card);
 646        maxlen = winsize(card) - buff;
 647
 648        openwin(card, page);
 649        if (len > maxlen) {
 650                memcpy_toio(winbase(card) + buff, skb->data, maxlen);
 651                openwin(card, page + 1);
 652                memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
 653        } else
 654                memcpy_toio(winbase(card) + buff, skb->data, len);
 655
 656#ifndef PAGE0_ALWAYS_MAPPED
 657        openwin(card, 0);       /* select pkt_desc table page back */
 658#endif
 659        writew(len, &desc->len);
 660        writeb(ST_TX_EOM, &desc->stat);
 661
 662        port->txin = next_desc(port, port->txin, 1);
 663        sca_outw(desc_offset(port, port->txin, 1),
 664                 get_dmac_tx(port) + EDAL, card);
 665
 666        sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
 667
 668        desc = desc_address(port, port->txin + 1, 1);
 669        if (readb(&desc->stat)) /* allow 1 packet gap */
 670                netif_stop_queue(dev);
 671
 672        spin_unlock_irq(&port->lock);
 673
 674        dev_kfree_skb(skb);
 675        return NETDEV_TX_OK;
 676}
 677
 678
 679#ifdef NEED_DETECT_RAM
 680static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase,
 681                                    u32 ramsize)
 682{
 683        /* Round RAM size to 32 bits, fill from end to start */
 684        u32 i = ramsize &= ~3;
 685        u32 size = winsize(card);
 686
 687        openwin(card, (i - 4) / size); /* select last window */
 688
 689        do {
 690                i -= 4;
 691                if ((i + 4) % size == 0)
 692                        openwin(card, i / size);
 693                writel(i ^ 0x12345678, rambase + i % size);
 694        } while (i > 0);
 695
 696        for (i = 0; i < ramsize ; i += 4) {
 697                if (i % size == 0)
 698                        openwin(card, i / size);
 699
 700                if (readl(rambase + i % size) != (i ^ 0x12345678))
 701                        break;
 702        }
 703
 704        return i;
 705}
 706#endif /* NEED_DETECT_RAM */
 707
 708
 709static void __devinit sca_init(card_t *card, int wait_states)
 710{
 711        sca_out(wait_states, WCRL, card); /* Wait Control */
 712        sca_out(wait_states, WCRM, card);
 713        sca_out(wait_states, WCRH, card);
 714
 715        sca_out(0, DMER, card); /* DMA Master disable */
 716        sca_out(0x03, PCR, card); /* DMA priority */
 717        sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
 718        sca_out(0, DSR_TX(0), card);
 719        sca_out(0, DSR_RX(1), card);
 720        sca_out(0, DSR_TX(1), card);
 721        sca_out(DMER_DME, DMER, card); /* DMA Master enable */
 722}
 723