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57#include <linux/fs.h>
58#include <linux/init.h>
59#include <linux/types.h>
60#include <linux/errno.h>
61#include <linux/kernel.h>
62#include <linux/slab.h>
63#include <linux/vmalloc.h>
64#include <linux/ioport.h>
65#include <linux/delay.h>
66#include <linux/pci.h>
67#include <linux/wait.h>
68#include <linux/spinlock.h>
69#include <linux/sched.h>
70#include <linux/interrupt.h>
71#include <linux/blkdev.h>
72#include <linux/firmware.h>
73#include <linux/module.h>
74#include <linux/moduleparam.h>
75#include <linux/libata.h>
76#include <linux/hdreg.h>
77#include <linux/reboot.h>
78#include <linux/stringify.h>
79#include <asm/io.h>
80#include <asm/irq.h>
81#include <asm/processor.h>
82#include <scsi/scsi.h>
83#include <scsi/scsi_host.h>
84#include <scsi/scsi_tcq.h>
85#include <scsi/scsi_eh.h>
86#include <scsi/scsi_cmnd.h>
87#include "ipr.h"
88
89
90
91
92static LIST_HEAD(ipr_ioa_head);
93static unsigned int ipr_log_level = IPR_DEFAULT_LOG_LEVEL;
94static unsigned int ipr_max_speed = 1;
95static int ipr_testmode = 0;
96static unsigned int ipr_fastfail = 0;
97static unsigned int ipr_transop_timeout = 0;
98static unsigned int ipr_debug = 0;
99static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS;
100static unsigned int ipr_dual_ioa_raid = 1;
101static DEFINE_SPINLOCK(ipr_driver_lock);
102
103
104static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
105 {
106 .mailbox = 0x0042C,
107 .cache_line_size = 0x20,
108 {
109 .set_interrupt_mask_reg = 0x0022C,
110 .clr_interrupt_mask_reg = 0x00230,
111 .clr_interrupt_mask_reg32 = 0x00230,
112 .sense_interrupt_mask_reg = 0x0022C,
113 .sense_interrupt_mask_reg32 = 0x0022C,
114 .clr_interrupt_reg = 0x00228,
115 .clr_interrupt_reg32 = 0x00228,
116 .sense_interrupt_reg = 0x00224,
117 .sense_interrupt_reg32 = 0x00224,
118 .ioarrin_reg = 0x00404,
119 .sense_uproc_interrupt_reg = 0x00214,
120 .sense_uproc_interrupt_reg32 = 0x00214,
121 .set_uproc_interrupt_reg = 0x00214,
122 .set_uproc_interrupt_reg32 = 0x00214,
123 .clr_uproc_interrupt_reg = 0x00218,
124 .clr_uproc_interrupt_reg32 = 0x00218
125 }
126 },
127 {
128 .mailbox = 0x0052C,
129 .cache_line_size = 0x20,
130 {
131 .set_interrupt_mask_reg = 0x00288,
132 .clr_interrupt_mask_reg = 0x0028C,
133 .clr_interrupt_mask_reg32 = 0x0028C,
134 .sense_interrupt_mask_reg = 0x00288,
135 .sense_interrupt_mask_reg32 = 0x00288,
136 .clr_interrupt_reg = 0x00284,
137 .clr_interrupt_reg32 = 0x00284,
138 .sense_interrupt_reg = 0x00280,
139 .sense_interrupt_reg32 = 0x00280,
140 .ioarrin_reg = 0x00504,
141 .sense_uproc_interrupt_reg = 0x00290,
142 .sense_uproc_interrupt_reg32 = 0x00290,
143 .set_uproc_interrupt_reg = 0x00290,
144 .set_uproc_interrupt_reg32 = 0x00290,
145 .clr_uproc_interrupt_reg = 0x00294,
146 .clr_uproc_interrupt_reg32 = 0x00294
147 }
148 },
149 {
150 .mailbox = 0x00044,
151 .cache_line_size = 0x20,
152 {
153 .set_interrupt_mask_reg = 0x00010,
154 .clr_interrupt_mask_reg = 0x00018,
155 .clr_interrupt_mask_reg32 = 0x0001C,
156 .sense_interrupt_mask_reg = 0x00010,
157 .sense_interrupt_mask_reg32 = 0x00014,
158 .clr_interrupt_reg = 0x00008,
159 .clr_interrupt_reg32 = 0x0000C,
160 .sense_interrupt_reg = 0x00000,
161 .sense_interrupt_reg32 = 0x00004,
162 .ioarrin_reg = 0x00070,
163 .sense_uproc_interrupt_reg = 0x00020,
164 .sense_uproc_interrupt_reg32 = 0x00024,
165 .set_uproc_interrupt_reg = 0x00020,
166 .set_uproc_interrupt_reg32 = 0x00024,
167 .clr_uproc_interrupt_reg = 0x00028,
168 .clr_uproc_interrupt_reg32 = 0x0002C,
169 .init_feedback_reg = 0x0005C,
170 .dump_addr_reg = 0x00064,
171 .dump_data_reg = 0x00068,
172 .endian_swap_reg = 0x00084
173 }
174 },
175};
176
177static const struct ipr_chip_t ipr_chip[] = {
178 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
179 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
180 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
181 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
182 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
183 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
184 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
185 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
186 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
187};
188
189static int ipr_max_bus_speeds [] = {
190 IPR_80MBs_SCSI_RATE, IPR_U160_SCSI_RATE, IPR_U320_SCSI_RATE
191};
192
193MODULE_AUTHOR("Brian King <brking@us.ibm.com>");
194MODULE_DESCRIPTION("IBM Power RAID SCSI Adapter Driver");
195module_param_named(max_speed, ipr_max_speed, uint, 0);
196MODULE_PARM_DESC(max_speed, "Maximum bus speed (0-2). Default: 1=U160. Speeds: 0=80 MB/s, 1=U160, 2=U320");
197module_param_named(log_level, ipr_log_level, uint, 0);
198MODULE_PARM_DESC(log_level, "Set to 0 - 4 for increasing verbosity of device driver");
199module_param_named(testmode, ipr_testmode, int, 0);
200MODULE_PARM_DESC(testmode, "DANGEROUS!!! Allows unsupported configurations");
201module_param_named(fastfail, ipr_fastfail, int, S_IRUGO | S_IWUSR);
202MODULE_PARM_DESC(fastfail, "Reduce timeouts and retries");
203module_param_named(transop_timeout, ipr_transop_timeout, int, 0);
204MODULE_PARM_DESC(transop_timeout, "Time in seconds to wait for adapter to come operational (default: 300)");
205module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR);
206MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)");
207module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0);
208MODULE_PARM_DESC(dual_ioa_raid, "Enable dual adapter RAID support. Set to 1 to enable. (default: 1)");
209module_param_named(max_devs, ipr_max_devs, int, 0);
210MODULE_PARM_DESC(max_devs, "Specify the maximum number of physical devices. "
211 "[Default=" __stringify(IPR_DEFAULT_SIS64_DEVS) "]");
212MODULE_LICENSE("GPL");
213MODULE_VERSION(IPR_DRIVER_VERSION);
214
215
216static const
217struct ipr_error_table_t ipr_error_table[] = {
218 {0x00000000, 1, IPR_DEFAULT_LOG_LEVEL,
219 "8155: An unknown error was received"},
220 {0x00330000, 0, 0,
221 "Soft underlength error"},
222 {0x005A0000, 0, 0,
223 "Command to be cancelled not found"},
224 {0x00808000, 0, 0,
225 "Qualified success"},
226 {0x01080000, 1, IPR_DEFAULT_LOG_LEVEL,
227 "FFFE: Soft device bus error recovered by the IOA"},
228 {0x01088100, 0, IPR_DEFAULT_LOG_LEVEL,
229 "4101: Soft device bus fabric error"},
230 {0x01100100, 0, IPR_DEFAULT_LOG_LEVEL,
231 "FFFC: Logical block guard error recovered by the device"},
232 {0x01100300, 0, IPR_DEFAULT_LOG_LEVEL,
233 "FFFC: Logical block reference tag error recovered by the device"},
234 {0x01108300, 0, IPR_DEFAULT_LOG_LEVEL,
235 "4171: Recovered scatter list tag / sequence number error"},
236 {0x01109000, 0, IPR_DEFAULT_LOG_LEVEL,
237 "FF3D: Recovered logical block CRC error on IOA to Host transfer"},
238 {0x01109200, 0, IPR_DEFAULT_LOG_LEVEL,
239 "4171: Recovered logical block sequence number error on IOA to Host transfer"},
240 {0x0110A000, 0, IPR_DEFAULT_LOG_LEVEL,
241 "FFFD: Recovered logical block reference tag error detected by the IOA"},
242 {0x0110A100, 0, IPR_DEFAULT_LOG_LEVEL,
243 "FFFD: Logical block guard error recovered by the IOA"},
244 {0x01170600, 0, IPR_DEFAULT_LOG_LEVEL,
245 "FFF9: Device sector reassign successful"},
246 {0x01170900, 0, IPR_DEFAULT_LOG_LEVEL,
247 "FFF7: Media error recovered by device rewrite procedures"},
248 {0x01180200, 0, IPR_DEFAULT_LOG_LEVEL,
249 "7001: IOA sector reassignment successful"},
250 {0x01180500, 0, IPR_DEFAULT_LOG_LEVEL,
251 "FFF9: Soft media error. Sector reassignment recommended"},
252 {0x01180600, 0, IPR_DEFAULT_LOG_LEVEL,
253 "FFF7: Media error recovered by IOA rewrite procedures"},
254 {0x01418000, 0, IPR_DEFAULT_LOG_LEVEL,
255 "FF3D: Soft PCI bus error recovered by the IOA"},
256 {0x01440000, 1, IPR_DEFAULT_LOG_LEVEL,
257 "FFF6: Device hardware error recovered by the IOA"},
258 {0x01448100, 0, IPR_DEFAULT_LOG_LEVEL,
259 "FFF6: Device hardware error recovered by the device"},
260 {0x01448200, 1, IPR_DEFAULT_LOG_LEVEL,
261 "FF3D: Soft IOA error recovered by the IOA"},
262 {0x01448300, 0, IPR_DEFAULT_LOG_LEVEL,
263 "FFFA: Undefined device response recovered by the IOA"},
264 {0x014A0000, 1, IPR_DEFAULT_LOG_LEVEL,
265 "FFF6: Device bus error, message or command phase"},
266 {0x014A8000, 0, IPR_DEFAULT_LOG_LEVEL,
267 "FFFE: Task Management Function failed"},
268 {0x015D0000, 0, IPR_DEFAULT_LOG_LEVEL,
269 "FFF6: Failure prediction threshold exceeded"},
270 {0x015D9200, 0, IPR_DEFAULT_LOG_LEVEL,
271 "8009: Impending cache battery pack failure"},
272 {0x02040400, 0, 0,
273 "34FF: Disk device format in progress"},
274 {0x02048000, 0, IPR_DEFAULT_LOG_LEVEL,
275 "9070: IOA requested reset"},
276 {0x023F0000, 0, 0,
277 "Synchronization required"},
278 {0x024E0000, 0, 0,
279 "No ready, IOA shutdown"},
280 {0x025A0000, 0, 0,
281 "Not ready, IOA has been shutdown"},
282 {0x02670100, 0, IPR_DEFAULT_LOG_LEVEL,
283 "3020: Storage subsystem configuration error"},
284 {0x03110B00, 0, 0,
285 "FFF5: Medium error, data unreadable, recommend reassign"},
286 {0x03110C00, 0, 0,
287 "7000: Medium error, data unreadable, do not reassign"},
288 {0x03310000, 0, IPR_DEFAULT_LOG_LEVEL,
289 "FFF3: Disk media format bad"},
290 {0x04050000, 0, IPR_DEFAULT_LOG_LEVEL,
291 "3002: Addressed device failed to respond to selection"},
292 {0x04080000, 1, IPR_DEFAULT_LOG_LEVEL,
293 "3100: Device bus error"},
294 {0x04080100, 0, IPR_DEFAULT_LOG_LEVEL,
295 "3109: IOA timed out a device command"},
296 {0x04088000, 0, 0,
297 "3120: SCSI bus is not operational"},
298 {0x04088100, 0, IPR_DEFAULT_LOG_LEVEL,
299 "4100: Hard device bus fabric error"},
300 {0x04100100, 0, IPR_DEFAULT_LOG_LEVEL,
301 "310C: Logical block guard error detected by the device"},
302 {0x04100300, 0, IPR_DEFAULT_LOG_LEVEL,
303 "310C: Logical block reference tag error detected by the device"},
304 {0x04108300, 1, IPR_DEFAULT_LOG_LEVEL,
305 "4170: Scatter list tag / sequence number error"},
306 {0x04109000, 1, IPR_DEFAULT_LOG_LEVEL,
307 "8150: Logical block CRC error on IOA to Host transfer"},
308 {0x04109200, 1, IPR_DEFAULT_LOG_LEVEL,
309 "4170: Logical block sequence number error on IOA to Host transfer"},
310 {0x0410A000, 0, IPR_DEFAULT_LOG_LEVEL,
311 "310D: Logical block reference tag error detected by the IOA"},
312 {0x0410A100, 0, IPR_DEFAULT_LOG_LEVEL,
313 "310D: Logical block guard error detected by the IOA"},
314 {0x04118000, 0, IPR_DEFAULT_LOG_LEVEL,
315 "9000: IOA reserved area data check"},
316 {0x04118100, 0, IPR_DEFAULT_LOG_LEVEL,
317 "9001: IOA reserved area invalid data pattern"},
318 {0x04118200, 0, IPR_DEFAULT_LOG_LEVEL,
319 "9002: IOA reserved area LRC error"},
320 {0x04118300, 1, IPR_DEFAULT_LOG_LEVEL,
321 "Hardware Error, IOA metadata access error"},
322 {0x04320000, 0, IPR_DEFAULT_LOG_LEVEL,
323 "102E: Out of alternate sectors for disk storage"},
324 {0x04330000, 1, IPR_DEFAULT_LOG_LEVEL,
325 "FFF4: Data transfer underlength error"},
326 {0x04338000, 1, IPR_DEFAULT_LOG_LEVEL,
327 "FFF4: Data transfer overlength error"},
328 {0x043E0100, 0, IPR_DEFAULT_LOG_LEVEL,
329 "3400: Logical unit failure"},
330 {0x04408500, 0, IPR_DEFAULT_LOG_LEVEL,
331 "FFF4: Device microcode is corrupt"},
332 {0x04418000, 1, IPR_DEFAULT_LOG_LEVEL,
333 "8150: PCI bus error"},
334 {0x04430000, 1, 0,
335 "Unsupported device bus message received"},
336 {0x04440000, 1, IPR_DEFAULT_LOG_LEVEL,
337 "FFF4: Disk device problem"},
338 {0x04448200, 1, IPR_DEFAULT_LOG_LEVEL,
339 "8150: Permanent IOA failure"},
340 {0x04448300, 0, IPR_DEFAULT_LOG_LEVEL,
341 "3010: Disk device returned wrong response to IOA"},
342 {0x04448400, 0, IPR_DEFAULT_LOG_LEVEL,
343 "8151: IOA microcode error"},
344 {0x04448500, 0, 0,
345 "Device bus status error"},
346 {0x04448600, 0, IPR_DEFAULT_LOG_LEVEL,
347 "8157: IOA error requiring IOA reset to recover"},
348 {0x04448700, 0, 0,
349 "ATA device status error"},
350 {0x04490000, 0, 0,
351 "Message reject received from the device"},
352 {0x04449200, 0, IPR_DEFAULT_LOG_LEVEL,
353 "8008: A permanent cache battery pack failure occurred"},
354 {0x0444A000, 0, IPR_DEFAULT_LOG_LEVEL,
355 "9090: Disk unit has been modified after the last known status"},
356 {0x0444A200, 0, IPR_DEFAULT_LOG_LEVEL,
357 "9081: IOA detected device error"},
358 {0x0444A300, 0, IPR_DEFAULT_LOG_LEVEL,
359 "9082: IOA detected device error"},
360 {0x044A0000, 1, IPR_DEFAULT_LOG_LEVEL,
361 "3110: Device bus error, message or command phase"},
362 {0x044A8000, 1, IPR_DEFAULT_LOG_LEVEL,
363 "3110: SAS Command / Task Management Function failed"},
364 {0x04670400, 0, IPR_DEFAULT_LOG_LEVEL,
365 "9091: Incorrect hardware configuration change has been detected"},
366 {0x04678000, 0, IPR_DEFAULT_LOG_LEVEL,
367 "9073: Invalid multi-adapter configuration"},
368 {0x04678100, 0, IPR_DEFAULT_LOG_LEVEL,
369 "4010: Incorrect connection between cascaded expanders"},
370 {0x04678200, 0, IPR_DEFAULT_LOG_LEVEL,
371 "4020: Connections exceed IOA design limits"},
372 {0x04678300, 0, IPR_DEFAULT_LOG_LEVEL,
373 "4030: Incorrect multipath connection"},
374 {0x04679000, 0, IPR_DEFAULT_LOG_LEVEL,
375 "4110: Unsupported enclosure function"},
376 {0x046E0000, 0, IPR_DEFAULT_LOG_LEVEL,
377 "FFF4: Command to logical unit failed"},
378 {0x05240000, 1, 0,
379 "Illegal request, invalid request type or request packet"},
380 {0x05250000, 0, 0,
381 "Illegal request, invalid resource handle"},
382 {0x05258000, 0, 0,
383 "Illegal request, commands not allowed to this device"},
384 {0x05258100, 0, 0,
385 "Illegal request, command not allowed to a secondary adapter"},
386 {0x05258200, 0, 0,
387 "Illegal request, command not allowed to a non-optimized resource"},
388 {0x05260000, 0, 0,
389 "Illegal request, invalid field in parameter list"},
390 {0x05260100, 0, 0,
391 "Illegal request, parameter not supported"},
392 {0x05260200, 0, 0,
393 "Illegal request, parameter value invalid"},
394 {0x052C0000, 0, 0,
395 "Illegal request, command sequence error"},
396 {0x052C8000, 1, 0,
397 "Illegal request, dual adapter support not enabled"},
398 {0x06040500, 0, IPR_DEFAULT_LOG_LEVEL,
399 "9031: Array protection temporarily suspended, protection resuming"},
400 {0x06040600, 0, IPR_DEFAULT_LOG_LEVEL,
401 "9040: Array protection temporarily suspended, protection resuming"},
402 {0x06288000, 0, IPR_DEFAULT_LOG_LEVEL,
403 "3140: Device bus not ready to ready transition"},
404 {0x06290000, 0, IPR_DEFAULT_LOG_LEVEL,
405 "FFFB: SCSI bus was reset"},
406 {0x06290500, 0, 0,
407 "FFFE: SCSI bus transition to single ended"},
408 {0x06290600, 0, 0,
409 "FFFE: SCSI bus transition to LVD"},
410 {0x06298000, 0, IPR_DEFAULT_LOG_LEVEL,
411 "FFFB: SCSI bus was reset by another initiator"},
412 {0x063F0300, 0, IPR_DEFAULT_LOG_LEVEL,
413 "3029: A device replacement has occurred"},
414 {0x064C8000, 0, IPR_DEFAULT_LOG_LEVEL,
415 "9051: IOA cache data exists for a missing or failed device"},
416 {0x064C8100, 0, IPR_DEFAULT_LOG_LEVEL,
417 "9055: Auxiliary cache IOA contains cache data needed by the primary IOA"},
418 {0x06670100, 0, IPR_DEFAULT_LOG_LEVEL,
419 "9025: Disk unit is not supported at its physical location"},
420 {0x06670600, 0, IPR_DEFAULT_LOG_LEVEL,
421 "3020: IOA detected a SCSI bus configuration error"},
422 {0x06678000, 0, IPR_DEFAULT_LOG_LEVEL,
423 "3150: SCSI bus configuration error"},
424 {0x06678100, 0, IPR_DEFAULT_LOG_LEVEL,
425 "9074: Asymmetric advanced function disk configuration"},
426 {0x06678300, 0, IPR_DEFAULT_LOG_LEVEL,
427 "4040: Incomplete multipath connection between IOA and enclosure"},
428 {0x06678400, 0, IPR_DEFAULT_LOG_LEVEL,
429 "4041: Incomplete multipath connection between enclosure and device"},
430 {0x06678500, 0, IPR_DEFAULT_LOG_LEVEL,
431 "9075: Incomplete multipath connection between IOA and remote IOA"},
432 {0x06678600, 0, IPR_DEFAULT_LOG_LEVEL,
433 "9076: Configuration error, missing remote IOA"},
434 {0x06679100, 0, IPR_DEFAULT_LOG_LEVEL,
435 "4050: Enclosure does not support a required multipath function"},
436 {0x06690000, 0, IPR_DEFAULT_LOG_LEVEL,
437 "4070: Logically bad block written on device"},
438 {0x06690200, 0, IPR_DEFAULT_LOG_LEVEL,
439 "9041: Array protection temporarily suspended"},
440 {0x06698200, 0, IPR_DEFAULT_LOG_LEVEL,
441 "9042: Corrupt array parity detected on specified device"},
442 {0x066B0200, 0, IPR_DEFAULT_LOG_LEVEL,
443 "9030: Array no longer protected due to missing or failed disk unit"},
444 {0x066B8000, 0, IPR_DEFAULT_LOG_LEVEL,
445 "9071: Link operational transition"},
446 {0x066B8100, 0, IPR_DEFAULT_LOG_LEVEL,
447 "9072: Link not operational transition"},
448 {0x066B8200, 0, IPR_DEFAULT_LOG_LEVEL,
449 "9032: Array exposed but still protected"},
450 {0x066B8300, 0, IPR_DEFAULT_LOG_LEVEL + 1,
451 "70DD: Device forced failed by disrupt device command"},
452 {0x066B9100, 0, IPR_DEFAULT_LOG_LEVEL,
453 "4061: Multipath redundancy level got better"},
454 {0x066B9200, 0, IPR_DEFAULT_LOG_LEVEL,
455 "4060: Multipath redundancy level got worse"},
456 {0x07270000, 0, 0,
457 "Failure due to other device"},
458 {0x07278000, 0, IPR_DEFAULT_LOG_LEVEL,
459 "9008: IOA does not support functions expected by devices"},
460 {0x07278100, 0, IPR_DEFAULT_LOG_LEVEL,
461 "9010: Cache data associated with attached devices cannot be found"},
462 {0x07278200, 0, IPR_DEFAULT_LOG_LEVEL,
463 "9011: Cache data belongs to devices other than those attached"},
464 {0x07278400, 0, IPR_DEFAULT_LOG_LEVEL,
465 "9020: Array missing 2 or more devices with only 1 device present"},
466 {0x07278500, 0, IPR_DEFAULT_LOG_LEVEL,
467 "9021: Array missing 2 or more devices with 2 or more devices present"},
468 {0x07278600, 0, IPR_DEFAULT_LOG_LEVEL,
469 "9022: Exposed array is missing a required device"},
470 {0x07278700, 0, IPR_DEFAULT_LOG_LEVEL,
471 "9023: Array member(s) not at required physical locations"},
472 {0x07278800, 0, IPR_DEFAULT_LOG_LEVEL,
473 "9024: Array not functional due to present hardware configuration"},
474 {0x07278900, 0, IPR_DEFAULT_LOG_LEVEL,
475 "9026: Array not functional due to present hardware configuration"},
476 {0x07278A00, 0, IPR_DEFAULT_LOG_LEVEL,
477 "9027: Array is missing a device and parity is out of sync"},
478 {0x07278B00, 0, IPR_DEFAULT_LOG_LEVEL,
479 "9028: Maximum number of arrays already exist"},
480 {0x07278C00, 0, IPR_DEFAULT_LOG_LEVEL,
481 "9050: Required cache data cannot be located for a disk unit"},
482 {0x07278D00, 0, IPR_DEFAULT_LOG_LEVEL,
483 "9052: Cache data exists for a device that has been modified"},
484 {0x07278F00, 0, IPR_DEFAULT_LOG_LEVEL,
485 "9054: IOA resources not available due to previous problems"},
486 {0x07279100, 0, IPR_DEFAULT_LOG_LEVEL,
487 "9092: Disk unit requires initialization before use"},
488 {0x07279200, 0, IPR_DEFAULT_LOG_LEVEL,
489 "9029: Incorrect hardware configuration change has been detected"},
490 {0x07279600, 0, IPR_DEFAULT_LOG_LEVEL,
491 "9060: One or more disk pairs are missing from an array"},
492 {0x07279700, 0, IPR_DEFAULT_LOG_LEVEL,
493 "9061: One or more disks are missing from an array"},
494 {0x07279800, 0, IPR_DEFAULT_LOG_LEVEL,
495 "9062: One or more disks are missing from an array"},
496 {0x07279900, 0, IPR_DEFAULT_LOG_LEVEL,
497 "9063: Maximum number of functional arrays has been exceeded"},
498 {0x0B260000, 0, 0,
499 "Aborted command, invalid descriptor"},
500 {0x0B5A0000, 0, 0,
501 "Command terminated by host"}
502};
503
504static const struct ipr_ses_table_entry ipr_ses_table[] = {
505 { "2104-DL1 ", "XXXXXXXXXXXXXXXX", 80 },
506 { "2104-TL1 ", "XXXXXXXXXXXXXXXX", 80 },
507 { "HSBP07M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
508 { "HSBP05M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
509 { "HSBP05M S U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
510 { "HSBP06E ASU2SCSI", "XXXXXXXXXXXXXXXX", 80 },
511 { "2104-DU3 ", "XXXXXXXXXXXXXXXX", 160 },
512 { "2104-TU3 ", "XXXXXXXXXXXXXXXX", 160 },
513 { "HSBP04C RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
514 { "HSBP06E RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
515 { "St V1S2 ", "XXXXXXXXXXXXXXXX", 160 },
516 { "HSBPD4M PU3SCSI", "XXXXXXX*XXXXXXXX", 160 },
517 { "VSBPD1H U3SCSI", "XXXXXXX*XXXXXXXX", 160 }
518};
519
520
521
522
523static int ipr_reset_alert(struct ipr_cmnd *);
524static void ipr_process_ccn(struct ipr_cmnd *);
525static void ipr_process_error(struct ipr_cmnd *);
526static void ipr_reset_ioa_job(struct ipr_cmnd *);
527static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *,
528 enum ipr_shutdown_type);
529
530#ifdef CONFIG_SCSI_IPR_TRACE
531
532
533
534
535
536
537
538
539
540static void ipr_trc_hook(struct ipr_cmnd *ipr_cmd,
541 u8 type, u32 add_data)
542{
543 struct ipr_trace_entry *trace_entry;
544 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
545
546 trace_entry = &ioa_cfg->trace[ioa_cfg->trace_index++];
547 trace_entry->time = jiffies;
548 trace_entry->op_code = ipr_cmd->ioarcb.cmd_pkt.cdb[0];
549 trace_entry->type = type;
550 if (ipr_cmd->ioa_cfg->sis64)
551 trace_entry->ata_op_code = ipr_cmd->i.ata_ioadl.regs.command;
552 else
553 trace_entry->ata_op_code = ipr_cmd->ioarcb.u.add_data.u.regs.command;
554 trace_entry->cmd_index = ipr_cmd->cmd_index & 0xff;
555 trace_entry->res_handle = ipr_cmd->ioarcb.res_handle;
556 trace_entry->u.add_data = add_data;
557}
558#else
559#define ipr_trc_hook(ipr_cmd, type, add_data) do { } while(0)
560#endif
561
562
563
564
565
566
567
568
569static void ipr_reinit_ipr_cmnd(struct ipr_cmnd *ipr_cmd)
570{
571 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
572 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
573 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
574 dma_addr_t dma_addr = ipr_cmd->dma_addr;
575
576 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
577 ioarcb->data_transfer_length = 0;
578 ioarcb->read_data_transfer_length = 0;
579 ioarcb->ioadl_len = 0;
580 ioarcb->read_ioadl_len = 0;
581
582 if (ipr_cmd->ioa_cfg->sis64) {
583 ioarcb->u.sis64_addr_data.data_ioadl_addr =
584 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
585 ioasa64->u.gata.status = 0;
586 } else {
587 ioarcb->write_ioadl_addr =
588 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
589 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
590 ioasa->u.gata.status = 0;
591 }
592
593 ioasa->hdr.ioasc = 0;
594 ioasa->hdr.residual_data_len = 0;
595 ipr_cmd->scsi_cmd = NULL;
596 ipr_cmd->qc = NULL;
597 ipr_cmd->sense_buffer[0] = 0;
598 ipr_cmd->dma_use_sg = 0;
599}
600
601
602
603
604
605
606
607
608static void ipr_init_ipr_cmnd(struct ipr_cmnd *ipr_cmd)
609{
610 ipr_reinit_ipr_cmnd(ipr_cmd);
611 ipr_cmd->u.scratch = 0;
612 ipr_cmd->sibling = NULL;
613 init_timer(&ipr_cmd->timer);
614}
615
616
617
618
619
620
621
622
623static
624struct ipr_cmnd *ipr_get_free_ipr_cmnd(struct ipr_ioa_cfg *ioa_cfg)
625{
626 struct ipr_cmnd *ipr_cmd;
627
628 ipr_cmd = list_entry(ioa_cfg->free_q.next, struct ipr_cmnd, queue);
629 list_del(&ipr_cmd->queue);
630 ipr_init_ipr_cmnd(ipr_cmd);
631
632 return ipr_cmd;
633}
634
635
636
637
638
639
640
641
642
643
644
645
646static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg,
647 u32 clr_ints)
648{
649 volatile u32 int_reg;
650
651
652 ioa_cfg->allow_interrupts = 0;
653
654
655 if (ioa_cfg->sis64)
656 writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);
657 else
658 writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
659
660
661 if (ioa_cfg->sis64)
662 writel(~0, ioa_cfg->regs.clr_interrupt_reg);
663 writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
664 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
665}
666
667
668
669
670
671
672
673
674static int ipr_save_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
675{
676 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
677
678 if (pcix_cmd_reg == 0)
679 return 0;
680
681 if (pci_read_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
682 &ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
683 dev_err(&ioa_cfg->pdev->dev, "Failed to save PCI-X command register\n");
684 return -EIO;
685 }
686
687 ioa_cfg->saved_pcix_cmd_reg |= PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO;
688 return 0;
689}
690
691
692
693
694
695
696
697
698static int ipr_set_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
699{
700 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
701
702 if (pcix_cmd_reg) {
703 if (pci_write_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
704 ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
705 dev_err(&ioa_cfg->pdev->dev, "Failed to setup PCI-X command register\n");
706 return -EIO;
707 }
708 }
709
710 return 0;
711}
712
713
714
715
716
717
718
719
720
721
722
723static void ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
724{
725 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
726 struct ata_queued_cmd *qc = ipr_cmd->qc;
727 struct ipr_sata_port *sata_port = qc->ap->private_data;
728
729 qc->err_mask |= AC_ERR_OTHER;
730 sata_port->ioasa.status |= ATA_BUSY;
731 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
732 ata_qc_complete(qc);
733}
734
735
736
737
738
739
740
741
742
743
744
745static void ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
746{
747 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
748 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
749
750 scsi_cmd->result |= (DID_ERROR << 16);
751
752 scsi_dma_unmap(ipr_cmd->scsi_cmd);
753 scsi_cmd->scsi_done(scsi_cmd);
754 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
755}
756
757
758
759
760
761
762
763
764
765
766static void ipr_fail_all_ops(struct ipr_ioa_cfg *ioa_cfg)
767{
768 struct ipr_cmnd *ipr_cmd, *temp;
769
770 ENTER;
771 list_for_each_entry_safe(ipr_cmd, temp, &ioa_cfg->pending_q, queue) {
772 list_del(&ipr_cmd->queue);
773
774 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_IOA_WAS_RESET);
775 ipr_cmd->s.ioasa.hdr.ilid = cpu_to_be32(IPR_DRIVER_ILID);
776
777 if (ipr_cmd->scsi_cmd)
778 ipr_cmd->done = ipr_scsi_eh_done;
779 else if (ipr_cmd->qc)
780 ipr_cmd->done = ipr_sata_eh_done;
781
782 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH, IPR_IOASC_IOA_WAS_RESET);
783 del_timer(&ipr_cmd->timer);
784 ipr_cmd->done(ipr_cmd);
785 }
786
787 LEAVE;
788}
789
790
791
792
793
794
795
796
797
798
799
800
801static void ipr_send_command(struct ipr_cmnd *ipr_cmd)
802{
803 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
804 dma_addr_t send_dma_addr = ipr_cmd->dma_addr;
805
806 if (ioa_cfg->sis64) {
807
808 send_dma_addr |= 0x1;
809
810
811
812 if (ipr_cmd->dma_use_sg * sizeof(struct ipr_ioadl64_desc) > 128 )
813 send_dma_addr |= 0x4;
814 writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
815 } else
816 writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
817}
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832static void ipr_do_req(struct ipr_cmnd *ipr_cmd,
833 void (*done) (struct ipr_cmnd *),
834 void (*timeout_func) (struct ipr_cmnd *), u32 timeout)
835{
836 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
837
838 list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q);
839
840 ipr_cmd->done = done;
841
842 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
843 ipr_cmd->timer.expires = jiffies + timeout;
844 ipr_cmd->timer.function = (void (*)(unsigned long))timeout_func;
845
846 add_timer(&ipr_cmd->timer);
847
848 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, 0);
849
850 mb();
851
852 ipr_send_command(ipr_cmd);
853}
854
855
856
857
858
859
860
861
862
863
864
865static void ipr_internal_cmd_done(struct ipr_cmnd *ipr_cmd)
866{
867 if (ipr_cmd->sibling)
868 ipr_cmd->sibling = NULL;
869 else
870 complete(&ipr_cmd->completion);
871}
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886static void ipr_init_ioadl(struct ipr_cmnd *ipr_cmd, dma_addr_t dma_addr,
887 u32 len, int flags)
888{
889 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
890 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
891
892 ipr_cmd->dma_use_sg = 1;
893
894 if (ipr_cmd->ioa_cfg->sis64) {
895 ioadl64->flags = cpu_to_be32(flags);
896 ioadl64->data_len = cpu_to_be32(len);
897 ioadl64->address = cpu_to_be64(dma_addr);
898
899 ipr_cmd->ioarcb.ioadl_len =
900 cpu_to_be32(sizeof(struct ipr_ioadl64_desc));
901 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
902 } else {
903 ioadl->flags_and_data_len = cpu_to_be32(flags | len);
904 ioadl->address = cpu_to_be32(dma_addr);
905
906 if (flags == IPR_IOADL_FLAGS_READ_LAST) {
907 ipr_cmd->ioarcb.read_ioadl_len =
908 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
909 ipr_cmd->ioarcb.read_data_transfer_length = cpu_to_be32(len);
910 } else {
911 ipr_cmd->ioarcb.ioadl_len =
912 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
913 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
914 }
915 }
916}
917
918
919
920
921
922
923
924
925
926
927static void ipr_send_blocking_cmd(struct ipr_cmnd *ipr_cmd,
928 void (*timeout_func) (struct ipr_cmnd *ipr_cmd),
929 u32 timeout)
930{
931 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
932
933 init_completion(&ipr_cmd->completion);
934 ipr_do_req(ipr_cmd, ipr_internal_cmd_done, timeout_func, timeout);
935
936 spin_unlock_irq(ioa_cfg->host->host_lock);
937 wait_for_completion(&ipr_cmd->completion);
938 spin_lock_irq(ioa_cfg->host->host_lock);
939}
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type,
955 struct ipr_hostrcb *hostrcb)
956{
957 struct ipr_cmnd *ipr_cmd;
958 struct ipr_ioarcb *ioarcb;
959
960 if (ioa_cfg->allow_cmds) {
961 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
962 list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q);
963 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_pending_q);
964
965 ipr_cmd->u.hostrcb = hostrcb;
966 ioarcb = &ipr_cmd->ioarcb;
967
968 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
969 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_HCAM;
970 ioarcb->cmd_pkt.cdb[0] = IPR_HOST_CONTROLLED_ASYNC;
971 ioarcb->cmd_pkt.cdb[1] = type;
972 ioarcb->cmd_pkt.cdb[7] = (sizeof(hostrcb->hcam) >> 8) & 0xff;
973 ioarcb->cmd_pkt.cdb[8] = sizeof(hostrcb->hcam) & 0xff;
974
975 ipr_init_ioadl(ipr_cmd, hostrcb->hostrcb_dma,
976 sizeof(hostrcb->hcam), IPR_IOADL_FLAGS_READ_LAST);
977
978 if (type == IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE)
979 ipr_cmd->done = ipr_process_ccn;
980 else
981 ipr_cmd->done = ipr_process_error;
982
983 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_IOA_RES_ADDR);
984
985 mb();
986
987 ipr_send_command(ipr_cmd);
988 } else {
989 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
990 }
991}
992
993
994
995
996
997
998
999
1000
1001static void ipr_update_ata_class(struct ipr_resource_entry *res, unsigned int proto)
1002{
1003 switch(proto) {
1004 case IPR_PROTO_SATA:
1005 case IPR_PROTO_SAS_STP:
1006 res->ata_class = ATA_DEV_ATA;
1007 break;
1008 case IPR_PROTO_SATA_ATAPI:
1009 case IPR_PROTO_SAS_STP_ATAPI:
1010 res->ata_class = ATA_DEV_ATAPI;
1011 break;
1012 default:
1013 res->ata_class = ATA_DEV_UNKNOWN;
1014 break;
1015 };
1016}
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026static void ipr_init_res_entry(struct ipr_resource_entry *res,
1027 struct ipr_config_table_entry_wrapper *cfgtew)
1028{
1029 int found = 0;
1030 unsigned int proto;
1031 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1032 struct ipr_resource_entry *gscsi_res = NULL;
1033
1034 res->needs_sync_complete = 0;
1035 res->in_erp = 0;
1036 res->add_to_ml = 0;
1037 res->del_from_ml = 0;
1038 res->resetting_device = 0;
1039 res->sdev = NULL;
1040 res->sata_port = NULL;
1041
1042 if (ioa_cfg->sis64) {
1043 proto = cfgtew->u.cfgte64->proto;
1044 res->res_flags = cfgtew->u.cfgte64->res_flags;
1045 res->qmodel = IPR_QUEUEING_MODEL64(res);
1046 res->type = cfgtew->u.cfgte64->res_type;
1047
1048 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1049 sizeof(res->res_path));
1050
1051 res->bus = 0;
1052 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1053 sizeof(res->dev_lun.scsi_lun));
1054 res->lun = scsilun_to_int(&res->dev_lun);
1055
1056 if (res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1057 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) {
1058 if (gscsi_res->dev_id == cfgtew->u.cfgte64->dev_id) {
1059 found = 1;
1060 res->target = gscsi_res->target;
1061 break;
1062 }
1063 }
1064 if (!found) {
1065 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1066 ioa_cfg->max_devs_supported);
1067 set_bit(res->target, ioa_cfg->target_ids);
1068 }
1069 } else if (res->type == IPR_RES_TYPE_IOAFP) {
1070 res->bus = IPR_IOAFP_VIRTUAL_BUS;
1071 res->target = 0;
1072 } else if (res->type == IPR_RES_TYPE_ARRAY) {
1073 res->bus = IPR_ARRAY_VIRTUAL_BUS;
1074 res->target = find_first_zero_bit(ioa_cfg->array_ids,
1075 ioa_cfg->max_devs_supported);
1076 set_bit(res->target, ioa_cfg->array_ids);
1077 } else if (res->type == IPR_RES_TYPE_VOLUME_SET) {
1078 res->bus = IPR_VSET_VIRTUAL_BUS;
1079 res->target = find_first_zero_bit(ioa_cfg->vset_ids,
1080 ioa_cfg->max_devs_supported);
1081 set_bit(res->target, ioa_cfg->vset_ids);
1082 } else {
1083 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1084 ioa_cfg->max_devs_supported);
1085 set_bit(res->target, ioa_cfg->target_ids);
1086 }
1087 } else {
1088 proto = cfgtew->u.cfgte->proto;
1089 res->qmodel = IPR_QUEUEING_MODEL(res);
1090 res->flags = cfgtew->u.cfgte->flags;
1091 if (res->flags & IPR_IS_IOA_RESOURCE)
1092 res->type = IPR_RES_TYPE_IOAFP;
1093 else
1094 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1095
1096 res->bus = cfgtew->u.cfgte->res_addr.bus;
1097 res->target = cfgtew->u.cfgte->res_addr.target;
1098 res->lun = cfgtew->u.cfgte->res_addr.lun;
1099 res->lun_wwn = get_unaligned_be64(cfgtew->u.cfgte->lun_wwn);
1100 }
1101
1102 ipr_update_ata_class(res, proto);
1103}
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113static int ipr_is_same_device(struct ipr_resource_entry *res,
1114 struct ipr_config_table_entry_wrapper *cfgtew)
1115{
1116 if (res->ioa_cfg->sis64) {
1117 if (!memcmp(&res->dev_id, &cfgtew->u.cfgte64->dev_id,
1118 sizeof(cfgtew->u.cfgte64->dev_id)) &&
1119 !memcmp(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1120 sizeof(cfgtew->u.cfgte64->lun))) {
1121 return 1;
1122 }
1123 } else {
1124 if (res->bus == cfgtew->u.cfgte->res_addr.bus &&
1125 res->target == cfgtew->u.cfgte->res_addr.target &&
1126 res->lun == cfgtew->u.cfgte->res_addr.lun)
1127 return 1;
1128 }
1129
1130 return 0;
1131}
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141static char *ipr_format_res_path(u8 *res_path, char *buffer, int len)
1142{
1143 int i;
1144 char *p = buffer;
1145
1146 *p = '\0';
1147 p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
1148 for (i = 1; res_path[i] != 0xff && ((i * 3) < len); i++)
1149 p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
1150
1151 return buffer;
1152}
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162static void ipr_update_res_entry(struct ipr_resource_entry *res,
1163 struct ipr_config_table_entry_wrapper *cfgtew)
1164{
1165 char buffer[IPR_MAX_RES_PATH_LENGTH];
1166 unsigned int proto;
1167 int new_path = 0;
1168
1169 if (res->ioa_cfg->sis64) {
1170 res->flags = cfgtew->u.cfgte64->flags;
1171 res->res_flags = cfgtew->u.cfgte64->res_flags;
1172 res->type = cfgtew->u.cfgte64->res_type;
1173
1174 memcpy(&res->std_inq_data, &cfgtew->u.cfgte64->std_inq_data,
1175 sizeof(struct ipr_std_inq_data));
1176
1177 res->qmodel = IPR_QUEUEING_MODEL64(res);
1178 proto = cfgtew->u.cfgte64->proto;
1179 res->res_handle = cfgtew->u.cfgte64->res_handle;
1180 res->dev_id = cfgtew->u.cfgte64->dev_id;
1181
1182 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1183 sizeof(res->dev_lun.scsi_lun));
1184
1185 if (memcmp(res->res_path, &cfgtew->u.cfgte64->res_path,
1186 sizeof(res->res_path))) {
1187 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1188 sizeof(res->res_path));
1189 new_path = 1;
1190 }
1191
1192 if (res->sdev && new_path)
1193 sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
1194 ipr_format_res_path(res->res_path, buffer,
1195 sizeof(buffer)));
1196 } else {
1197 res->flags = cfgtew->u.cfgte->flags;
1198 if (res->flags & IPR_IS_IOA_RESOURCE)
1199 res->type = IPR_RES_TYPE_IOAFP;
1200 else
1201 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1202
1203 memcpy(&res->std_inq_data, &cfgtew->u.cfgte->std_inq_data,
1204 sizeof(struct ipr_std_inq_data));
1205
1206 res->qmodel = IPR_QUEUEING_MODEL(res);
1207 proto = cfgtew->u.cfgte->proto;
1208 res->res_handle = cfgtew->u.cfgte->res_handle;
1209 }
1210
1211 ipr_update_ata_class(res, proto);
1212}
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223static void ipr_clear_res_target(struct ipr_resource_entry *res)
1224{
1225 struct ipr_resource_entry *gscsi_res = NULL;
1226 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1227
1228 if (!ioa_cfg->sis64)
1229 return;
1230
1231 if (res->bus == IPR_ARRAY_VIRTUAL_BUS)
1232 clear_bit(res->target, ioa_cfg->array_ids);
1233 else if (res->bus == IPR_VSET_VIRTUAL_BUS)
1234 clear_bit(res->target, ioa_cfg->vset_ids);
1235 else if (res->bus == 0 && res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1236 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue)
1237 if (gscsi_res->dev_id == res->dev_id && gscsi_res != res)
1238 return;
1239 clear_bit(res->target, ioa_cfg->target_ids);
1240
1241 } else if (res->bus == 0)
1242 clear_bit(res->target, ioa_cfg->target_ids);
1243}
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg,
1254 struct ipr_hostrcb *hostrcb)
1255{
1256 struct ipr_resource_entry *res = NULL;
1257 struct ipr_config_table_entry_wrapper cfgtew;
1258 __be32 cc_res_handle;
1259
1260 u32 is_ndn = 1;
1261
1262 if (ioa_cfg->sis64) {
1263 cfgtew.u.cfgte64 = &hostrcb->hcam.u.ccn.u.cfgte64;
1264 cc_res_handle = cfgtew.u.cfgte64->res_handle;
1265 } else {
1266 cfgtew.u.cfgte = &hostrcb->hcam.u.ccn.u.cfgte;
1267 cc_res_handle = cfgtew.u.cfgte->res_handle;
1268 }
1269
1270 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
1271 if (res->res_handle == cc_res_handle) {
1272 is_ndn = 0;
1273 break;
1274 }
1275 }
1276
1277 if (is_ndn) {
1278 if (list_empty(&ioa_cfg->free_res_q)) {
1279 ipr_send_hcam(ioa_cfg,
1280 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
1281 hostrcb);
1282 return;
1283 }
1284
1285 res = list_entry(ioa_cfg->free_res_q.next,
1286 struct ipr_resource_entry, queue);
1287
1288 list_del(&res->queue);
1289 ipr_init_res_entry(res, &cfgtew);
1290 list_add_tail(&res->queue, &ioa_cfg->used_res_q);
1291 }
1292
1293 ipr_update_res_entry(res, &cfgtew);
1294
1295 if (hostrcb->hcam.notify_type == IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY) {
1296 if (res->sdev) {
1297 res->del_from_ml = 1;
1298 res->res_handle = IPR_INVALID_RES_HANDLE;
1299 if (ioa_cfg->allow_ml_add_del)
1300 schedule_work(&ioa_cfg->work_q);
1301 } else {
1302 ipr_clear_res_target(res);
1303 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
1304 }
1305 } else if (!res->sdev || res->del_from_ml) {
1306 res->add_to_ml = 1;
1307 if (ioa_cfg->allow_ml_add_del)
1308 schedule_work(&ioa_cfg->work_q);
1309 }
1310
1311 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1312}
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd)
1325{
1326 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1327 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
1328 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
1329
1330 list_del(&hostrcb->queue);
1331 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
1332
1333 if (ioasc) {
1334 if (ioasc != IPR_IOASC_IOA_WAS_RESET)
1335 dev_err(&ioa_cfg->pdev->dev,
1336 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
1337
1338 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1339 } else {
1340 ipr_handle_config_change(ioa_cfg, hostrcb);
1341 }
1342}
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355static int strip_and_pad_whitespace(int i, char *buf)
1356{
1357 while (i && buf[i] == ' ')
1358 i--;
1359 buf[i+1] = ' ';
1360 buf[i+2] = '\0';
1361 return i + 2;
1362}
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1374 struct ipr_vpd *vpd)
1375{
1376 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3];
1377 int i = 0;
1378
1379 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1380 i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer);
1381
1382 memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN);
1383 i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer);
1384
1385 memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN);
1386 buffer[IPR_SERIAL_NUM_LEN + i] = '\0';
1387
1388 ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer);
1389}
1390
1391
1392
1393
1394
1395
1396
1397
1398static void ipr_log_vpd(struct ipr_vpd *vpd)
1399{
1400 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN
1401 + IPR_SERIAL_NUM_LEN];
1402
1403 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1404 memcpy(buffer + IPR_VENDOR_ID_LEN, vpd->vpids.product_id,
1405 IPR_PROD_ID_LEN);
1406 buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN] = '\0';
1407 ipr_err("Vendor/Product ID: %s\n", buffer);
1408
1409 memcpy(buffer, vpd->sn, IPR_SERIAL_NUM_LEN);
1410 buffer[IPR_SERIAL_NUM_LEN] = '\0';
1411 ipr_err(" Serial Number: %s\n", buffer);
1412}
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423static void ipr_log_ext_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1424 struct ipr_ext_vpd *vpd)
1425{
1426 ipr_log_vpd_compact(prefix, hostrcb, &vpd->vpd);
1427 ipr_hcam_err(hostrcb, "%s WWN: %08X%08X\n", prefix,
1428 be32_to_cpu(vpd->wwid[0]), be32_to_cpu(vpd->wwid[1]));
1429}
1430
1431
1432
1433
1434
1435
1436
1437
1438static void ipr_log_ext_vpd(struct ipr_ext_vpd *vpd)
1439{
1440 ipr_log_vpd(&vpd->vpd);
1441 ipr_err(" WWN: %08X%08X\n", be32_to_cpu(vpd->wwid[0]),
1442 be32_to_cpu(vpd->wwid[1]));
1443}
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453static void ipr_log_enhanced_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1454 struct ipr_hostrcb *hostrcb)
1455{
1456 struct ipr_hostrcb_type_12_error *error;
1457
1458 if (ioa_cfg->sis64)
1459 error = &hostrcb->hcam.u.error64.u.type_12_error;
1460 else
1461 error = &hostrcb->hcam.u.error.u.type_12_error;
1462
1463 ipr_err("-----Current Configuration-----\n");
1464 ipr_err("Cache Directory Card Information:\n");
1465 ipr_log_ext_vpd(&error->ioa_vpd);
1466 ipr_err("Adapter Card Information:\n");
1467 ipr_log_ext_vpd(&error->cfc_vpd);
1468
1469 ipr_err("-----Expected Configuration-----\n");
1470 ipr_err("Cache Directory Card Information:\n");
1471 ipr_log_ext_vpd(&error->ioa_last_attached_to_cfc_vpd);
1472 ipr_err("Adapter Card Information:\n");
1473 ipr_log_ext_vpd(&error->cfc_last_attached_to_ioa_vpd);
1474
1475 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1476 be32_to_cpu(error->ioa_data[0]),
1477 be32_to_cpu(error->ioa_data[1]),
1478 be32_to_cpu(error->ioa_data[2]));
1479}
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489static void ipr_log_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1490 struct ipr_hostrcb *hostrcb)
1491{
1492 struct ipr_hostrcb_type_02_error *error =
1493 &hostrcb->hcam.u.error.u.type_02_error;
1494
1495 ipr_err("-----Current Configuration-----\n");
1496 ipr_err("Cache Directory Card Information:\n");
1497 ipr_log_vpd(&error->ioa_vpd);
1498 ipr_err("Adapter Card Information:\n");
1499 ipr_log_vpd(&error->cfc_vpd);
1500
1501 ipr_err("-----Expected Configuration-----\n");
1502 ipr_err("Cache Directory Card Information:\n");
1503 ipr_log_vpd(&error->ioa_last_attached_to_cfc_vpd);
1504 ipr_err("Adapter Card Information:\n");
1505 ipr_log_vpd(&error->cfc_last_attached_to_ioa_vpd);
1506
1507 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1508 be32_to_cpu(error->ioa_data[0]),
1509 be32_to_cpu(error->ioa_data[1]),
1510 be32_to_cpu(error->ioa_data[2]));
1511}
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521static void ipr_log_enhanced_config_error(struct ipr_ioa_cfg *ioa_cfg,
1522 struct ipr_hostrcb *hostrcb)
1523{
1524 int errors_logged, i;
1525 struct ipr_hostrcb_device_data_entry_enhanced *dev_entry;
1526 struct ipr_hostrcb_type_13_error *error;
1527
1528 error = &hostrcb->hcam.u.error.u.type_13_error;
1529 errors_logged = be32_to_cpu(error->errors_logged);
1530
1531 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1532 be32_to_cpu(error->errors_detected), errors_logged);
1533
1534 dev_entry = error->dev;
1535
1536 for (i = 0; i < errors_logged; i++, dev_entry++) {
1537 ipr_err_separator;
1538
1539 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1540 ipr_log_ext_vpd(&dev_entry->vpd);
1541
1542 ipr_err("-----New Device Information-----\n");
1543 ipr_log_ext_vpd(&dev_entry->new_vpd);
1544
1545 ipr_err("Cache Directory Card Information:\n");
1546 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1547
1548 ipr_err("Adapter Card Information:\n");
1549 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1550 }
1551}
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg,
1562 struct ipr_hostrcb *hostrcb)
1563{
1564 int errors_logged, i;
1565 struct ipr_hostrcb64_device_data_entry_enhanced *dev_entry;
1566 struct ipr_hostrcb_type_23_error *error;
1567 char buffer[IPR_MAX_RES_PATH_LENGTH];
1568
1569 error = &hostrcb->hcam.u.error64.u.type_23_error;
1570 errors_logged = be32_to_cpu(error->errors_logged);
1571
1572 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1573 be32_to_cpu(error->errors_detected), errors_logged);
1574
1575 dev_entry = error->dev;
1576
1577 for (i = 0; i < errors_logged; i++, dev_entry++) {
1578 ipr_err_separator;
1579
1580 ipr_err("Device %d : %s", i + 1,
1581 ipr_format_res_path(dev_entry->res_path, buffer,
1582 sizeof(buffer)));
1583 ipr_log_ext_vpd(&dev_entry->vpd);
1584
1585 ipr_err("-----New Device Information-----\n");
1586 ipr_log_ext_vpd(&dev_entry->new_vpd);
1587
1588 ipr_err("Cache Directory Card Information:\n");
1589 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1590
1591 ipr_err("Adapter Card Information:\n");
1592 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1593 }
1594}
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604static void ipr_log_config_error(struct ipr_ioa_cfg *ioa_cfg,
1605 struct ipr_hostrcb *hostrcb)
1606{
1607 int errors_logged, i;
1608 struct ipr_hostrcb_device_data_entry *dev_entry;
1609 struct ipr_hostrcb_type_03_error *error;
1610
1611 error = &hostrcb->hcam.u.error.u.type_03_error;
1612 errors_logged = be32_to_cpu(error->errors_logged);
1613
1614 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1615 be32_to_cpu(error->errors_detected), errors_logged);
1616
1617 dev_entry = error->dev;
1618
1619 for (i = 0; i < errors_logged; i++, dev_entry++) {
1620 ipr_err_separator;
1621
1622 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1623 ipr_log_vpd(&dev_entry->vpd);
1624
1625 ipr_err("-----New Device Information-----\n");
1626 ipr_log_vpd(&dev_entry->new_vpd);
1627
1628 ipr_err("Cache Directory Card Information:\n");
1629 ipr_log_vpd(&dev_entry->ioa_last_with_dev_vpd);
1630
1631 ipr_err("Adapter Card Information:\n");
1632 ipr_log_vpd(&dev_entry->cfc_last_with_dev_vpd);
1633
1634 ipr_err("Additional IOA Data: %08X %08X %08X %08X %08X\n",
1635 be32_to_cpu(dev_entry->ioa_data[0]),
1636 be32_to_cpu(dev_entry->ioa_data[1]),
1637 be32_to_cpu(dev_entry->ioa_data[2]),
1638 be32_to_cpu(dev_entry->ioa_data[3]),
1639 be32_to_cpu(dev_entry->ioa_data[4]));
1640 }
1641}
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651static void ipr_log_enhanced_array_error(struct ipr_ioa_cfg *ioa_cfg,
1652 struct ipr_hostrcb *hostrcb)
1653{
1654 int i, num_entries;
1655 struct ipr_hostrcb_type_14_error *error;
1656 struct ipr_hostrcb_array_data_entry_enhanced *array_entry;
1657 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1658
1659 error = &hostrcb->hcam.u.error.u.type_14_error;
1660
1661 ipr_err_separator;
1662
1663 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1664 error->protection_level,
1665 ioa_cfg->host->host_no,
1666 error->last_func_vset_res_addr.bus,
1667 error->last_func_vset_res_addr.target,
1668 error->last_func_vset_res_addr.lun);
1669
1670 ipr_err_separator;
1671
1672 array_entry = error->array_member;
1673 num_entries = min_t(u32, be32_to_cpu(error->num_entries),
1674 ARRAY_SIZE(error->array_member));
1675
1676 for (i = 0; i < num_entries; i++, array_entry++) {
1677 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1678 continue;
1679
1680 if (be32_to_cpu(error->exposed_mode_adn) == i)
1681 ipr_err("Exposed Array Member %d:\n", i);
1682 else
1683 ipr_err("Array Member %d:\n", i);
1684
1685 ipr_log_ext_vpd(&array_entry->vpd);
1686 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1687 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1688 "Expected Location");
1689
1690 ipr_err_separator;
1691 }
1692}
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702static void ipr_log_array_error(struct ipr_ioa_cfg *ioa_cfg,
1703 struct ipr_hostrcb *hostrcb)
1704{
1705 int i;
1706 struct ipr_hostrcb_type_04_error *error;
1707 struct ipr_hostrcb_array_data_entry *array_entry;
1708 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1709
1710 error = &hostrcb->hcam.u.error.u.type_04_error;
1711
1712 ipr_err_separator;
1713
1714 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1715 error->protection_level,
1716 ioa_cfg->host->host_no,
1717 error->last_func_vset_res_addr.bus,
1718 error->last_func_vset_res_addr.target,
1719 error->last_func_vset_res_addr.lun);
1720
1721 ipr_err_separator;
1722
1723 array_entry = error->array_member;
1724
1725 for (i = 0; i < 18; i++) {
1726 if (!memcmp(array_entry->vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1727 continue;
1728
1729 if (be32_to_cpu(error->exposed_mode_adn) == i)
1730 ipr_err("Exposed Array Member %d:\n", i);
1731 else
1732 ipr_err("Array Member %d:\n", i);
1733
1734 ipr_log_vpd(&array_entry->vpd);
1735
1736 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1737 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1738 "Expected Location");
1739
1740 ipr_err_separator;
1741
1742 if (i == 9)
1743 array_entry = error->array_member2;
1744 else
1745 array_entry++;
1746 }
1747}
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758static void ipr_log_hex_data(struct ipr_ioa_cfg *ioa_cfg, u32 *data, int len)
1759{
1760 int i;
1761
1762 if (len == 0)
1763 return;
1764
1765 if (ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
1766 len = min_t(int, len, IPR_DEFAULT_MAX_ERROR_DUMP);
1767
1768 for (i = 0; i < len / 4; i += 4) {
1769 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
1770 be32_to_cpu(data[i]),
1771 be32_to_cpu(data[i+1]),
1772 be32_to_cpu(data[i+2]),
1773 be32_to_cpu(data[i+3]));
1774 }
1775}
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785static void ipr_log_enhanced_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1786 struct ipr_hostrcb *hostrcb)
1787{
1788 struct ipr_hostrcb_type_17_error *error;
1789
1790 if (ioa_cfg->sis64)
1791 error = &hostrcb->hcam.u.error64.u.type_17_error;
1792 else
1793 error = &hostrcb->hcam.u.error.u.type_17_error;
1794
1795 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1796 strim(error->failure_reason);
1797
1798 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1799 be32_to_cpu(hostrcb->hcam.u.error.prc));
1800 ipr_log_ext_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1801 ipr_log_hex_data(ioa_cfg, error->data,
1802 be32_to_cpu(hostrcb->hcam.length) -
1803 (offsetof(struct ipr_hostrcb_error, u) +
1804 offsetof(struct ipr_hostrcb_type_17_error, data)));
1805}
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815static void ipr_log_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1816 struct ipr_hostrcb *hostrcb)
1817{
1818 struct ipr_hostrcb_type_07_error *error;
1819
1820 error = &hostrcb->hcam.u.error.u.type_07_error;
1821 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1822 strim(error->failure_reason);
1823
1824 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1825 be32_to_cpu(hostrcb->hcam.u.error.prc));
1826 ipr_log_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1827 ipr_log_hex_data(ioa_cfg, error->data,
1828 be32_to_cpu(hostrcb->hcam.length) -
1829 (offsetof(struct ipr_hostrcb_error, u) +
1830 offsetof(struct ipr_hostrcb_type_07_error, data)));
1831}
1832
1833static const struct {
1834 u8 active;
1835 char *desc;
1836} path_active_desc[] = {
1837 { IPR_PATH_NO_INFO, "Path" },
1838 { IPR_PATH_ACTIVE, "Active path" },
1839 { IPR_PATH_NOT_ACTIVE, "Inactive path" }
1840};
1841
1842static const struct {
1843 u8 state;
1844 char *desc;
1845} path_state_desc[] = {
1846 { IPR_PATH_STATE_NO_INFO, "has no path state information available" },
1847 { IPR_PATH_HEALTHY, "is healthy" },
1848 { IPR_PATH_DEGRADED, "is degraded" },
1849 { IPR_PATH_FAILED, "is failed" }
1850};
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860static void ipr_log_fabric_path(struct ipr_hostrcb *hostrcb,
1861 struct ipr_hostrcb_fabric_desc *fabric)
1862{
1863 int i, j;
1864 u8 path_state = fabric->path_state;
1865 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
1866 u8 state = path_state & IPR_PATH_STATE_MASK;
1867
1868 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
1869 if (path_active_desc[i].active != active)
1870 continue;
1871
1872 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
1873 if (path_state_desc[j].state != state)
1874 continue;
1875
1876 if (fabric->cascaded_expander == 0xff && fabric->phy == 0xff) {
1877 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d\n",
1878 path_active_desc[i].desc, path_state_desc[j].desc,
1879 fabric->ioa_port);
1880 } else if (fabric->cascaded_expander == 0xff) {
1881 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Phy=%d\n",
1882 path_active_desc[i].desc, path_state_desc[j].desc,
1883 fabric->ioa_port, fabric->phy);
1884 } else if (fabric->phy == 0xff) {
1885 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d\n",
1886 path_active_desc[i].desc, path_state_desc[j].desc,
1887 fabric->ioa_port, fabric->cascaded_expander);
1888 } else {
1889 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d, Phy=%d\n",
1890 path_active_desc[i].desc, path_state_desc[j].desc,
1891 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
1892 }
1893 return;
1894 }
1895 }
1896
1897 ipr_err("Path state=%02X IOA Port=%d Cascade=%d Phy=%d\n", path_state,
1898 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
1899}
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb,
1910 struct ipr_hostrcb64_fabric_desc *fabric)
1911{
1912 int i, j;
1913 u8 path_state = fabric->path_state;
1914 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
1915 u8 state = path_state & IPR_PATH_STATE_MASK;
1916 char buffer[IPR_MAX_RES_PATH_LENGTH];
1917
1918 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
1919 if (path_active_desc[i].active != active)
1920 continue;
1921
1922 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
1923 if (path_state_desc[j].state != state)
1924 continue;
1925
1926 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
1927 path_active_desc[i].desc, path_state_desc[j].desc,
1928 ipr_format_res_path(fabric->res_path, buffer,
1929 sizeof(buffer)));
1930 return;
1931 }
1932 }
1933
1934 ipr_err("Path state=%02X Resource Path=%s\n", path_state,
1935 ipr_format_res_path(fabric->res_path, buffer, sizeof(buffer)));
1936}
1937
1938static const struct {
1939 u8 type;
1940 char *desc;
1941} path_type_desc[] = {
1942 { IPR_PATH_CFG_IOA_PORT, "IOA port" },
1943 { IPR_PATH_CFG_EXP_PORT, "Expander port" },
1944 { IPR_PATH_CFG_DEVICE_PORT, "Device port" },
1945 { IPR_PATH_CFG_DEVICE_LUN, "Device LUN" }
1946};
1947
1948static const struct {
1949 u8 status;
1950 char *desc;
1951} path_status_desc[] = {
1952 { IPR_PATH_CFG_NO_PROB, "Functional" },
1953 { IPR_PATH_CFG_DEGRADED, "Degraded" },
1954 { IPR_PATH_CFG_FAILED, "Failed" },
1955 { IPR_PATH_CFG_SUSPECT, "Suspect" },
1956 { IPR_PATH_NOT_DETECTED, "Missing" },
1957 { IPR_PATH_INCORRECT_CONN, "Incorrectly connected" }
1958};
1959
1960static const char *link_rate[] = {
1961 "unknown",
1962 "disabled",
1963 "phy reset problem",
1964 "spinup hold",
1965 "port selector",
1966 "unknown",
1967 "unknown",
1968 "unknown",
1969 "1.5Gbps",
1970 "3.0Gbps",
1971 "unknown",
1972 "unknown",
1973 "unknown",
1974 "unknown",
1975 "unknown",
1976 "unknown"
1977};
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987static void ipr_log_path_elem(struct ipr_hostrcb *hostrcb,
1988 struct ipr_hostrcb_config_element *cfg)
1989{
1990 int i, j;
1991 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
1992 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
1993
1994 if (type == IPR_PATH_CFG_NOT_EXIST)
1995 return;
1996
1997 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
1998 if (path_type_desc[i].type != type)
1999 continue;
2000
2001 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2002 if (path_status_desc[j].status != status)
2003 continue;
2004
2005 if (type == IPR_PATH_CFG_IOA_PORT) {
2006 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, WWN=%08X%08X\n",
2007 path_status_desc[j].desc, path_type_desc[i].desc,
2008 cfg->phy, link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2009 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2010 } else {
2011 if (cfg->cascaded_expander == 0xff && cfg->phy == 0xff) {
2012 ipr_hcam_err(hostrcb, "%s %s: Link rate=%s, WWN=%08X%08X\n",
2013 path_status_desc[j].desc, path_type_desc[i].desc,
2014 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2015 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2016 } else if (cfg->cascaded_expander == 0xff) {
2017 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, "
2018 "WWN=%08X%08X\n", path_status_desc[j].desc,
2019 path_type_desc[i].desc, cfg->phy,
2020 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2021 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2022 } else if (cfg->phy == 0xff) {
2023 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Link rate=%s, "
2024 "WWN=%08X%08X\n", path_status_desc[j].desc,
2025 path_type_desc[i].desc, cfg->cascaded_expander,
2026 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2027 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2028 } else {
2029 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Phy=%d, Link rate=%s "
2030 "WWN=%08X%08X\n", path_status_desc[j].desc,
2031 path_type_desc[i].desc, cfg->cascaded_expander, cfg->phy,
2032 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2033 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2034 }
2035 }
2036 return;
2037 }
2038 }
2039
2040 ipr_hcam_err(hostrcb, "Path element=%02X: Cascade=%d Phy=%d Link rate=%s "
2041 "WWN=%08X%08X\n", cfg->type_status, cfg->cascaded_expander, cfg->phy,
2042 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2043 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2044}
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
2055 struct ipr_hostrcb64_config_element *cfg)
2056{
2057 int i, j;
2058 u8 desc_id = cfg->descriptor_id & IPR_DESCRIPTOR_MASK;
2059 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2060 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2061 char buffer[IPR_MAX_RES_PATH_LENGTH];
2062
2063 if (type == IPR_PATH_CFG_NOT_EXIST || desc_id != IPR_DESCRIPTOR_SIS64)
2064 return;
2065
2066 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2067 if (path_type_desc[i].type != type)
2068 continue;
2069
2070 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2071 if (path_status_desc[j].status != status)
2072 continue;
2073
2074 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
2075 path_status_desc[j].desc, path_type_desc[i].desc,
2076 ipr_format_res_path(cfg->res_path, buffer,
2077 sizeof(buffer)),
2078 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2079 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2080 return;
2081 }
2082 }
2083 ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
2084 "WWN=%08X%08X\n", cfg->type_status,
2085 ipr_format_res_path(cfg->res_path, buffer, sizeof(buffer)),
2086 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2087 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2088}
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098static void ipr_log_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2099 struct ipr_hostrcb *hostrcb)
2100{
2101 struct ipr_hostrcb_type_20_error *error;
2102 struct ipr_hostrcb_fabric_desc *fabric;
2103 struct ipr_hostrcb_config_element *cfg;
2104 int i, add_len;
2105
2106 error = &hostrcb->hcam.u.error.u.type_20_error;
2107 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2108 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2109
2110 add_len = be32_to_cpu(hostrcb->hcam.length) -
2111 (offsetof(struct ipr_hostrcb_error, u) +
2112 offsetof(struct ipr_hostrcb_type_20_error, desc));
2113
2114 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2115 ipr_log_fabric_path(hostrcb, fabric);
2116 for_each_fabric_cfg(fabric, cfg)
2117 ipr_log_path_elem(hostrcb, cfg);
2118
2119 add_len -= be16_to_cpu(fabric->length);
2120 fabric = (struct ipr_hostrcb_fabric_desc *)
2121 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2122 }
2123
2124 ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len);
2125}
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
2136 struct ipr_hostrcb *hostrcb)
2137{
2138 int i, num_entries;
2139 struct ipr_hostrcb_type_24_error *error;
2140 struct ipr_hostrcb64_array_data_entry *array_entry;
2141 char buffer[IPR_MAX_RES_PATH_LENGTH];
2142 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
2143
2144 error = &hostrcb->hcam.u.error64.u.type_24_error;
2145
2146 ipr_err_separator;
2147
2148 ipr_err("RAID %s Array Configuration: %s\n",
2149 error->protection_level,
2150 ipr_format_res_path(error->last_res_path, buffer, sizeof(buffer)));
2151
2152 ipr_err_separator;
2153
2154 array_entry = error->array_member;
2155 num_entries = min_t(u32, error->num_entries,
2156 ARRAY_SIZE(error->array_member));
2157
2158 for (i = 0; i < num_entries; i++, array_entry++) {
2159
2160 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
2161 continue;
2162
2163 if (error->exposed_mode_adn == i)
2164 ipr_err("Exposed Array Member %d:\n", i);
2165 else
2166 ipr_err("Array Member %d:\n", i);
2167
2168 ipr_err("Array Member %d:\n", i);
2169 ipr_log_ext_vpd(&array_entry->vpd);
2170 ipr_err("Current Location: %s\n",
2171 ipr_format_res_path(array_entry->res_path, buffer,
2172 sizeof(buffer)));
2173 ipr_err("Expected Location: %s\n",
2174 ipr_format_res_path(array_entry->expected_res_path,
2175 buffer, sizeof(buffer)));
2176
2177 ipr_err_separator;
2178 }
2179}
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189static void ipr_log_sis64_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2190 struct ipr_hostrcb *hostrcb)
2191{
2192 struct ipr_hostrcb_type_30_error *error;
2193 struct ipr_hostrcb64_fabric_desc *fabric;
2194 struct ipr_hostrcb64_config_element *cfg;
2195 int i, add_len;
2196
2197 error = &hostrcb->hcam.u.error64.u.type_30_error;
2198
2199 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2200 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2201
2202 add_len = be32_to_cpu(hostrcb->hcam.length) -
2203 (offsetof(struct ipr_hostrcb64_error, u) +
2204 offsetof(struct ipr_hostrcb_type_30_error, desc));
2205
2206 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2207 ipr_log64_fabric_path(hostrcb, fabric);
2208 for_each_fabric_cfg(fabric, cfg)
2209 ipr_log64_path_elem(hostrcb, cfg);
2210
2211 add_len -= be16_to_cpu(fabric->length);
2212 fabric = (struct ipr_hostrcb64_fabric_desc *)
2213 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2214 }
2215
2216 ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len);
2217}
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227static void ipr_log_generic_error(struct ipr_ioa_cfg *ioa_cfg,
2228 struct ipr_hostrcb *hostrcb)
2229{
2230 ipr_log_hex_data(ioa_cfg, hostrcb->hcam.u.raw.data,
2231 be32_to_cpu(hostrcb->hcam.length));
2232}
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245static u32 ipr_get_error(u32 ioasc)
2246{
2247 int i;
2248
2249 for (i = 0; i < ARRAY_SIZE(ipr_error_table); i++)
2250 if (ipr_error_table[i].ioasc == (ioasc & IPR_IOASC_IOASC_MASK))
2251 return i;
2252
2253 return 0;
2254}
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg,
2267 struct ipr_hostrcb *hostrcb)
2268{
2269 u32 ioasc;
2270 int error_index;
2271
2272 if (hostrcb->hcam.notify_type != IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY)
2273 return;
2274
2275 if (hostrcb->hcam.notifications_lost == IPR_HOST_RCB_NOTIFICATIONS_LOST)
2276 dev_err(&ioa_cfg->pdev->dev, "Error notifications lost\n");
2277
2278 if (ioa_cfg->sis64)
2279 ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2280 else
2281 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2282
2283 if (!ioa_cfg->sis64 && (ioasc == IPR_IOASC_BUS_WAS_RESET ||
2284 ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER)) {
2285
2286 scsi_report_bus_reset(ioa_cfg->host,
2287 hostrcb->hcam.u.error.fd_res_addr.bus);
2288 }
2289
2290 error_index = ipr_get_error(ioasc);
2291
2292 if (!ipr_error_table[error_index].log_hcam)
2293 return;
2294
2295 ipr_hcam_err(hostrcb, "%s\n", ipr_error_table[error_index].error);
2296
2297
2298 ioa_cfg->errors_logged++;
2299
2300 if (ioa_cfg->log_level < ipr_error_table[error_index].log_hcam)
2301 return;
2302 if (be32_to_cpu(hostrcb->hcam.length) > sizeof(hostrcb->hcam.u.raw))
2303 hostrcb->hcam.length = cpu_to_be32(sizeof(hostrcb->hcam.u.raw));
2304
2305 switch (hostrcb->hcam.overlay_id) {
2306 case IPR_HOST_RCB_OVERLAY_ID_2:
2307 ipr_log_cache_error(ioa_cfg, hostrcb);
2308 break;
2309 case IPR_HOST_RCB_OVERLAY_ID_3:
2310 ipr_log_config_error(ioa_cfg, hostrcb);
2311 break;
2312 case IPR_HOST_RCB_OVERLAY_ID_4:
2313 case IPR_HOST_RCB_OVERLAY_ID_6:
2314 ipr_log_array_error(ioa_cfg, hostrcb);
2315 break;
2316 case IPR_HOST_RCB_OVERLAY_ID_7:
2317 ipr_log_dual_ioa_error(ioa_cfg, hostrcb);
2318 break;
2319 case IPR_HOST_RCB_OVERLAY_ID_12:
2320 ipr_log_enhanced_cache_error(ioa_cfg, hostrcb);
2321 break;
2322 case IPR_HOST_RCB_OVERLAY_ID_13:
2323 ipr_log_enhanced_config_error(ioa_cfg, hostrcb);
2324 break;
2325 case IPR_HOST_RCB_OVERLAY_ID_14:
2326 case IPR_HOST_RCB_OVERLAY_ID_16:
2327 ipr_log_enhanced_array_error(ioa_cfg, hostrcb);
2328 break;
2329 case IPR_HOST_RCB_OVERLAY_ID_17:
2330 ipr_log_enhanced_dual_ioa_error(ioa_cfg, hostrcb);
2331 break;
2332 case IPR_HOST_RCB_OVERLAY_ID_20:
2333 ipr_log_fabric_error(ioa_cfg, hostrcb);
2334 break;
2335 case IPR_HOST_RCB_OVERLAY_ID_23:
2336 ipr_log_sis64_config_error(ioa_cfg, hostrcb);
2337 break;
2338 case IPR_HOST_RCB_OVERLAY_ID_24:
2339 case IPR_HOST_RCB_OVERLAY_ID_26:
2340 ipr_log_sis64_array_error(ioa_cfg, hostrcb);
2341 break;
2342 case IPR_HOST_RCB_OVERLAY_ID_30:
2343 ipr_log_sis64_fabric_error(ioa_cfg, hostrcb);
2344 break;
2345 case IPR_HOST_RCB_OVERLAY_ID_1:
2346 case IPR_HOST_RCB_OVERLAY_ID_DEFAULT:
2347 default:
2348 ipr_log_generic_error(ioa_cfg, hostrcb);
2349 break;
2350 }
2351}
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2365{
2366 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2367 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
2368 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
2369 u32 fd_ioasc;
2370
2371 if (ioa_cfg->sis64)
2372 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2373 else
2374 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2375
2376 list_del(&hostrcb->queue);
2377 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
2378
2379 if (!ioasc) {
2380 ipr_handle_log_data(ioa_cfg, hostrcb);
2381 if (fd_ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED)
2382 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
2383 } else if (ioasc != IPR_IOASC_IOA_WAS_RESET) {
2384 dev_err(&ioa_cfg->pdev->dev,
2385 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
2386 }
2387
2388 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
2389}
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401static void ipr_timeout(struct ipr_cmnd *ipr_cmd)
2402{
2403 unsigned long lock_flags = 0;
2404 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2405
2406 ENTER;
2407 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2408
2409 ioa_cfg->errors_logged++;
2410 dev_err(&ioa_cfg->pdev->dev,
2411 "Adapter being reset due to command timeout.\n");
2412
2413 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2414 ioa_cfg->sdt_state = GET_DUMP;
2415
2416 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd)
2417 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2418
2419 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2420 LEAVE;
2421}
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433static void ipr_oper_timeout(struct ipr_cmnd *ipr_cmd)
2434{
2435 unsigned long lock_flags = 0;
2436 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2437
2438 ENTER;
2439 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2440
2441 ioa_cfg->errors_logged++;
2442 dev_err(&ioa_cfg->pdev->dev,
2443 "Adapter timed out transitioning to operational.\n");
2444
2445 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2446 ioa_cfg->sdt_state = GET_DUMP;
2447
2448 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd) {
2449 if (ipr_fastfail)
2450 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
2451 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2452 }
2453
2454 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2455 LEAVE;
2456}
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468static int ipr_reset_reload(struct ipr_ioa_cfg *ioa_cfg,
2469 enum ipr_shutdown_type shutdown_type)
2470{
2471 if (!ioa_cfg->in_reset_reload)
2472 ipr_initiate_ioa_reset(ioa_cfg, shutdown_type);
2473
2474 spin_unlock_irq(ioa_cfg->host->host_lock);
2475 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
2476 spin_lock_irq(ioa_cfg->host->host_lock);
2477
2478
2479
2480 if (ioa_cfg->ioa_is_dead) {
2481 ipr_trace;
2482 return FAILED;
2483 }
2484
2485 return SUCCESS;
2486}
2487
2488
2489
2490
2491
2492
2493
2494
2495static const struct ipr_ses_table_entry *
2496ipr_find_ses_entry(struct ipr_resource_entry *res)
2497{
2498 int i, j, matches;
2499 struct ipr_std_inq_vpids *vpids;
2500 const struct ipr_ses_table_entry *ste = ipr_ses_table;
2501
2502 for (i = 0; i < ARRAY_SIZE(ipr_ses_table); i++, ste++) {
2503 for (j = 0, matches = 0; j < IPR_PROD_ID_LEN; j++) {
2504 if (ste->compare_product_id_byte[j] == 'X') {
2505 vpids = &res->std_inq_data.vpids;
2506 if (vpids->product_id[j] == ste->product_id[j])
2507 matches++;
2508 else
2509 break;
2510 } else
2511 matches++;
2512 }
2513
2514 if (matches == IPR_PROD_ID_LEN)
2515 return ste;
2516 }
2517
2518 return NULL;
2519}
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533static u32 ipr_get_max_scsi_speed(struct ipr_ioa_cfg *ioa_cfg, u8 bus, u8 bus_width)
2534{
2535 struct ipr_resource_entry *res;
2536 const struct ipr_ses_table_entry *ste;
2537 u32 max_xfer_rate = IPR_MAX_SCSI_RATE(bus_width);
2538
2539
2540 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
2541 if (!(IPR_IS_SES_DEVICE(res->std_inq_data)))
2542 continue;
2543
2544 if (bus != res->bus)
2545 continue;
2546
2547 if (!(ste = ipr_find_ses_entry(res)))
2548 continue;
2549
2550 max_xfer_rate = (ste->max_bus_speed_limit * 10) / (bus_width / 8);
2551 }
2552
2553 return max_xfer_rate;
2554}
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566static int ipr_wait_iodbg_ack(struct ipr_ioa_cfg *ioa_cfg, int max_delay)
2567{
2568 volatile u32 pcii_reg;
2569 int delay = 1;
2570
2571
2572 while (delay < max_delay) {
2573 pcii_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
2574
2575 if (pcii_reg & IPR_PCII_IO_DEBUG_ACKNOWLEDGE)
2576 return 0;
2577
2578
2579 if ((delay / 1000) > MAX_UDELAY_MS)
2580 mdelay(delay / 1000);
2581 else
2582 udelay(delay);
2583
2584 delay += delay;
2585 }
2586 return -EIO;
2587}
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599static int ipr_get_sis64_dump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2600 u32 start_addr,
2601 __be32 *dest, u32 length_in_words)
2602{
2603 int i;
2604
2605 for (i = 0; i < length_in_words; i++) {
2606 writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg);
2607 *dest = cpu_to_be32(readl(ioa_cfg->regs.dump_data_reg));
2608 dest++;
2609 }
2610
2611 return 0;
2612}
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2625 u32 start_addr,
2626 __be32 *dest, u32 length_in_words)
2627{
2628 volatile u32 temp_pcii_reg;
2629 int i, delay = 0;
2630
2631 if (ioa_cfg->sis64)
2632 return ipr_get_sis64_dump_data_section(ioa_cfg, start_addr,
2633 dest, length_in_words);
2634
2635
2636 writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
2637 ioa_cfg->regs.set_uproc_interrupt_reg32);
2638
2639
2640 if (ipr_wait_iodbg_ack(ioa_cfg,
2641 IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC)) {
2642 dev_err(&ioa_cfg->pdev->dev,
2643 "IOA dump long data transfer timeout\n");
2644 return -EIO;
2645 }
2646
2647
2648 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2649 ioa_cfg->regs.clr_interrupt_reg);
2650
2651
2652 writel(start_addr, ioa_cfg->ioa_mailbox);
2653
2654
2655 writel(IPR_UPROCI_RESET_ALERT,
2656 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2657
2658 for (i = 0; i < length_in_words; i++) {
2659
2660 if (ipr_wait_iodbg_ack(ioa_cfg,
2661 IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC)) {
2662 dev_err(&ioa_cfg->pdev->dev,
2663 "IOA dump short data transfer timeout\n");
2664 return -EIO;
2665 }
2666
2667
2668 *dest = cpu_to_be32(readl(ioa_cfg->ioa_mailbox));
2669 dest++;
2670
2671
2672 if (i < (length_in_words - 1)) {
2673
2674 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2675 ioa_cfg->regs.clr_interrupt_reg);
2676 }
2677 }
2678
2679
2680 writel(IPR_UPROCI_RESET_ALERT,
2681 ioa_cfg->regs.set_uproc_interrupt_reg32);
2682
2683 writel(IPR_UPROCI_IO_DEBUG_ALERT,
2684 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2685
2686
2687 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2688 ioa_cfg->regs.clr_interrupt_reg);
2689
2690
2691 while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) {
2692 temp_pcii_reg =
2693 readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
2694
2695 if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT))
2696 return 0;
2697
2698 udelay(10);
2699 delay += 10;
2700 }
2701
2702 return 0;
2703}
2704
2705#ifdef CONFIG_SCSI_IPR_DUMP
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717static int ipr_sdt_copy(struct ipr_ioa_cfg *ioa_cfg,
2718 unsigned long pci_address, u32 length)
2719{
2720 int bytes_copied = 0;
2721 int cur_len, rc, rem_len, rem_page_len, max_dump_size;
2722 __be32 *page;
2723 unsigned long lock_flags = 0;
2724 struct ipr_ioa_dump *ioa_dump = &ioa_cfg->dump->ioa_dump;
2725
2726 if (ioa_cfg->sis64)
2727 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
2728 else
2729 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
2730
2731 while (bytes_copied < length &&
2732 (ioa_dump->hdr.len + bytes_copied) < max_dump_size) {
2733 if (ioa_dump->page_offset >= PAGE_SIZE ||
2734 ioa_dump->page_offset == 0) {
2735 page = (__be32 *)__get_free_page(GFP_ATOMIC);
2736
2737 if (!page) {
2738 ipr_trace;
2739 return bytes_copied;
2740 }
2741
2742 ioa_dump->page_offset = 0;
2743 ioa_dump->ioa_data[ioa_dump->next_page_index] = page;
2744 ioa_dump->next_page_index++;
2745 } else
2746 page = ioa_dump->ioa_data[ioa_dump->next_page_index - 1];
2747
2748 rem_len = length - bytes_copied;
2749 rem_page_len = PAGE_SIZE - ioa_dump->page_offset;
2750 cur_len = min(rem_len, rem_page_len);
2751
2752 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2753 if (ioa_cfg->sdt_state == ABORT_DUMP) {
2754 rc = -EIO;
2755 } else {
2756 rc = ipr_get_ldump_data_section(ioa_cfg,
2757 pci_address + bytes_copied,
2758 &page[ioa_dump->page_offset / 4],
2759 (cur_len / sizeof(u32)));
2760 }
2761 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2762
2763 if (!rc) {
2764 ioa_dump->page_offset += cur_len;
2765 bytes_copied += cur_len;
2766 } else {
2767 ipr_trace;
2768 break;
2769 }
2770 schedule();
2771 }
2772
2773 return bytes_copied;
2774}
2775
2776
2777
2778
2779
2780
2781
2782
2783static void ipr_init_dump_entry_hdr(struct ipr_dump_entry_header *hdr)
2784{
2785 hdr->eye_catcher = IPR_DUMP_EYE_CATCHER;
2786 hdr->num_elems = 1;
2787 hdr->offset = sizeof(*hdr);
2788 hdr->status = IPR_DUMP_STATUS_SUCCESS;
2789}
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799static void ipr_dump_ioa_type_data(struct ipr_ioa_cfg *ioa_cfg,
2800 struct ipr_driver_dump *driver_dump)
2801{
2802 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
2803
2804 ipr_init_dump_entry_hdr(&driver_dump->ioa_type_entry.hdr);
2805 driver_dump->ioa_type_entry.hdr.len =
2806 sizeof(struct ipr_dump_ioa_type_entry) -
2807 sizeof(struct ipr_dump_entry_header);
2808 driver_dump->ioa_type_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2809 driver_dump->ioa_type_entry.hdr.id = IPR_DUMP_DRIVER_TYPE_ID;
2810 driver_dump->ioa_type_entry.type = ioa_cfg->type;
2811 driver_dump->ioa_type_entry.fw_version = (ucode_vpd->major_release << 24) |
2812 (ucode_vpd->card_type << 16) | (ucode_vpd->minor_release[0] << 8) |
2813 ucode_vpd->minor_release[1];
2814 driver_dump->hdr.num_entries++;
2815}
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825static void ipr_dump_version_data(struct ipr_ioa_cfg *ioa_cfg,
2826 struct ipr_driver_dump *driver_dump)
2827{
2828 ipr_init_dump_entry_hdr(&driver_dump->version_entry.hdr);
2829 driver_dump->version_entry.hdr.len =
2830 sizeof(struct ipr_dump_version_entry) -
2831 sizeof(struct ipr_dump_entry_header);
2832 driver_dump->version_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
2833 driver_dump->version_entry.hdr.id = IPR_DUMP_DRIVER_VERSION_ID;
2834 strcpy(driver_dump->version_entry.version, IPR_DRIVER_VERSION);
2835 driver_dump->hdr.num_entries++;
2836}
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846static void ipr_dump_trace_data(struct ipr_ioa_cfg *ioa_cfg,
2847 struct ipr_driver_dump *driver_dump)
2848{
2849 ipr_init_dump_entry_hdr(&driver_dump->trace_entry.hdr);
2850 driver_dump->trace_entry.hdr.len =
2851 sizeof(struct ipr_dump_trace_entry) -
2852 sizeof(struct ipr_dump_entry_header);
2853 driver_dump->trace_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2854 driver_dump->trace_entry.hdr.id = IPR_DUMP_TRACE_ID;
2855 memcpy(driver_dump->trace_entry.trace, ioa_cfg->trace, IPR_TRACE_SIZE);
2856 driver_dump->hdr.num_entries++;
2857}
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867static void ipr_dump_location_data(struct ipr_ioa_cfg *ioa_cfg,
2868 struct ipr_driver_dump *driver_dump)
2869{
2870 ipr_init_dump_entry_hdr(&driver_dump->location_entry.hdr);
2871 driver_dump->location_entry.hdr.len =
2872 sizeof(struct ipr_dump_location_entry) -
2873 sizeof(struct ipr_dump_entry_header);
2874 driver_dump->location_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
2875 driver_dump->location_entry.hdr.id = IPR_DUMP_LOCATION_ID;
2876 strcpy(driver_dump->location_entry.location, dev_name(&ioa_cfg->pdev->dev));
2877 driver_dump->hdr.num_entries++;
2878}
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump)
2889{
2890 unsigned long start_addr, sdt_word;
2891 unsigned long lock_flags = 0;
2892 struct ipr_driver_dump *driver_dump = &dump->driver_dump;
2893 struct ipr_ioa_dump *ioa_dump = &dump->ioa_dump;
2894 u32 num_entries, max_num_entries, start_off, end_off;
2895 u32 max_dump_size, bytes_to_copy, bytes_copied, rc;
2896 struct ipr_sdt *sdt;
2897 int valid = 1;
2898 int i;
2899
2900 ENTER;
2901
2902 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2903
2904 if (ioa_cfg->sdt_state != GET_DUMP) {
2905 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2906 return;
2907 }
2908
2909 if (ioa_cfg->sis64) {
2910 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2911 ssleep(IPR_DUMP_DELAY_SECONDS);
2912 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2913 }
2914
2915 start_addr = readl(ioa_cfg->ioa_mailbox);
2916
2917 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(start_addr)) {
2918 dev_err(&ioa_cfg->pdev->dev,
2919 "Invalid dump table format: %lx\n", start_addr);
2920 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2921 return;
2922 }
2923
2924 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA initiated\n");
2925
2926 driver_dump->hdr.eye_catcher = IPR_DUMP_EYE_CATCHER;
2927
2928
2929 driver_dump->hdr.len = sizeof(struct ipr_driver_dump);
2930 driver_dump->hdr.num_entries = 1;
2931 driver_dump->hdr.first_entry_offset = sizeof(struct ipr_dump_header);
2932 driver_dump->hdr.status = IPR_DUMP_STATUS_SUCCESS;
2933 driver_dump->hdr.os = IPR_DUMP_OS_LINUX;
2934 driver_dump->hdr.driver_name = IPR_DUMP_DRIVER_NAME;
2935
2936 ipr_dump_version_data(ioa_cfg, driver_dump);
2937 ipr_dump_location_data(ioa_cfg, driver_dump);
2938 ipr_dump_ioa_type_data(ioa_cfg, driver_dump);
2939 ipr_dump_trace_data(ioa_cfg, driver_dump);
2940
2941
2942 driver_dump->hdr.len += sizeof(struct ipr_dump_entry_header);
2943
2944
2945 ipr_init_dump_entry_hdr(&ioa_dump->hdr);
2946 ioa_dump->hdr.len = 0;
2947 ioa_dump->hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2948 ioa_dump->hdr.id = IPR_DUMP_IOA_DUMP_ID;
2949
2950
2951
2952
2953
2954 sdt = &ioa_dump->sdt;
2955
2956 if (ioa_cfg->sis64) {
2957 max_num_entries = IPR_FMT3_NUM_SDT_ENTRIES;
2958 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
2959 } else {
2960 max_num_entries = IPR_FMT2_NUM_SDT_ENTRIES;
2961 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
2962 }
2963
2964 bytes_to_copy = offsetof(struct ipr_sdt, entry) +
2965 (max_num_entries * sizeof(struct ipr_sdt_entry));
2966 rc = ipr_get_ldump_data_section(ioa_cfg, start_addr, (__be32 *)sdt,
2967 bytes_to_copy / sizeof(__be32));
2968
2969
2970 if (rc || ((be32_to_cpu(sdt->hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
2971 (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
2972 dev_err(&ioa_cfg->pdev->dev,
2973 "Dump of IOA failed. Dump table not valid: %d, %X.\n",
2974 rc, be32_to_cpu(sdt->hdr.state));
2975 driver_dump->hdr.status = IPR_DUMP_STATUS_FAILED;
2976 ioa_cfg->sdt_state = DUMP_OBTAINED;
2977 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2978 return;
2979 }
2980
2981 num_entries = be32_to_cpu(sdt->hdr.num_entries_used);
2982
2983 if (num_entries > max_num_entries)
2984 num_entries = max_num_entries;
2985
2986
2987 dump->driver_dump.hdr.len += sizeof(struct ipr_sdt_header);
2988 if (ioa_cfg->sis64)
2989 dump->driver_dump.hdr.len += num_entries * sizeof(struct ipr_sdt_entry);
2990 else
2991 dump->driver_dump.hdr.len += max_num_entries * sizeof(struct ipr_sdt_entry);
2992
2993 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2994
2995 for (i = 0; i < num_entries; i++) {
2996 if (ioa_dump->hdr.len > max_dump_size) {
2997 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
2998 break;
2999 }
3000
3001 if (sdt->entry[i].flags & IPR_SDT_VALID_ENTRY) {
3002 sdt_word = be32_to_cpu(sdt->entry[i].start_token);
3003 if (ioa_cfg->sis64)
3004 bytes_to_copy = be32_to_cpu(sdt->entry[i].end_token);
3005 else {
3006 start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK;
3007 end_off = be32_to_cpu(sdt->entry[i].end_token);
3008
3009 if (ipr_sdt_is_fmt2(sdt_word) && sdt_word)
3010 bytes_to_copy = end_off - start_off;
3011 else
3012 valid = 0;
3013 }
3014 if (valid) {
3015 if (bytes_to_copy > max_dump_size) {
3016 sdt->entry[i].flags &= ~IPR_SDT_VALID_ENTRY;
3017 continue;
3018 }
3019
3020
3021 bytes_copied = ipr_sdt_copy(ioa_cfg, sdt_word,
3022 bytes_to_copy);
3023
3024 ioa_dump->hdr.len += bytes_copied;
3025
3026 if (bytes_copied != bytes_to_copy) {
3027 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3028 break;
3029 }
3030 }
3031 }
3032 }
3033
3034 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA completed.\n");
3035
3036
3037 driver_dump->hdr.len += ioa_dump->hdr.len;
3038 wmb();
3039 ioa_cfg->sdt_state = DUMP_OBTAINED;
3040 LEAVE;
3041}
3042
3043#else
3044#define ipr_get_ioa_dump(ioa_cfg, dump) do { } while(0)
3045#endif
3046
3047
3048
3049
3050
3051
3052
3053
3054static void ipr_release_dump(struct kref *kref)
3055{
3056 struct ipr_dump *dump = container_of(kref,struct ipr_dump,kref);
3057 struct ipr_ioa_cfg *ioa_cfg = dump->ioa_cfg;
3058 unsigned long lock_flags = 0;
3059 int i;
3060
3061 ENTER;
3062 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3063 ioa_cfg->dump = NULL;
3064 ioa_cfg->sdt_state = INACTIVE;
3065 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3066
3067 for (i = 0; i < dump->ioa_dump.next_page_index; i++)
3068 free_page((unsigned long) dump->ioa_dump.ioa_data[i]);
3069
3070 vfree(dump->ioa_dump.ioa_data);
3071 kfree(dump);
3072 LEAVE;
3073}
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086static void ipr_worker_thread(struct work_struct *work)
3087{
3088 unsigned long lock_flags;
3089 struct ipr_resource_entry *res;
3090 struct scsi_device *sdev;
3091 struct ipr_dump *dump;
3092 struct ipr_ioa_cfg *ioa_cfg =
3093 container_of(work, struct ipr_ioa_cfg, work_q);
3094 u8 bus, target, lun;
3095 int did_work;
3096
3097 ENTER;
3098 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3099
3100 if (ioa_cfg->sdt_state == GET_DUMP) {
3101 dump = ioa_cfg->dump;
3102 if (!dump) {
3103 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3104 return;
3105 }
3106 kref_get(&dump->kref);
3107 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3108 ipr_get_ioa_dump(ioa_cfg, dump);
3109 kref_put(&dump->kref, ipr_release_dump);
3110
3111 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3112 if (ioa_cfg->sdt_state == DUMP_OBTAINED)
3113 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3114 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3115 return;
3116 }
3117
3118restart:
3119 do {
3120 did_work = 0;
3121 if (!ioa_cfg->allow_cmds || !ioa_cfg->allow_ml_add_del) {
3122 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3123 return;
3124 }
3125
3126 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3127 if (res->del_from_ml && res->sdev) {
3128 did_work = 1;
3129 sdev = res->sdev;
3130 if (!scsi_device_get(sdev)) {
3131 if (!res->add_to_ml)
3132 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
3133 else
3134 res->del_from_ml = 0;
3135 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3136 scsi_remove_device(sdev);
3137 scsi_device_put(sdev);
3138 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3139 }
3140 break;
3141 }
3142 }
3143 } while(did_work);
3144
3145 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3146 if (res->add_to_ml) {
3147 bus = res->bus;
3148 target = res->target;
3149 lun = res->lun;
3150 res->add_to_ml = 0;
3151 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3152 scsi_add_device(ioa_cfg->host, bus, target, lun);
3153 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3154 goto restart;
3155 }
3156 }
3157
3158 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3159 kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
3160 LEAVE;
3161}
3162
3163#ifdef CONFIG_SCSI_IPR_TRACE
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176static ssize_t ipr_read_trace(struct file *filp, struct kobject *kobj,
3177 struct bin_attribute *bin_attr,
3178 char *buf, loff_t off, size_t count)
3179{
3180 struct device *dev = container_of(kobj, struct device, kobj);
3181 struct Scsi_Host *shost = class_to_shost(dev);
3182 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3183 unsigned long lock_flags = 0;
3184 ssize_t ret;
3185
3186 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3187 ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace,
3188 IPR_TRACE_SIZE);
3189 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3190
3191 return ret;
3192}
3193
3194static struct bin_attribute ipr_trace_attr = {
3195 .attr = {
3196 .name = "trace",
3197 .mode = S_IRUGO,
3198 },
3199 .size = 0,
3200 .read = ipr_read_trace,
3201};
3202#endif
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212static ssize_t ipr_show_fw_version(struct device *dev,
3213 struct device_attribute *attr, char *buf)
3214{
3215 struct Scsi_Host *shost = class_to_shost(dev);
3216 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3217 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3218 unsigned long lock_flags = 0;
3219 int len;
3220
3221 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3222 len = snprintf(buf, PAGE_SIZE, "%02X%02X%02X%02X\n",
3223 ucode_vpd->major_release, ucode_vpd->card_type,
3224 ucode_vpd->minor_release[0],
3225 ucode_vpd->minor_release[1]);
3226 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3227 return len;
3228}
3229
3230static struct device_attribute ipr_fw_version_attr = {
3231 .attr = {
3232 .name = "fw_version",
3233 .mode = S_IRUGO,
3234 },
3235 .show = ipr_show_fw_version,
3236};
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246static ssize_t ipr_show_log_level(struct device *dev,
3247 struct device_attribute *attr, char *buf)
3248{
3249 struct Scsi_Host *shost = class_to_shost(dev);
3250 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3251 unsigned long lock_flags = 0;
3252 int len;
3253
3254 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3255 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->log_level);
3256 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3257 return len;
3258}
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268static ssize_t ipr_store_log_level(struct device *dev,
3269 struct device_attribute *attr,
3270 const char *buf, size_t count)
3271{
3272 struct Scsi_Host *shost = class_to_shost(dev);
3273 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3274 unsigned long lock_flags = 0;
3275
3276 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3277 ioa_cfg->log_level = simple_strtoul(buf, NULL, 10);
3278 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3279 return strlen(buf);
3280}
3281
3282static struct device_attribute ipr_log_level_attr = {
3283 .attr = {
3284 .name = "log_level",
3285 .mode = S_IRUGO | S_IWUSR,
3286 },
3287 .show = ipr_show_log_level,
3288 .store = ipr_store_log_level
3289};
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303static ssize_t ipr_store_diagnostics(struct device *dev,
3304 struct device_attribute *attr,
3305 const char *buf, size_t count)
3306{
3307 struct Scsi_Host *shost = class_to_shost(dev);
3308 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3309 unsigned long lock_flags = 0;
3310 int rc = count;
3311
3312 if (!capable(CAP_SYS_ADMIN))
3313 return -EACCES;
3314
3315 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3316 while(ioa_cfg->in_reset_reload) {
3317 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3318 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3319 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3320 }
3321
3322 ioa_cfg->errors_logged = 0;
3323 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3324
3325 if (ioa_cfg->in_reset_reload) {
3326 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3327 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3328
3329
3330 msleep(1000);
3331 } else {
3332 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3333 return -EIO;
3334 }
3335
3336 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3337 if (ioa_cfg->in_reset_reload || ioa_cfg->errors_logged)
3338 rc = -EIO;
3339 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3340
3341 return rc;
3342}
3343
3344static struct device_attribute ipr_diagnostics_attr = {
3345 .attr = {
3346 .name = "run_diagnostics",
3347 .mode = S_IWUSR,
3348 },
3349 .store = ipr_store_diagnostics
3350};
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360static ssize_t ipr_show_adapter_state(struct device *dev,
3361 struct device_attribute *attr, char *buf)
3362{
3363 struct Scsi_Host *shost = class_to_shost(dev);
3364 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3365 unsigned long lock_flags = 0;
3366 int len;
3367
3368 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3369 if (ioa_cfg->ioa_is_dead)
3370 len = snprintf(buf, PAGE_SIZE, "offline\n");
3371 else
3372 len = snprintf(buf, PAGE_SIZE, "online\n");
3373 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3374 return len;
3375}
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388static ssize_t ipr_store_adapter_state(struct device *dev,
3389 struct device_attribute *attr,
3390 const char *buf, size_t count)
3391{
3392 struct Scsi_Host *shost = class_to_shost(dev);
3393 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3394 unsigned long lock_flags;
3395 int result = count;
3396
3397 if (!capable(CAP_SYS_ADMIN))
3398 return -EACCES;
3399
3400 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3401 if (ioa_cfg->ioa_is_dead && !strncmp(buf, "online", 6)) {
3402 ioa_cfg->ioa_is_dead = 0;
3403 ioa_cfg->reset_retries = 0;
3404 ioa_cfg->in_ioa_bringdown = 0;
3405 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3406 }
3407 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3408 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3409
3410 return result;
3411}
3412
3413static struct device_attribute ipr_ioa_state_attr = {
3414 .attr = {
3415 .name = "online_state",
3416 .mode = S_IRUGO | S_IWUSR,
3417 },
3418 .show = ipr_show_adapter_state,
3419 .store = ipr_store_adapter_state
3420};
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433static ssize_t ipr_store_reset_adapter(struct device *dev,
3434 struct device_attribute *attr,
3435 const char *buf, size_t count)
3436{
3437 struct Scsi_Host *shost = class_to_shost(dev);
3438 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3439 unsigned long lock_flags;
3440 int result = count;
3441
3442 if (!capable(CAP_SYS_ADMIN))
3443 return -EACCES;
3444
3445 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3446 if (!ioa_cfg->in_reset_reload)
3447 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3448 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3449 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3450
3451 return result;
3452}
3453
3454static struct device_attribute ipr_ioa_reset_attr = {
3455 .attr = {
3456 .name = "reset_host",
3457 .mode = S_IWUSR,
3458 },
3459 .store = ipr_store_reset_adapter
3460};
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472static struct ipr_sglist *ipr_alloc_ucode_buffer(int buf_len)
3473{
3474 int sg_size, order, bsize_elem, num_elem, i, j;
3475 struct ipr_sglist *sglist;
3476 struct scatterlist *scatterlist;
3477 struct page *page;
3478
3479
3480 sg_size = buf_len / (IPR_MAX_SGLIST - 1);
3481
3482
3483 order = get_order(sg_size);
3484
3485
3486 bsize_elem = PAGE_SIZE * (1 << order);
3487
3488
3489 if (buf_len % bsize_elem)
3490 num_elem = (buf_len / bsize_elem) + 1;
3491 else
3492 num_elem = buf_len / bsize_elem;
3493
3494
3495 sglist = kzalloc(sizeof(struct ipr_sglist) +
3496 (sizeof(struct scatterlist) * (num_elem - 1)),
3497 GFP_KERNEL);
3498
3499 if (sglist == NULL) {
3500 ipr_trace;
3501 return NULL;
3502 }
3503
3504 scatterlist = sglist->scatterlist;
3505 sg_init_table(scatterlist, num_elem);
3506
3507 sglist->order = order;
3508 sglist->num_sg = num_elem;
3509
3510
3511 for (i = 0; i < num_elem; i++) {
3512 page = alloc_pages(GFP_KERNEL, order);
3513 if (!page) {
3514 ipr_trace;
3515
3516
3517 for (j = i - 1; j >= 0; j--)
3518 __free_pages(sg_page(&scatterlist[j]), order);
3519 kfree(sglist);
3520 return NULL;
3521 }
3522
3523 sg_set_page(&scatterlist[i], page, 0, 0);
3524 }
3525
3526 return sglist;
3527}
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539static void ipr_free_ucode_buffer(struct ipr_sglist *sglist)
3540{
3541 int i;
3542
3543 for (i = 0; i < sglist->num_sg; i++)
3544 __free_pages(sg_page(&sglist->scatterlist[i]), sglist->order);
3545
3546 kfree(sglist);
3547}
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561static int ipr_copy_ucode_buffer(struct ipr_sglist *sglist,
3562 u8 *buffer, u32 len)
3563{
3564 int bsize_elem, i, result = 0;
3565 struct scatterlist *scatterlist;
3566 void *kaddr;
3567
3568
3569 bsize_elem = PAGE_SIZE * (1 << sglist->order);
3570
3571 scatterlist = sglist->scatterlist;
3572
3573 for (i = 0; i < (len / bsize_elem); i++, buffer += bsize_elem) {
3574 struct page *page = sg_page(&scatterlist[i]);
3575
3576 kaddr = kmap(page);
3577 memcpy(kaddr, buffer, bsize_elem);
3578 kunmap(page);
3579
3580 scatterlist[i].length = bsize_elem;
3581
3582 if (result != 0) {
3583 ipr_trace;
3584 return result;
3585 }
3586 }
3587
3588 if (len % bsize_elem) {
3589 struct page *page = sg_page(&scatterlist[i]);
3590
3591 kaddr = kmap(page);
3592 memcpy(kaddr, buffer, len % bsize_elem);
3593 kunmap(page);
3594
3595 scatterlist[i].length = len % bsize_elem;
3596 }
3597
3598 sglist->buffer_len = len;
3599 return result;
3600}
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610static void ipr_build_ucode_ioadl64(struct ipr_cmnd *ipr_cmd,
3611 struct ipr_sglist *sglist)
3612{
3613 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3614 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
3615 struct scatterlist *scatterlist = sglist->scatterlist;
3616 int i;
3617
3618 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3619 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3620 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3621
3622 ioarcb->ioadl_len =
3623 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
3624 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3625 ioadl64[i].flags = cpu_to_be32(IPR_IOADL_FLAGS_WRITE);
3626 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(&scatterlist[i]));
3627 ioadl64[i].address = cpu_to_be64(sg_dma_address(&scatterlist[i]));
3628 }
3629
3630 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3631}
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641static void ipr_build_ucode_ioadl(struct ipr_cmnd *ipr_cmd,
3642 struct ipr_sglist *sglist)
3643{
3644 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3645 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
3646 struct scatterlist *scatterlist = sglist->scatterlist;
3647 int i;
3648
3649 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3650 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3651 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3652
3653 ioarcb->ioadl_len =
3654 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
3655
3656 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3657 ioadl[i].flags_and_data_len =
3658 cpu_to_be32(IPR_IOADL_FLAGS_WRITE | sg_dma_len(&scatterlist[i]));
3659 ioadl[i].address =
3660 cpu_to_be32(sg_dma_address(&scatterlist[i]));
3661 }
3662
3663 ioadl[i-1].flags_and_data_len |=
3664 cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3665}
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677static int ipr_update_ioa_ucode(struct ipr_ioa_cfg *ioa_cfg,
3678 struct ipr_sglist *sglist)
3679{
3680 unsigned long lock_flags;
3681
3682 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3683 while(ioa_cfg->in_reset_reload) {
3684 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3685 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3686 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3687 }
3688
3689 if (ioa_cfg->ucode_sglist) {
3690 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3691 dev_err(&ioa_cfg->pdev->dev,
3692 "Microcode download already in progress\n");
3693 return -EIO;
3694 }
3695
3696 sglist->num_dma_sg = pci_map_sg(ioa_cfg->pdev, sglist->scatterlist,
3697 sglist->num_sg, DMA_TO_DEVICE);
3698
3699 if (!sglist->num_dma_sg) {
3700 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3701 dev_err(&ioa_cfg->pdev->dev,
3702 "Failed to map microcode download buffer!\n");
3703 return -EIO;
3704 }
3705
3706 ioa_cfg->ucode_sglist = sglist;
3707 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3708 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3709 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3710
3711 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3712 ioa_cfg->ucode_sglist = NULL;
3713 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3714 return 0;
3715}
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728static ssize_t ipr_store_update_fw(struct device *dev,
3729 struct device_attribute *attr,
3730 const char *buf, size_t count)
3731{
3732 struct Scsi_Host *shost = class_to_shost(dev);
3733 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3734 struct ipr_ucode_image_header *image_hdr;
3735 const struct firmware *fw_entry;
3736 struct ipr_sglist *sglist;
3737 char fname[100];
3738 char *src;
3739 int len, result, dnld_size;
3740
3741 if (!capable(CAP_SYS_ADMIN))
3742 return -EACCES;
3743
3744 len = snprintf(fname, 99, "%s", buf);
3745 fname[len-1] = '\0';
3746
3747 if(request_firmware(&fw_entry, fname, &ioa_cfg->pdev->dev)) {
3748 dev_err(&ioa_cfg->pdev->dev, "Firmware file %s not found\n", fname);
3749 return -EIO;
3750 }
3751
3752 image_hdr = (struct ipr_ucode_image_header *)fw_entry->data;
3753
3754 if (be32_to_cpu(image_hdr->header_length) > fw_entry->size ||
3755 (ioa_cfg->vpd_cbs->page3_data.card_type &&
3756 ioa_cfg->vpd_cbs->page3_data.card_type != image_hdr->card_type)) {
3757 dev_err(&ioa_cfg->pdev->dev, "Invalid microcode buffer\n");
3758 release_firmware(fw_entry);
3759 return -EINVAL;
3760 }
3761
3762 src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length);
3763 dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length);
3764 sglist = ipr_alloc_ucode_buffer(dnld_size);
3765
3766 if (!sglist) {
3767 dev_err(&ioa_cfg->pdev->dev, "Microcode buffer allocation failed\n");
3768 release_firmware(fw_entry);
3769 return -ENOMEM;
3770 }
3771
3772 result = ipr_copy_ucode_buffer(sglist, src, dnld_size);
3773
3774 if (result) {
3775 dev_err(&ioa_cfg->pdev->dev,
3776 "Microcode buffer copy to DMA buffer failed\n");
3777 goto out;
3778 }
3779
3780 result = ipr_update_ioa_ucode(ioa_cfg, sglist);
3781
3782 if (!result)
3783 result = count;
3784out:
3785 ipr_free_ucode_buffer(sglist);
3786 release_firmware(fw_entry);
3787 return result;
3788}
3789
3790static struct device_attribute ipr_update_fw_attr = {
3791 .attr = {
3792 .name = "update_fw",
3793 .mode = S_IWUSR,
3794 },
3795 .store = ipr_store_update_fw
3796};
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806static ssize_t ipr_show_fw_type(struct device *dev,
3807 struct device_attribute *attr, char *buf)
3808{
3809 struct Scsi_Host *shost = class_to_shost(dev);
3810 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3811 unsigned long lock_flags = 0;
3812 int len;
3813
3814 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3815 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->sis64);
3816 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3817 return len;
3818}
3819
3820static struct device_attribute ipr_ioa_fw_type_attr = {
3821 .attr = {
3822 .name = "fw_type",
3823 .mode = S_IRUGO,
3824 },
3825 .show = ipr_show_fw_type
3826};
3827
3828static struct device_attribute *ipr_ioa_attrs[] = {
3829 &ipr_fw_version_attr,
3830 &ipr_log_level_attr,
3831 &ipr_diagnostics_attr,
3832 &ipr_ioa_state_attr,
3833 &ipr_ioa_reset_attr,
3834 &ipr_update_fw_attr,
3835 &ipr_ioa_fw_type_attr,
3836 NULL,
3837};
3838
3839#ifdef CONFIG_SCSI_IPR_DUMP
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852static ssize_t ipr_read_dump(struct file *filp, struct kobject *kobj,
3853 struct bin_attribute *bin_attr,
3854 char *buf, loff_t off, size_t count)
3855{
3856 struct device *cdev = container_of(kobj, struct device, kobj);
3857 struct Scsi_Host *shost = class_to_shost(cdev);
3858 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3859 struct ipr_dump *dump;
3860 unsigned long lock_flags = 0;
3861 char *src;
3862 int len, sdt_end;
3863 size_t rc = count;
3864
3865 if (!capable(CAP_SYS_ADMIN))
3866 return -EACCES;
3867
3868 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3869 dump = ioa_cfg->dump;
3870
3871 if (ioa_cfg->sdt_state != DUMP_OBTAINED || !dump) {
3872 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3873 return 0;
3874 }
3875 kref_get(&dump->kref);
3876 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3877
3878 if (off > dump->driver_dump.hdr.len) {
3879 kref_put(&dump->kref, ipr_release_dump);
3880 return 0;
3881 }
3882
3883 if (off + count > dump->driver_dump.hdr.len) {
3884 count = dump->driver_dump.hdr.len - off;
3885 rc = count;
3886 }
3887
3888 if (count && off < sizeof(dump->driver_dump)) {
3889 if (off + count > sizeof(dump->driver_dump))
3890 len = sizeof(dump->driver_dump) - off;
3891 else
3892 len = count;
3893 src = (u8 *)&dump->driver_dump + off;
3894 memcpy(buf, src, len);
3895 buf += len;
3896 off += len;
3897 count -= len;
3898 }
3899
3900 off -= sizeof(dump->driver_dump);
3901
3902 if (ioa_cfg->sis64)
3903 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
3904 (be32_to_cpu(dump->ioa_dump.sdt.hdr.num_entries_used) *
3905 sizeof(struct ipr_sdt_entry));
3906 else
3907 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
3908 (IPR_FMT2_NUM_SDT_ENTRIES * sizeof(struct ipr_sdt_entry));
3909
3910 if (count && off < sdt_end) {
3911 if (off + count > sdt_end)
3912 len = sdt_end - off;
3913 else
3914 len = count;
3915 src = (u8 *)&dump->ioa_dump + off;
3916 memcpy(buf, src, len);
3917 buf += len;
3918 off += len;
3919 count -= len;
3920 }
3921
3922 off -= sdt_end;
3923
3924 while (count) {
3925 if ((off & PAGE_MASK) != ((off + count) & PAGE_MASK))
3926 len = PAGE_ALIGN(off) - off;
3927 else
3928 len = count;
3929 src = (u8 *)dump->ioa_dump.ioa_data[(off & PAGE_MASK) >> PAGE_SHIFT];
3930 src += off & ~PAGE_MASK;
3931 memcpy(buf, src, len);
3932 buf += len;
3933 off += len;
3934 count -= len;
3935 }
3936
3937 kref_put(&dump->kref, ipr_release_dump);
3938 return rc;
3939}
3940
3941
3942
3943
3944
3945
3946
3947
3948static int ipr_alloc_dump(struct ipr_ioa_cfg *ioa_cfg)
3949{
3950 struct ipr_dump *dump;
3951 __be32 **ioa_data;
3952 unsigned long lock_flags = 0;
3953
3954 dump = kzalloc(sizeof(struct ipr_dump), GFP_KERNEL);
3955
3956 if (!dump) {
3957 ipr_err("Dump memory allocation failed\n");
3958 return -ENOMEM;
3959 }
3960
3961 if (ioa_cfg->sis64)
3962 ioa_data = vmalloc(IPR_FMT3_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
3963 else
3964 ioa_data = vmalloc(IPR_FMT2_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
3965
3966 if (!ioa_data) {
3967 ipr_err("Dump memory allocation failed\n");
3968 kfree(dump);
3969 return -ENOMEM;
3970 }
3971
3972 dump->ioa_dump.ioa_data = ioa_data;
3973
3974 kref_init(&dump->kref);
3975 dump->ioa_cfg = ioa_cfg;
3976
3977 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3978
3979 if (INACTIVE != ioa_cfg->sdt_state) {
3980 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3981 vfree(dump->ioa_dump.ioa_data);
3982 kfree(dump);
3983 return 0;
3984 }
3985
3986 ioa_cfg->dump = dump;
3987 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
3988 if (ioa_cfg->ioa_is_dead && !ioa_cfg->dump_taken) {
3989 ioa_cfg->dump_taken = 1;
3990 schedule_work(&ioa_cfg->work_q);
3991 }
3992 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3993
3994 return 0;
3995}
3996
3997
3998
3999
4000
4001
4002
4003
4004static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg)
4005{
4006 struct ipr_dump *dump;
4007 unsigned long lock_flags = 0;
4008
4009 ENTER;
4010
4011 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4012 dump = ioa_cfg->dump;
4013 if (!dump) {
4014 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4015 return 0;
4016 }
4017
4018 ioa_cfg->dump = NULL;
4019 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4020
4021 kref_put(&dump->kref, ipr_release_dump);
4022
4023 LEAVE;
4024 return 0;
4025}
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039static ssize_t ipr_write_dump(struct file *filp, struct kobject *kobj,
4040 struct bin_attribute *bin_attr,
4041 char *buf, loff_t off, size_t count)
4042{
4043 struct device *cdev = container_of(kobj, struct device, kobj);
4044 struct Scsi_Host *shost = class_to_shost(cdev);
4045 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4046 int rc;
4047
4048 if (!capable(CAP_SYS_ADMIN))
4049 return -EACCES;
4050
4051 if (buf[0] == '1')
4052 rc = ipr_alloc_dump(ioa_cfg);
4053 else if (buf[0] == '0')
4054 rc = ipr_free_dump(ioa_cfg);
4055 else
4056 return -EINVAL;
4057
4058 if (rc)
4059 return rc;
4060 else
4061 return count;
4062}
4063
4064static struct bin_attribute ipr_dump_attr = {
4065 .attr = {
4066 .name = "dump",
4067 .mode = S_IRUSR | S_IWUSR,
4068 },
4069 .size = 0,
4070 .read = ipr_read_dump,
4071 .write = ipr_write_dump
4072};
4073#else
4074static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg) { return 0; };
4075#endif
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086static int ipr_change_queue_depth(struct scsi_device *sdev, int qdepth,
4087 int reason)
4088{
4089 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4090 struct ipr_resource_entry *res;
4091 unsigned long lock_flags = 0;
4092
4093 if (reason != SCSI_QDEPTH_DEFAULT)
4094 return -EOPNOTSUPP;
4095
4096 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4097 res = (struct ipr_resource_entry *)sdev->hostdata;
4098
4099 if (res && ipr_is_gata(res) && qdepth > IPR_MAX_CMD_PER_ATA_LUN)
4100 qdepth = IPR_MAX_CMD_PER_ATA_LUN;
4101 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4102
4103 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4104 return sdev->queue_depth;
4105}
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115static int ipr_change_queue_type(struct scsi_device *sdev, int tag_type)
4116{
4117 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4118 struct ipr_resource_entry *res;
4119 unsigned long lock_flags = 0;
4120
4121 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4122 res = (struct ipr_resource_entry *)sdev->hostdata;
4123
4124 if (res) {
4125 if (ipr_is_gscsi(res) && sdev->tagged_supported) {
4126
4127
4128
4129
4130 scsi_set_tag_type(sdev, tag_type);
4131
4132 if (tag_type)
4133 scsi_activate_tcq(sdev, sdev->queue_depth);
4134 else
4135 scsi_deactivate_tcq(sdev, sdev->queue_depth);
4136 } else
4137 tag_type = 0;
4138 } else
4139 tag_type = 0;
4140
4141 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4142 return tag_type;
4143}
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154static ssize_t ipr_show_adapter_handle(struct device *dev, struct device_attribute *attr, char *buf)
4155{
4156 struct scsi_device *sdev = to_scsi_device(dev);
4157 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4158 struct ipr_resource_entry *res;
4159 unsigned long lock_flags = 0;
4160 ssize_t len = -ENXIO;
4161
4162 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4163 res = (struct ipr_resource_entry *)sdev->hostdata;
4164 if (res)
4165 len = snprintf(buf, PAGE_SIZE, "%08X\n", res->res_handle);
4166 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4167 return len;
4168}
4169
4170static struct device_attribute ipr_adapter_handle_attr = {
4171 .attr = {
4172 .name = "adapter_handle",
4173 .mode = S_IRUSR,
4174 },
4175 .show = ipr_show_adapter_handle
4176};
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribute *attr, char *buf)
4189{
4190 struct scsi_device *sdev = to_scsi_device(dev);
4191 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4192 struct ipr_resource_entry *res;
4193 unsigned long lock_flags = 0;
4194 ssize_t len = -ENXIO;
4195 char buffer[IPR_MAX_RES_PATH_LENGTH];
4196
4197 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4198 res = (struct ipr_resource_entry *)sdev->hostdata;
4199 if (res && ioa_cfg->sis64)
4200 len = snprintf(buf, PAGE_SIZE, "%s\n",
4201 ipr_format_res_path(res->res_path, buffer,
4202 sizeof(buffer)));
4203 else if (res)
4204 len = snprintf(buf, PAGE_SIZE, "%d:%d:%d:%d\n", ioa_cfg->host->host_no,
4205 res->bus, res->target, res->lun);
4206
4207 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4208 return len;
4209}
4210
4211static struct device_attribute ipr_resource_path_attr = {
4212 .attr = {
4213 .name = "resource_path",
4214 .mode = S_IRUGO,
4215 },
4216 .show = ipr_show_resource_path
4217};
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228static ssize_t ipr_show_device_id(struct device *dev, struct device_attribute *attr, char *buf)
4229{
4230 struct scsi_device *sdev = to_scsi_device(dev);
4231 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4232 struct ipr_resource_entry *res;
4233 unsigned long lock_flags = 0;
4234 ssize_t len = -ENXIO;
4235
4236 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4237 res = (struct ipr_resource_entry *)sdev->hostdata;
4238 if (res && ioa_cfg->sis64)
4239 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->dev_id);
4240 else if (res)
4241 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->lun_wwn);
4242
4243 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4244 return len;
4245}
4246
4247static struct device_attribute ipr_device_id_attr = {
4248 .attr = {
4249 .name = "device_id",
4250 .mode = S_IRUGO,
4251 },
4252 .show = ipr_show_device_id
4253};
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264static ssize_t ipr_show_resource_type(struct device *dev, struct device_attribute *attr, char *buf)
4265{
4266 struct scsi_device *sdev = to_scsi_device(dev);
4267 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4268 struct ipr_resource_entry *res;
4269 unsigned long lock_flags = 0;
4270 ssize_t len = -ENXIO;
4271
4272 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4273 res = (struct ipr_resource_entry *)sdev->hostdata;
4274
4275 if (res)
4276 len = snprintf(buf, PAGE_SIZE, "%x\n", res->type);
4277
4278 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4279 return len;
4280}
4281
4282static struct device_attribute ipr_resource_type_attr = {
4283 .attr = {
4284 .name = "resource_type",
4285 .mode = S_IRUGO,
4286 },
4287 .show = ipr_show_resource_type
4288};
4289
4290static struct device_attribute *ipr_dev_attrs[] = {
4291 &ipr_adapter_handle_attr,
4292 &ipr_resource_path_attr,
4293 &ipr_device_id_attr,
4294 &ipr_resource_type_attr,
4295 NULL,
4296};
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312static int ipr_biosparam(struct scsi_device *sdev,
4313 struct block_device *block_device,
4314 sector_t capacity, int *parm)
4315{
4316 int heads, sectors;
4317 sector_t cylinders;
4318
4319 heads = 128;
4320 sectors = 32;
4321
4322 cylinders = capacity;
4323 sector_div(cylinders, (128 * 32));
4324
4325
4326 parm[0] = heads;
4327 parm[1] = sectors;
4328 parm[2] = cylinders;
4329
4330 return 0;
4331}
4332
4333
4334
4335
4336
4337
4338
4339
4340static struct ipr_resource_entry *ipr_find_starget(struct scsi_target *starget)
4341{
4342 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4343 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4344 struct ipr_resource_entry *res;
4345
4346 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4347 if ((res->bus == starget->channel) &&
4348 (res->target == starget->id) &&
4349 (res->lun == 0)) {
4350 return res;
4351 }
4352 }
4353
4354 return NULL;
4355}
4356
4357static struct ata_port_info sata_port_info;
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369static int ipr_target_alloc(struct scsi_target *starget)
4370{
4371 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4372 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4373 struct ipr_sata_port *sata_port;
4374 struct ata_port *ap;
4375 struct ipr_resource_entry *res;
4376 unsigned long lock_flags;
4377
4378 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4379 res = ipr_find_starget(starget);
4380 starget->hostdata = NULL;
4381
4382 if (res && ipr_is_gata(res)) {
4383 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4384 sata_port = kzalloc(sizeof(*sata_port), GFP_KERNEL);
4385 if (!sata_port)
4386 return -ENOMEM;
4387
4388 ap = ata_sas_port_alloc(&ioa_cfg->ata_host, &sata_port_info, shost);
4389 if (ap) {
4390 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4391 sata_port->ioa_cfg = ioa_cfg;
4392 sata_port->ap = ap;
4393 sata_port->res = res;
4394
4395 res->sata_port = sata_port;
4396 ap->private_data = sata_port;
4397 starget->hostdata = sata_port;
4398 } else {
4399 kfree(sata_port);
4400 return -ENOMEM;
4401 }
4402 }
4403 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4404
4405 return 0;
4406}
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416static void ipr_target_destroy(struct scsi_target *starget)
4417{
4418 struct ipr_sata_port *sata_port = starget->hostdata;
4419 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4420 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4421
4422 if (ioa_cfg->sis64) {
4423 if (starget->channel == IPR_ARRAY_VIRTUAL_BUS)
4424 clear_bit(starget->id, ioa_cfg->array_ids);
4425 else if (starget->channel == IPR_VSET_VIRTUAL_BUS)
4426 clear_bit(starget->id, ioa_cfg->vset_ids);
4427 else if (starget->channel == 0)
4428 clear_bit(starget->id, ioa_cfg->target_ids);
4429 }
4430
4431 if (sata_port) {
4432 starget->hostdata = NULL;
4433 ata_sas_port_destroy(sata_port->ap);
4434 kfree(sata_port);
4435 }
4436}
4437
4438
4439
4440
4441
4442
4443
4444
4445static struct ipr_resource_entry *ipr_find_sdev(struct scsi_device *sdev)
4446{
4447 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4448 struct ipr_resource_entry *res;
4449
4450 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4451 if ((res->bus == sdev->channel) &&
4452 (res->target == sdev->id) &&
4453 (res->lun == sdev->lun))
4454 return res;
4455 }
4456
4457 return NULL;
4458}
4459
4460
4461
4462
4463
4464
4465
4466
4467static void ipr_slave_destroy(struct scsi_device *sdev)
4468{
4469 struct ipr_resource_entry *res;
4470 struct ipr_ioa_cfg *ioa_cfg;
4471 unsigned long lock_flags = 0;
4472
4473 ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4474
4475 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4476 res = (struct ipr_resource_entry *) sdev->hostdata;
4477 if (res) {
4478 if (res->sata_port)
4479 res->sata_port->ap->link.device[0].class = ATA_DEV_NONE;
4480 sdev->hostdata = NULL;
4481 res->sdev = NULL;
4482 res->sata_port = NULL;
4483 }
4484 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4485}
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496static int ipr_slave_configure(struct scsi_device *sdev)
4497{
4498 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4499 struct ipr_resource_entry *res;
4500 struct ata_port *ap = NULL;
4501 unsigned long lock_flags = 0;
4502 char buffer[IPR_MAX_RES_PATH_LENGTH];
4503
4504 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4505 res = sdev->hostdata;
4506 if (res) {
4507 if (ipr_is_af_dasd_device(res))
4508 sdev->type = TYPE_RAID;
4509 if (ipr_is_af_dasd_device(res) || ipr_is_ioa_resource(res)) {
4510 sdev->scsi_level = 4;
4511 sdev->no_uld_attach = 1;
4512 }
4513 if (ipr_is_vset_device(res)) {
4514 blk_queue_rq_timeout(sdev->request_queue,
4515 IPR_VSET_RW_TIMEOUT);
4516 blk_queue_max_hw_sectors(sdev->request_queue, IPR_VSET_MAX_SECTORS);
4517 }
4518 if (ipr_is_gata(res) && res->sata_port)
4519 ap = res->sata_port->ap;
4520 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4521
4522 if (ap) {
4523 scsi_adjust_queue_depth(sdev, 0, IPR_MAX_CMD_PER_ATA_LUN);
4524 ata_sas_slave_configure(sdev, ap);
4525 } else
4526 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4527 if (ioa_cfg->sis64)
4528 sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
4529 ipr_format_res_path(res->res_path, buffer,
4530 sizeof(buffer)));
4531 return 0;
4532 }
4533 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4534 return 0;
4535}
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547static int ipr_ata_slave_alloc(struct scsi_device *sdev)
4548{
4549 struct ipr_sata_port *sata_port = NULL;
4550 int rc = -ENXIO;
4551
4552 ENTER;
4553 if (sdev->sdev_target)
4554 sata_port = sdev->sdev_target->hostdata;
4555 if (sata_port)
4556 rc = ata_sas_port_init(sata_port->ap);
4557 if (rc)
4558 ipr_slave_destroy(sdev);
4559
4560 LEAVE;
4561 return rc;
4562}
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576static int ipr_slave_alloc(struct scsi_device *sdev)
4577{
4578 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4579 struct ipr_resource_entry *res;
4580 unsigned long lock_flags;
4581 int rc = -ENXIO;
4582
4583 sdev->hostdata = NULL;
4584
4585 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4586
4587 res = ipr_find_sdev(sdev);
4588 if (res) {
4589 res->sdev = sdev;
4590 res->add_to_ml = 0;
4591 res->in_erp = 0;
4592 sdev->hostdata = res;
4593 if (!ipr_is_naca_model(res))
4594 res->needs_sync_complete = 1;
4595 rc = 0;
4596 if (ipr_is_gata(res)) {
4597 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4598 return ipr_ata_slave_alloc(sdev);
4599 }
4600 }
4601
4602 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4603
4604 return rc;
4605}
4606
4607
4608
4609
4610
4611
4612
4613
4614static int __ipr_eh_host_reset(struct scsi_cmnd * scsi_cmd)
4615{
4616 struct ipr_ioa_cfg *ioa_cfg;
4617 int rc;
4618
4619 ENTER;
4620 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
4621
4622 dev_err(&ioa_cfg->pdev->dev,
4623 "Adapter being reset as a result of error recovery.\n");
4624
4625 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
4626 ioa_cfg->sdt_state = GET_DUMP;
4627
4628 rc = ipr_reset_reload(ioa_cfg, IPR_SHUTDOWN_ABBREV);
4629
4630 LEAVE;
4631 return rc;
4632}
4633
4634static int ipr_eh_host_reset(struct scsi_cmnd * cmd)
4635{
4636 int rc;
4637
4638 spin_lock_irq(cmd->device->host->host_lock);
4639 rc = __ipr_eh_host_reset(cmd);
4640 spin_unlock_irq(cmd->device->host->host_lock);
4641
4642 return rc;
4643}
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg,
4660 struct ipr_resource_entry *res)
4661{
4662 struct ipr_cmnd *ipr_cmd;
4663 struct ipr_ioarcb *ioarcb;
4664 struct ipr_cmd_pkt *cmd_pkt;
4665 struct ipr_ioarcb_ata_regs *regs;
4666 u32 ioasc;
4667
4668 ENTER;
4669 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
4670 ioarcb = &ipr_cmd->ioarcb;
4671 cmd_pkt = &ioarcb->cmd_pkt;
4672
4673 if (ipr_cmd->ioa_cfg->sis64) {
4674 regs = &ipr_cmd->i.ata_ioadl.regs;
4675 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
4676 } else
4677 regs = &ioarcb->u.add_data.u.regs;
4678
4679 ioarcb->res_handle = res->res_handle;
4680 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
4681 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
4682 if (ipr_is_gata(res)) {
4683 cmd_pkt->cdb[2] = IPR_ATA_PHY_RESET;
4684 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(regs->flags));
4685 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
4686 }
4687
4688 ipr_send_blocking_cmd(ipr_cmd, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
4689 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
4690 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
4691 if (ipr_is_gata(res) && res->sata_port && ioasc != IPR_IOASC_IOA_WAS_RESET) {
4692 if (ipr_cmd->ioa_cfg->sis64)
4693 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
4694 sizeof(struct ipr_ioasa_gata));
4695 else
4696 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
4697 sizeof(struct ipr_ioasa_gata));
4698 }
4699
4700 LEAVE;
4701 return (IPR_IOASC_SENSE_KEY(ioasc) ? -EIO : 0);
4702}
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714static int ipr_sata_reset(struct ata_link *link, unsigned int *classes,
4715 unsigned long deadline)
4716{
4717 struct ipr_sata_port *sata_port = link->ap->private_data;
4718 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
4719 struct ipr_resource_entry *res;
4720 unsigned long lock_flags = 0;
4721 int rc = -ENXIO;
4722
4723 ENTER;
4724 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4725 while(ioa_cfg->in_reset_reload) {
4726 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4727 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4728 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4729 }
4730
4731 res = sata_port->res;
4732 if (res) {
4733 rc = ipr_device_reset(ioa_cfg, res);
4734 *classes = res->ata_class;
4735 }
4736
4737 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4738 LEAVE;
4739 return rc;
4740}
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753static int __ipr_eh_dev_reset(struct scsi_cmnd * scsi_cmd)
4754{
4755 struct ipr_cmnd *ipr_cmd;
4756 struct ipr_ioa_cfg *ioa_cfg;
4757 struct ipr_resource_entry *res;
4758 struct ata_port *ap;
4759 int rc = 0;
4760
4761 ENTER;
4762 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
4763 res = scsi_cmd->device->hostdata;
4764
4765 if (!res)
4766 return FAILED;
4767
4768
4769
4770
4771
4772
4773 if (ioa_cfg->in_reset_reload)
4774 return FAILED;
4775 if (ioa_cfg->ioa_is_dead)
4776 return FAILED;
4777
4778 list_for_each_entry(ipr_cmd, &ioa_cfg->pending_q, queue) {
4779 if (ipr_cmd->ioarcb.res_handle == res->res_handle) {
4780 if (ipr_cmd->scsi_cmd)
4781 ipr_cmd->done = ipr_scsi_eh_done;
4782 if (ipr_cmd->qc)
4783 ipr_cmd->done = ipr_sata_eh_done;
4784 if (ipr_cmd->qc && !(ipr_cmd->qc->flags & ATA_QCFLAG_FAILED)) {
4785 ipr_cmd->qc->err_mask |= AC_ERR_TIMEOUT;
4786 ipr_cmd->qc->flags |= ATA_QCFLAG_FAILED;
4787 }
4788 }
4789 }
4790
4791 res->resetting_device = 1;
4792 scmd_printk(KERN_ERR, scsi_cmd, "Resetting device\n");
4793
4794 if (ipr_is_gata(res) && res->sata_port) {
4795 ap = res->sata_port->ap;
4796 spin_unlock_irq(scsi_cmd->device->host->host_lock);
4797 ata_std_error_handler(ap);
4798 spin_lock_irq(scsi_cmd->device->host->host_lock);
4799
4800 list_for_each_entry(ipr_cmd, &ioa_cfg->pending_q, queue) {
4801 if (ipr_cmd->ioarcb.res_handle == res->res_handle) {
4802 rc = -EIO;
4803 break;
4804 }
4805 }
4806 } else
4807 rc = ipr_device_reset(ioa_cfg, res);
4808 res->resetting_device = 0;
4809
4810 LEAVE;
4811 return (rc ? FAILED : SUCCESS);
4812}
4813
4814static int ipr_eh_dev_reset(struct scsi_cmnd * cmd)
4815{
4816 int rc;
4817
4818 spin_lock_irq(cmd->device->host->host_lock);
4819 rc = __ipr_eh_dev_reset(cmd);
4820 spin_unlock_irq(cmd->device->host->host_lock);
4821
4822 return rc;
4823}
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834static void ipr_bus_reset_done(struct ipr_cmnd *ipr_cmd)
4835{
4836 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
4837 struct ipr_resource_entry *res;
4838
4839 ENTER;
4840 if (!ioa_cfg->sis64)
4841 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4842 if (res->res_handle == ipr_cmd->ioarcb.res_handle) {
4843 scsi_report_bus_reset(ioa_cfg->host, res->bus);
4844 break;
4845 }
4846 }
4847
4848
4849
4850
4851
4852 if (ipr_cmd->sibling->sibling)
4853 ipr_cmd->sibling->sibling = NULL;
4854 else
4855 ipr_cmd->sibling->done(ipr_cmd->sibling);
4856
4857 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
4858 LEAVE;
4859}
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872static void ipr_abort_timeout(struct ipr_cmnd *ipr_cmd)
4873{
4874 struct ipr_cmnd *reset_cmd;
4875 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
4876 struct ipr_cmd_pkt *cmd_pkt;
4877 unsigned long lock_flags = 0;
4878
4879 ENTER;
4880 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4881 if (ipr_cmd->completion.done || ioa_cfg->in_reset_reload) {
4882 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4883 return;
4884 }
4885
4886 sdev_printk(KERN_ERR, ipr_cmd->u.sdev, "Abort timed out. Resetting bus.\n");
4887 reset_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
4888 ipr_cmd->sibling = reset_cmd;
4889 reset_cmd->sibling = ipr_cmd;
4890 reset_cmd->ioarcb.res_handle = ipr_cmd->ioarcb.res_handle;
4891 cmd_pkt = &reset_cmd->ioarcb.cmd_pkt;
4892 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
4893 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
4894 cmd_pkt->cdb[2] = IPR_RESET_TYPE_SELECT | IPR_BUS_RESET;
4895
4896 ipr_do_req(reset_cmd, ipr_bus_reset_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
4897 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4898 LEAVE;
4899}
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910static int ipr_cancel_op(struct scsi_cmnd * scsi_cmd)
4911{
4912 struct ipr_cmnd *ipr_cmd;
4913 struct ipr_ioa_cfg *ioa_cfg;
4914 struct ipr_resource_entry *res;
4915 struct ipr_cmd_pkt *cmd_pkt;
4916 u32 ioasc;
4917 int op_found = 0;
4918
4919 ENTER;
4920 ioa_cfg = (struct ipr_ioa_cfg *)scsi_cmd->device->host->hostdata;
4921 res = scsi_cmd->device->hostdata;
4922
4923
4924
4925
4926
4927 if (ioa_cfg->in_reset_reload || ioa_cfg->ioa_is_dead)
4928 return FAILED;
4929 if (!res || !ipr_is_gscsi(res))
4930 return FAILED;
4931
4932 list_for_each_entry(ipr_cmd, &ioa_cfg->pending_q, queue) {
4933 if (ipr_cmd->scsi_cmd == scsi_cmd) {
4934 ipr_cmd->done = ipr_scsi_eh_done;
4935 op_found = 1;
4936 break;
4937 }
4938 }
4939
4940 if (!op_found)
4941 return SUCCESS;
4942
4943 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
4944 ipr_cmd->ioarcb.res_handle = res->res_handle;
4945 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
4946 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
4947 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
4948 ipr_cmd->u.sdev = scsi_cmd->device;
4949
4950 scmd_printk(KERN_ERR, scsi_cmd, "Aborting command: %02X\n",
4951 scsi_cmd->cmnd[0]);
4952 ipr_send_blocking_cmd(ipr_cmd, ipr_abort_timeout, IPR_CANCEL_ALL_TIMEOUT);
4953 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
4954
4955
4956
4957
4958
4959 if (ioasc == IPR_IOASC_BUS_WAS_RESET || ioasc == IPR_IOASC_SYNC_REQUIRED) {
4960 ioasc = 0;
4961 ipr_trace;
4962 }
4963
4964 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
4965 if (!ipr_is_naca_model(res))
4966 res->needs_sync_complete = 1;
4967
4968 LEAVE;
4969 return (IPR_IOASC_SENSE_KEY(ioasc) ? FAILED : SUCCESS);
4970}
4971
4972
4973
4974
4975
4976
4977
4978
4979static int ipr_eh_abort(struct scsi_cmnd * scsi_cmd)
4980{
4981 unsigned long flags;
4982 int rc;
4983
4984 ENTER;
4985
4986 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
4987 rc = ipr_cancel_op(scsi_cmd);
4988 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
4989
4990 LEAVE;
4991 return rc;
4992}
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
5003 u32 int_reg)
5004{
5005 irqreturn_t rc = IRQ_HANDLED;
5006 u32 int_mask_reg;
5007
5008 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
5009 int_reg &= ~int_mask_reg;
5010
5011
5012
5013
5014 if ((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0) {
5015 if (ioa_cfg->sis64) {
5016 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
5017 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5018 if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
5019
5020
5021 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
5022 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5023 list_del(&ioa_cfg->reset_cmd->queue);
5024 del_timer(&ioa_cfg->reset_cmd->timer);
5025 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5026 return IRQ_HANDLED;
5027 }
5028 }
5029
5030 return IRQ_NONE;
5031 }
5032
5033 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
5034
5035 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.set_interrupt_mask_reg);
5036
5037
5038 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.clr_interrupt_reg);
5039 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5040
5041 list_del(&ioa_cfg->reset_cmd->queue);
5042 del_timer(&ioa_cfg->reset_cmd->timer);
5043 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5044 } else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
5045 if (ipr_debug && printk_ratelimit())
5046 dev_err(&ioa_cfg->pdev->dev,
5047 "Spurious interrupt detected. 0x%08X\n", int_reg);
5048 writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
5049 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5050 return IRQ_NONE;
5051 } else {
5052 if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
5053 ioa_cfg->ioa_unit_checked = 1;
5054 else
5055 dev_err(&ioa_cfg->pdev->dev,
5056 "Permanent IOA failure. 0x%08X\n", int_reg);
5057
5058 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5059 ioa_cfg->sdt_state = GET_DUMP;
5060
5061 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
5062 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5063 }
5064
5065 return rc;
5066}
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076static void ipr_isr_eh(struct ipr_ioa_cfg *ioa_cfg, char *msg)
5077{
5078 ioa_cfg->errors_logged++;
5079 dev_err(&ioa_cfg->pdev->dev, "%s\n", msg);
5080
5081 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5082 ioa_cfg->sdt_state = GET_DUMP;
5083
5084 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5085}
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095static irqreturn_t ipr_isr(int irq, void *devp)
5096{
5097 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
5098 unsigned long lock_flags = 0;
5099 u32 int_reg = 0;
5100 u32 ioasc;
5101 u16 cmd_index;
5102 int num_hrrq = 0;
5103 int irq_none = 0;
5104 struct ipr_cmnd *ipr_cmd;
5105 irqreturn_t rc = IRQ_NONE;
5106
5107 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5108
5109
5110 if (!ioa_cfg->allow_interrupts) {
5111 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5112 return IRQ_NONE;
5113 }
5114
5115 while (1) {
5116 ipr_cmd = NULL;
5117
5118 while ((be32_to_cpu(*ioa_cfg->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5119 ioa_cfg->toggle_bit) {
5120
5121 cmd_index = (be32_to_cpu(*ioa_cfg->hrrq_curr) &
5122 IPR_HRRQ_REQ_RESP_HANDLE_MASK) >> IPR_HRRQ_REQ_RESP_HANDLE_SHIFT;
5123
5124 if (unlikely(cmd_index >= IPR_NUM_CMD_BLKS)) {
5125 ipr_isr_eh(ioa_cfg, "Invalid response handle from IOA");
5126 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5127 return IRQ_HANDLED;
5128 }
5129
5130 ipr_cmd = ioa_cfg->ipr_cmnd_list[cmd_index];
5131
5132 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5133
5134 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH, ioasc);
5135
5136 list_del(&ipr_cmd->queue);
5137 del_timer(&ipr_cmd->timer);
5138 ipr_cmd->done(ipr_cmd);
5139
5140 rc = IRQ_HANDLED;
5141
5142 if (ioa_cfg->hrrq_curr < ioa_cfg->hrrq_end) {
5143 ioa_cfg->hrrq_curr++;
5144 } else {
5145 ioa_cfg->hrrq_curr = ioa_cfg->hrrq_start;
5146 ioa_cfg->toggle_bit ^= 1u;
5147 }
5148 }
5149
5150 if (ipr_cmd != NULL) {
5151
5152 num_hrrq = 0;
5153 do {
5154 writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
5155 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5156 } while (int_reg & IPR_PCII_HRRQ_UPDATED &&
5157 num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
5158
5159 } else if (rc == IRQ_NONE && irq_none == 0) {
5160 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5161 irq_none++;
5162 } else if (num_hrrq == IPR_MAX_HRRQ_RETRIES &&
5163 int_reg & IPR_PCII_HRRQ_UPDATED) {
5164 ipr_isr_eh(ioa_cfg, "Error clearing HRRQ");
5165 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5166 return IRQ_HANDLED;
5167 } else
5168 break;
5169 }
5170
5171 if (unlikely(rc == IRQ_NONE))
5172 rc = ipr_handle_other_interrupt(ioa_cfg, int_reg);
5173
5174 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5175 return rc;
5176}
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg,
5187 struct ipr_cmnd *ipr_cmd)
5188{
5189 int i, nseg;
5190 struct scatterlist *sg;
5191 u32 length;
5192 u32 ioadl_flags = 0;
5193 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5194 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5195 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
5196
5197 length = scsi_bufflen(scsi_cmd);
5198 if (!length)
5199 return 0;
5200
5201 nseg = scsi_dma_map(scsi_cmd);
5202 if (nseg < 0) {
5203 if (printk_ratelimit())
5204 dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
5205 return -1;
5206 }
5207
5208 ipr_cmd->dma_use_sg = nseg;
5209
5210 ioarcb->data_transfer_length = cpu_to_be32(length);
5211 ioarcb->ioadl_len =
5212 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
5213
5214 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5215 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5216 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5217 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE)
5218 ioadl_flags = IPR_IOADL_FLAGS_READ;
5219
5220 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5221 ioadl64[i].flags = cpu_to_be32(ioadl_flags);
5222 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
5223 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
5224 }
5225
5226 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5227 return 0;
5228}
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg,
5239 struct ipr_cmnd *ipr_cmd)
5240{
5241 int i, nseg;
5242 struct scatterlist *sg;
5243 u32 length;
5244 u32 ioadl_flags = 0;
5245 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5246 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5247 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
5248
5249 length = scsi_bufflen(scsi_cmd);
5250 if (!length)
5251 return 0;
5252
5253 nseg = scsi_dma_map(scsi_cmd);
5254 if (nseg < 0) {
5255 dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
5256 return -1;
5257 }
5258
5259 ipr_cmd->dma_use_sg = nseg;
5260
5261 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5262 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5263 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5264 ioarcb->data_transfer_length = cpu_to_be32(length);
5265 ioarcb->ioadl_len =
5266 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5267 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) {
5268 ioadl_flags = IPR_IOADL_FLAGS_READ;
5269 ioarcb->read_data_transfer_length = cpu_to_be32(length);
5270 ioarcb->read_ioadl_len =
5271 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5272 }
5273
5274 if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->u.add_data.u.ioadl)) {
5275 ioadl = ioarcb->u.add_data.u.ioadl;
5276 ioarcb->write_ioadl_addr = cpu_to_be32((ipr_cmd->dma_addr) +
5277 offsetof(struct ipr_ioarcb, u.add_data));
5278 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5279 }
5280
5281 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5282 ioadl[i].flags_and_data_len =
5283 cpu_to_be32(ioadl_flags | sg_dma_len(sg));
5284 ioadl[i].address = cpu_to_be32(sg_dma_address(sg));
5285 }
5286
5287 ioadl[i-1].flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5288 return 0;
5289}
5290
5291
5292
5293
5294
5295
5296
5297
5298static u8 ipr_get_task_attributes(struct scsi_cmnd *scsi_cmd)
5299{
5300 u8 tag[2];
5301 u8 rc = IPR_FLAGS_LO_UNTAGGED_TASK;
5302
5303 if (scsi_populate_tag_msg(scsi_cmd, tag)) {
5304 switch (tag[0]) {
5305 case MSG_SIMPLE_TAG:
5306 rc = IPR_FLAGS_LO_SIMPLE_TASK;
5307 break;
5308 case MSG_HEAD_TAG:
5309 rc = IPR_FLAGS_LO_HEAD_OF_Q_TASK;
5310 break;
5311 case MSG_ORDERED_TAG:
5312 rc = IPR_FLAGS_LO_ORDERED_TASK;
5313 break;
5314 };
5315 }
5316
5317 return rc;
5318}
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330static void ipr_erp_done(struct ipr_cmnd *ipr_cmd)
5331{
5332 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5333 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5334 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5335 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5336
5337 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5338 scsi_cmd->result |= (DID_ERROR << 16);
5339 scmd_printk(KERN_ERR, scsi_cmd,
5340 "Request Sense failed with IOASC: 0x%08X\n", ioasc);
5341 } else {
5342 memcpy(scsi_cmd->sense_buffer, ipr_cmd->sense_buffer,
5343 SCSI_SENSE_BUFFERSIZE);
5344 }
5345
5346 if (res) {
5347 if (!ipr_is_naca_model(res))
5348 res->needs_sync_complete = 1;
5349 res->in_erp = 0;
5350 }
5351 scsi_dma_unmap(ipr_cmd->scsi_cmd);
5352 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
5353 scsi_cmd->scsi_done(scsi_cmd);
5354}
5355
5356
5357
5358
5359
5360
5361
5362
5363static void ipr_reinit_ipr_cmnd_for_erp(struct ipr_cmnd *ipr_cmd)
5364{
5365 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5366 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5367 dma_addr_t dma_addr = ipr_cmd->dma_addr;
5368
5369 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
5370 ioarcb->data_transfer_length = 0;
5371 ioarcb->read_data_transfer_length = 0;
5372 ioarcb->ioadl_len = 0;
5373 ioarcb->read_ioadl_len = 0;
5374 ioasa->hdr.ioasc = 0;
5375 ioasa->hdr.residual_data_len = 0;
5376
5377 if (ipr_cmd->ioa_cfg->sis64)
5378 ioarcb->u.sis64_addr_data.data_ioadl_addr =
5379 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
5380 else {
5381 ioarcb->write_ioadl_addr =
5382 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
5383 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5384 }
5385}
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397static void ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
5398{
5399 struct ipr_cmd_pkt *cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5400 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5401
5402 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5403 ipr_erp_done(ipr_cmd);
5404 return;
5405 }
5406
5407 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5408
5409 cmd_pkt->request_type = IPR_RQTYPE_SCSICDB;
5410 cmd_pkt->cdb[0] = REQUEST_SENSE;
5411 cmd_pkt->cdb[4] = SCSI_SENSE_BUFFERSIZE;
5412 cmd_pkt->flags_hi |= IPR_FLAGS_HI_SYNC_OVERRIDE;
5413 cmd_pkt->flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
5414 cmd_pkt->timeout = cpu_to_be16(IPR_REQUEST_SENSE_TIMEOUT / HZ);
5415
5416 ipr_init_ioadl(ipr_cmd, ipr_cmd->sense_buffer_dma,
5417 SCSI_SENSE_BUFFERSIZE, IPR_IOADL_FLAGS_READ_LAST);
5418
5419 ipr_do_req(ipr_cmd, ipr_erp_done, ipr_timeout,
5420 IPR_REQUEST_SENSE_TIMEOUT * 2);
5421}
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435static void ipr_erp_cancel_all(struct ipr_cmnd *ipr_cmd)
5436{
5437 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5438 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5439 struct ipr_cmd_pkt *cmd_pkt;
5440
5441 res->in_erp = 1;
5442
5443 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5444
5445 if (!scsi_get_tag_type(scsi_cmd->device)) {
5446 ipr_erp_request_sense(ipr_cmd);
5447 return;
5448 }
5449
5450 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5451 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5452 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5453
5454 ipr_do_req(ipr_cmd, ipr_erp_request_sense, ipr_timeout,
5455 IPR_CANCEL_ALL_TIMEOUT);
5456}
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471static void ipr_dump_ioasa(struct ipr_ioa_cfg *ioa_cfg,
5472 struct ipr_cmnd *ipr_cmd, struct ipr_resource_entry *res)
5473{
5474 int i;
5475 u16 data_len;
5476 u32 ioasc, fd_ioasc;
5477 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5478 __be32 *ioasa_data = (__be32 *)ioasa;
5479 int error_index;
5480
5481 ioasc = be32_to_cpu(ioasa->hdr.ioasc) & IPR_IOASC_IOASC_MASK;
5482 fd_ioasc = be32_to_cpu(ioasa->hdr.fd_ioasc) & IPR_IOASC_IOASC_MASK;
5483
5484 if (0 == ioasc)
5485 return;
5486
5487 if (ioa_cfg->log_level < IPR_DEFAULT_LOG_LEVEL)
5488 return;
5489
5490 if (ioasc == IPR_IOASC_BUS_WAS_RESET && fd_ioasc)
5491 error_index = ipr_get_error(fd_ioasc);
5492 else
5493 error_index = ipr_get_error(ioasc);
5494
5495 if (ioa_cfg->log_level < IPR_MAX_LOG_LEVEL) {
5496
5497 if (ioasa->hdr.ilid != 0)
5498 return;
5499
5500 if (!ipr_is_gscsi(res))
5501 return;
5502
5503 if (ipr_error_table[error_index].log_ioasa == 0)
5504 return;
5505 }
5506
5507 ipr_res_err(ioa_cfg, res, "%s\n", ipr_error_table[error_index].error);
5508
5509 data_len = be16_to_cpu(ioasa->hdr.ret_stat_len);
5510 if (ioa_cfg->sis64 && sizeof(struct ipr_ioasa64) < data_len)
5511 data_len = sizeof(struct ipr_ioasa64);
5512 else if (!ioa_cfg->sis64 && sizeof(struct ipr_ioasa) < data_len)
5513 data_len = sizeof(struct ipr_ioasa);
5514
5515 ipr_err("IOASA Dump:\n");
5516
5517 for (i = 0; i < data_len / 4; i += 4) {
5518 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
5519 be32_to_cpu(ioasa_data[i]),
5520 be32_to_cpu(ioasa_data[i+1]),
5521 be32_to_cpu(ioasa_data[i+2]),
5522 be32_to_cpu(ioasa_data[i+3]));
5523 }
5524}
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534static void ipr_gen_sense(struct ipr_cmnd *ipr_cmd)
5535{
5536 u32 failing_lba;
5537 u8 *sense_buf = ipr_cmd->scsi_cmd->sense_buffer;
5538 struct ipr_resource_entry *res = ipr_cmd->scsi_cmd->device->hostdata;
5539 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5540 u32 ioasc = be32_to_cpu(ioasa->hdr.ioasc);
5541
5542 memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
5543
5544 if (ioasc >= IPR_FIRST_DRIVER_IOASC)
5545 return;
5546
5547 ipr_cmd->scsi_cmd->result = SAM_STAT_CHECK_CONDITION;
5548
5549 if (ipr_is_vset_device(res) &&
5550 ioasc == IPR_IOASC_MED_DO_NOT_REALLOC &&
5551 ioasa->u.vset.failing_lba_hi != 0) {
5552 sense_buf[0] = 0x72;
5553 sense_buf[1] = IPR_IOASC_SENSE_KEY(ioasc);
5554 sense_buf[2] = IPR_IOASC_SENSE_CODE(ioasc);
5555 sense_buf[3] = IPR_IOASC_SENSE_QUAL(ioasc);
5556
5557 sense_buf[7] = 12;
5558 sense_buf[8] = 0;
5559 sense_buf[9] = 0x0A;
5560 sense_buf[10] = 0x80;
5561
5562 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_hi);
5563
5564 sense_buf[12] = (failing_lba & 0xff000000) >> 24;
5565 sense_buf[13] = (failing_lba & 0x00ff0000) >> 16;
5566 sense_buf[14] = (failing_lba & 0x0000ff00) >> 8;
5567 sense_buf[15] = failing_lba & 0x000000ff;
5568
5569 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
5570
5571 sense_buf[16] = (failing_lba & 0xff000000) >> 24;
5572 sense_buf[17] = (failing_lba & 0x00ff0000) >> 16;
5573 sense_buf[18] = (failing_lba & 0x0000ff00) >> 8;
5574 sense_buf[19] = failing_lba & 0x000000ff;
5575 } else {
5576 sense_buf[0] = 0x70;
5577 sense_buf[2] = IPR_IOASC_SENSE_KEY(ioasc);
5578 sense_buf[12] = IPR_IOASC_SENSE_CODE(ioasc);
5579 sense_buf[13] = IPR_IOASC_SENSE_QUAL(ioasc);
5580
5581
5582 if ((IPR_IOASC_SENSE_KEY(ioasc) == 0x05) &&
5583 (be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_FIELD_POINTER_VALID)) {
5584 sense_buf[7] = 10;
5585
5586
5587 if (IPR_IOASC_SENSE_CODE(ioasc) == 0x24)
5588 sense_buf[15] = 0xC0;
5589 else
5590 sense_buf[15] = 0x80;
5591
5592 sense_buf[16] =
5593 ((IPR_FIELD_POINTER_MASK &
5594 be32_to_cpu(ioasa->hdr.ioasc_specific)) >> 8) & 0xff;
5595 sense_buf[17] =
5596 (IPR_FIELD_POINTER_MASK &
5597 be32_to_cpu(ioasa->hdr.ioasc_specific)) & 0xff;
5598 } else {
5599 if (ioasc == IPR_IOASC_MED_DO_NOT_REALLOC) {
5600 if (ipr_is_vset_device(res))
5601 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
5602 else
5603 failing_lba = be32_to_cpu(ioasa->u.dasd.failing_lba);
5604
5605 sense_buf[0] |= 0x80;
5606 sense_buf[3] = (failing_lba & 0xff000000) >> 24;
5607 sense_buf[4] = (failing_lba & 0x00ff0000) >> 16;
5608 sense_buf[5] = (failing_lba & 0x0000ff00) >> 8;
5609 sense_buf[6] = failing_lba & 0x000000ff;
5610 }
5611
5612 sense_buf[7] = 6;
5613 }
5614 }
5615}
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627static int ipr_get_autosense(struct ipr_cmnd *ipr_cmd)
5628{
5629 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5630 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
5631
5632 if ((be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_AUTOSENSE_VALID) == 0)
5633 return 0;
5634
5635 if (ipr_cmd->ioa_cfg->sis64)
5636 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa64->auto_sense.data,
5637 min_t(u16, be16_to_cpu(ioasa64->auto_sense.auto_sense_len),
5638 SCSI_SENSE_BUFFERSIZE));
5639 else
5640 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa->auto_sense.data,
5641 min_t(u16, be16_to_cpu(ioasa->auto_sense.auto_sense_len),
5642 SCSI_SENSE_BUFFERSIZE));
5643 return 1;
5644}
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657static void ipr_erp_start(struct ipr_ioa_cfg *ioa_cfg,
5658 struct ipr_cmnd *ipr_cmd)
5659{
5660 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5661 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5662 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5663 u32 masked_ioasc = ioasc & IPR_IOASC_IOASC_MASK;
5664
5665 if (!res) {
5666 ipr_scsi_eh_done(ipr_cmd);
5667 return;
5668 }
5669
5670 if (!ipr_is_gscsi(res) && masked_ioasc != IPR_IOASC_HW_DEV_BUS_STATUS)
5671 ipr_gen_sense(ipr_cmd);
5672
5673 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
5674
5675 switch (masked_ioasc) {
5676 case IPR_IOASC_ABORTED_CMD_TERM_BY_HOST:
5677 if (ipr_is_naca_model(res))
5678 scsi_cmd->result |= (DID_ABORT << 16);
5679 else
5680 scsi_cmd->result |= (DID_IMM_RETRY << 16);
5681 break;
5682 case IPR_IOASC_IR_RESOURCE_HANDLE:
5683 case IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA:
5684 scsi_cmd->result |= (DID_NO_CONNECT << 16);
5685 break;
5686 case IPR_IOASC_HW_SEL_TIMEOUT:
5687 scsi_cmd->result |= (DID_NO_CONNECT << 16);
5688 if (!ipr_is_naca_model(res))
5689 res->needs_sync_complete = 1;
5690 break;
5691 case IPR_IOASC_SYNC_REQUIRED:
5692 if (!res->in_erp)
5693 res->needs_sync_complete = 1;
5694 scsi_cmd->result |= (DID_IMM_RETRY << 16);
5695 break;
5696 case IPR_IOASC_MED_DO_NOT_REALLOC:
5697 case IPR_IOASA_IR_DUAL_IOA_DISABLED:
5698 scsi_cmd->result |= (DID_PASSTHROUGH << 16);
5699 break;
5700 case IPR_IOASC_BUS_WAS_RESET:
5701 case IPR_IOASC_BUS_WAS_RESET_BY_OTHER:
5702
5703
5704
5705
5706 if (!res->resetting_device)
5707 scsi_report_bus_reset(ioa_cfg->host, scsi_cmd->device->channel);
5708 scsi_cmd->result |= (DID_ERROR << 16);
5709 if (!ipr_is_naca_model(res))
5710 res->needs_sync_complete = 1;
5711 break;
5712 case IPR_IOASC_HW_DEV_BUS_STATUS:
5713 scsi_cmd->result |= IPR_IOASC_SENSE_STATUS(ioasc);
5714 if (IPR_IOASC_SENSE_STATUS(ioasc) == SAM_STAT_CHECK_CONDITION) {
5715 if (!ipr_get_autosense(ipr_cmd)) {
5716 if (!ipr_is_naca_model(res)) {
5717 ipr_erp_cancel_all(ipr_cmd);
5718 return;
5719 }
5720 }
5721 }
5722 if (!ipr_is_naca_model(res))
5723 res->needs_sync_complete = 1;
5724 break;
5725 case IPR_IOASC_NR_INIT_CMD_REQUIRED:
5726 break;
5727 default:
5728 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
5729 scsi_cmd->result |= (DID_ERROR << 16);
5730 if (!ipr_is_vset_device(res) && !ipr_is_naca_model(res))
5731 res->needs_sync_complete = 1;
5732 break;
5733 }
5734
5735 scsi_dma_unmap(ipr_cmd->scsi_cmd);
5736 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
5737 scsi_cmd->scsi_done(scsi_cmd);
5738}
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750static void ipr_scsi_done(struct ipr_cmnd *ipr_cmd)
5751{
5752 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5753 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5754 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5755
5756 scsi_set_resid(scsi_cmd, be32_to_cpu(ipr_cmd->s.ioasa.hdr.residual_data_len));
5757
5758 if (likely(IPR_IOASC_SENSE_KEY(ioasc) == 0)) {
5759 scsi_dma_unmap(ipr_cmd->scsi_cmd);
5760 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
5761 scsi_cmd->scsi_done(scsi_cmd);
5762 } else
5763 ipr_erp_start(ioa_cfg, ipr_cmd);
5764}
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778static int ipr_queuecommand_lck(struct scsi_cmnd *scsi_cmd,
5779 void (*done) (struct scsi_cmnd *))
5780{
5781 struct ipr_ioa_cfg *ioa_cfg;
5782 struct ipr_resource_entry *res;
5783 struct ipr_ioarcb *ioarcb;
5784 struct ipr_cmnd *ipr_cmd;
5785 int rc = 0;
5786
5787 scsi_cmd->scsi_done = done;
5788 ioa_cfg = (struct ipr_ioa_cfg *)scsi_cmd->device->host->hostdata;
5789 res = scsi_cmd->device->hostdata;
5790 scsi_cmd->result = (DID_OK << 16);
5791
5792
5793
5794
5795
5796
5797 if (unlikely(!ioa_cfg->allow_cmds && !ioa_cfg->ioa_is_dead))
5798 return SCSI_MLQUEUE_HOST_BUSY;
5799
5800
5801
5802
5803
5804 if (unlikely(ioa_cfg->ioa_is_dead || !res)) {
5805 memset(scsi_cmd->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
5806 scsi_cmd->result = (DID_NO_CONNECT << 16);
5807 scsi_cmd->scsi_done(scsi_cmd);
5808 return 0;
5809 }
5810
5811 if (ipr_is_gata(res) && res->sata_port)
5812 return ata_sas_queuecmd(scsi_cmd, res->sata_port->ap);
5813
5814 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5815 ioarcb = &ipr_cmd->ioarcb;
5816 list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q);
5817
5818 memcpy(ioarcb->cmd_pkt.cdb, scsi_cmd->cmnd, scsi_cmd->cmd_len);
5819 ipr_cmd->scsi_cmd = scsi_cmd;
5820 ioarcb->res_handle = res->res_handle;
5821 ipr_cmd->done = ipr_scsi_done;
5822 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
5823
5824 if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) {
5825 if (scsi_cmd->underflow == 0)
5826 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
5827
5828 if (res->needs_sync_complete) {
5829 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_SYNC_COMPLETE;
5830 res->needs_sync_complete = 0;
5831 }
5832
5833 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
5834 if (ipr_is_gscsi(res))
5835 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST;
5836 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR;
5837 ioarcb->cmd_pkt.flags_lo |= ipr_get_task_attributes(scsi_cmd);
5838 }
5839
5840 if (scsi_cmd->cmnd[0] >= 0xC0 &&
5841 (!ipr_is_gscsi(res) || scsi_cmd->cmnd[0] == IPR_QUERY_RSRC_STATE))
5842 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
5843
5844 if (likely(rc == 0)) {
5845 if (ioa_cfg->sis64)
5846 rc = ipr_build_ioadl64(ioa_cfg, ipr_cmd);
5847 else
5848 rc = ipr_build_ioadl(ioa_cfg, ipr_cmd);
5849 }
5850
5851 if (likely(rc == 0)) {
5852 mb();
5853 ipr_send_command(ipr_cmd);
5854 } else {
5855 list_move_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
5856 return SCSI_MLQUEUE_HOST_BUSY;
5857 }
5858
5859 return 0;
5860}
5861
5862static DEF_SCSI_QCMD(ipr_queuecommand)
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873static int ipr_ioctl(struct scsi_device *sdev, int cmd, void __user *arg)
5874{
5875 struct ipr_resource_entry *res;
5876
5877 res = (struct ipr_resource_entry *)sdev->hostdata;
5878 if (res && ipr_is_gata(res)) {
5879 if (cmd == HDIO_GET_IDENTITY)
5880 return -ENOTTY;
5881 return ata_sas_scsi_ioctl(res->sata_port->ap, sdev, cmd, arg);
5882 }
5883
5884 return -EINVAL;
5885}
5886
5887
5888
5889
5890
5891
5892
5893
5894static const char * ipr_ioa_info(struct Scsi_Host *host)
5895{
5896 static char buffer[512];
5897 struct ipr_ioa_cfg *ioa_cfg;
5898 unsigned long lock_flags = 0;
5899
5900 ioa_cfg = (struct ipr_ioa_cfg *) host->hostdata;
5901
5902 spin_lock_irqsave(host->host_lock, lock_flags);
5903 sprintf(buffer, "IBM %X Storage Adapter", ioa_cfg->type);
5904 spin_unlock_irqrestore(host->host_lock, lock_flags);
5905
5906 return buffer;
5907}
5908
5909static struct scsi_host_template driver_template = {
5910 .module = THIS_MODULE,
5911 .name = "IPR",
5912 .info = ipr_ioa_info,
5913 .ioctl = ipr_ioctl,
5914 .queuecommand = ipr_queuecommand,
5915 .eh_abort_handler = ipr_eh_abort,
5916 .eh_device_reset_handler = ipr_eh_dev_reset,
5917 .eh_host_reset_handler = ipr_eh_host_reset,
5918 .slave_alloc = ipr_slave_alloc,
5919 .slave_configure = ipr_slave_configure,
5920 .slave_destroy = ipr_slave_destroy,
5921 .target_alloc = ipr_target_alloc,
5922 .target_destroy = ipr_target_destroy,
5923 .change_queue_depth = ipr_change_queue_depth,
5924 .change_queue_type = ipr_change_queue_type,
5925 .bios_param = ipr_biosparam,
5926 .can_queue = IPR_MAX_COMMANDS,
5927 .this_id = -1,
5928 .sg_tablesize = IPR_MAX_SGLIST,
5929 .max_sectors = IPR_IOA_MAX_SECTORS,
5930 .cmd_per_lun = IPR_MAX_CMD_PER_LUN,
5931 .use_clustering = ENABLE_CLUSTERING,
5932 .shost_attrs = ipr_ioa_attrs,
5933 .sdev_attrs = ipr_dev_attrs,
5934 .proc_name = IPR_NAME
5935};
5936
5937
5938
5939
5940
5941
5942static void ipr_ata_phy_reset(struct ata_port *ap)
5943{
5944 unsigned long flags;
5945 struct ipr_sata_port *sata_port = ap->private_data;
5946 struct ipr_resource_entry *res = sata_port->res;
5947 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
5948 int rc;
5949
5950 ENTER;
5951 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
5952 while(ioa_cfg->in_reset_reload) {
5953 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
5954 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5955 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
5956 }
5957
5958 if (!ioa_cfg->allow_cmds)
5959 goto out_unlock;
5960
5961 rc = ipr_device_reset(ioa_cfg, res);
5962
5963 if (rc) {
5964 ap->link.device[0].class = ATA_DEV_NONE;
5965 goto out_unlock;
5966 }
5967
5968 ap->link.device[0].class = res->ata_class;
5969 if (ap->link.device[0].class == ATA_DEV_UNKNOWN)
5970 ap->link.device[0].class = ATA_DEV_NONE;
5971
5972out_unlock:
5973 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
5974 LEAVE;
5975}
5976
5977
5978
5979
5980
5981
5982
5983
5984static void ipr_ata_post_internal(struct ata_queued_cmd *qc)
5985{
5986 struct ipr_sata_port *sata_port = qc->ap->private_data;
5987 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
5988 struct ipr_cmnd *ipr_cmd;
5989 unsigned long flags;
5990
5991 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
5992 while(ioa_cfg->in_reset_reload) {
5993 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
5994 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5995 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
5996 }
5997
5998 list_for_each_entry(ipr_cmd, &ioa_cfg->pending_q, queue) {
5999 if (ipr_cmd->qc == qc) {
6000 ipr_device_reset(ioa_cfg, sata_port->res);
6001 break;
6002 }
6003 }
6004 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6005}
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015static void ipr_copy_sata_tf(struct ipr_ioarcb_ata_regs *regs,
6016 struct ata_taskfile *tf)
6017{
6018 regs->feature = tf->feature;
6019 regs->nsect = tf->nsect;
6020 regs->lbal = tf->lbal;
6021 regs->lbam = tf->lbam;
6022 regs->lbah = tf->lbah;
6023 regs->device = tf->device;
6024 regs->command = tf->command;
6025 regs->hob_feature = tf->hob_feature;
6026 regs->hob_nsect = tf->hob_nsect;
6027 regs->hob_lbal = tf->hob_lbal;
6028 regs->hob_lbam = tf->hob_lbam;
6029 regs->hob_lbah = tf->hob_lbah;
6030 regs->ctl = tf->ctl;
6031}
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043static void ipr_sata_done(struct ipr_cmnd *ipr_cmd)
6044{
6045 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6046 struct ata_queued_cmd *qc = ipr_cmd->qc;
6047 struct ipr_sata_port *sata_port = qc->ap->private_data;
6048 struct ipr_resource_entry *res = sata_port->res;
6049 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6050
6051 if (ipr_cmd->ioa_cfg->sis64)
6052 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
6053 sizeof(struct ipr_ioasa_gata));
6054 else
6055 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
6056 sizeof(struct ipr_ioasa_gata));
6057 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6058
6059 if (be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc_specific) & IPR_ATA_DEVICE_WAS_RESET)
6060 scsi_report_device_reset(ioa_cfg->host, res->bus, res->target);
6061
6062 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6063 qc->err_mask |= __ac_err_mask(sata_port->ioasa.status);
6064 else
6065 qc->err_mask |= ac_err_mask(sata_port->ioasa.status);
6066 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
6067 ata_qc_complete(qc);
6068}
6069
6070
6071
6072
6073
6074
6075
6076static void ipr_build_ata_ioadl64(struct ipr_cmnd *ipr_cmd,
6077 struct ata_queued_cmd *qc)
6078{
6079 u32 ioadl_flags = 0;
6080 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6081 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
6082 struct ipr_ioadl64_desc *last_ioadl64 = NULL;
6083 int len = qc->nbytes;
6084 struct scatterlist *sg;
6085 unsigned int si;
6086 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6087
6088 if (len == 0)
6089 return;
6090
6091 if (qc->dma_dir == DMA_TO_DEVICE) {
6092 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6093 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6094 } else if (qc->dma_dir == DMA_FROM_DEVICE)
6095 ioadl_flags = IPR_IOADL_FLAGS_READ;
6096
6097 ioarcb->data_transfer_length = cpu_to_be32(len);
6098 ioarcb->ioadl_len =
6099 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
6100 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6101 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ata_ioadl));
6102
6103 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6104 ioadl64->flags = cpu_to_be32(ioadl_flags);
6105 ioadl64->data_len = cpu_to_be32(sg_dma_len(sg));
6106 ioadl64->address = cpu_to_be64(sg_dma_address(sg));
6107
6108 last_ioadl64 = ioadl64;
6109 ioadl64++;
6110 }
6111
6112 if (likely(last_ioadl64))
6113 last_ioadl64->flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6114}
6115
6116
6117
6118
6119
6120
6121
6122static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd,
6123 struct ata_queued_cmd *qc)
6124{
6125 u32 ioadl_flags = 0;
6126 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6127 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
6128 struct ipr_ioadl_desc *last_ioadl = NULL;
6129 int len = qc->nbytes;
6130 struct scatterlist *sg;
6131 unsigned int si;
6132
6133 if (len == 0)
6134 return;
6135
6136 if (qc->dma_dir == DMA_TO_DEVICE) {
6137 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6138 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6139 ioarcb->data_transfer_length = cpu_to_be32(len);
6140 ioarcb->ioadl_len =
6141 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6142 } else if (qc->dma_dir == DMA_FROM_DEVICE) {
6143 ioadl_flags = IPR_IOADL_FLAGS_READ;
6144 ioarcb->read_data_transfer_length = cpu_to_be32(len);
6145 ioarcb->read_ioadl_len =
6146 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6147 }
6148
6149 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6150 ioadl->flags_and_data_len = cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6151 ioadl->address = cpu_to_be32(sg_dma_address(sg));
6152
6153 last_ioadl = ioadl;
6154 ioadl++;
6155 }
6156
6157 if (likely(last_ioadl))
6158 last_ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6159}
6160
6161
6162
6163
6164
6165
6166
6167
6168static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc)
6169{
6170 struct ata_port *ap = qc->ap;
6171 struct ipr_sata_port *sata_port = ap->private_data;
6172 struct ipr_resource_entry *res = sata_port->res;
6173 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6174 struct ipr_cmnd *ipr_cmd;
6175 struct ipr_ioarcb *ioarcb;
6176 struct ipr_ioarcb_ata_regs *regs;
6177
6178 if (unlikely(!ioa_cfg->allow_cmds || ioa_cfg->ioa_is_dead))
6179 return AC_ERR_SYSTEM;
6180
6181 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
6182 ioarcb = &ipr_cmd->ioarcb;
6183
6184 if (ioa_cfg->sis64) {
6185 regs = &ipr_cmd->i.ata_ioadl.regs;
6186 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
6187 } else
6188 regs = &ioarcb->u.add_data.u.regs;
6189
6190 memset(regs, 0, sizeof(*regs));
6191 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(*regs));
6192
6193 list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q);
6194 ipr_cmd->qc = qc;
6195 ipr_cmd->done = ipr_sata_done;
6196 ipr_cmd->ioarcb.res_handle = res->res_handle;
6197 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_ATA_PASSTHRU;
6198 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6199 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6200 ipr_cmd->dma_use_sg = qc->n_elem;
6201
6202 if (ioa_cfg->sis64)
6203 ipr_build_ata_ioadl64(ipr_cmd, qc);
6204 else
6205 ipr_build_ata_ioadl(ipr_cmd, qc);
6206
6207 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
6208 ipr_copy_sata_tf(regs, &qc->tf);
6209 memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN);
6210 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6211
6212 switch (qc->tf.protocol) {
6213 case ATA_PROT_NODATA:
6214 case ATA_PROT_PIO:
6215 break;
6216
6217 case ATA_PROT_DMA:
6218 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6219 break;
6220
6221 case ATAPI_PROT_PIO:
6222 case ATAPI_PROT_NODATA:
6223 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6224 break;
6225
6226 case ATAPI_PROT_DMA:
6227 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6228 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6229 break;
6230
6231 default:
6232 WARN_ON(1);
6233 return AC_ERR_INVALID;
6234 }
6235
6236 mb();
6237
6238 ipr_send_command(ipr_cmd);
6239
6240 return 0;
6241}
6242
6243
6244
6245
6246
6247
6248
6249
6250static bool ipr_qc_fill_rtf(struct ata_queued_cmd *qc)
6251{
6252 struct ipr_sata_port *sata_port = qc->ap->private_data;
6253 struct ipr_ioasa_gata *g = &sata_port->ioasa;
6254 struct ata_taskfile *tf = &qc->result_tf;
6255
6256 tf->feature = g->error;
6257 tf->nsect = g->nsect;
6258 tf->lbal = g->lbal;
6259 tf->lbam = g->lbam;
6260 tf->lbah = g->lbah;
6261 tf->device = g->device;
6262 tf->command = g->status;
6263 tf->hob_nsect = g->hob_nsect;
6264 tf->hob_lbal = g->hob_lbal;
6265 tf->hob_lbam = g->hob_lbam;
6266 tf->hob_lbah = g->hob_lbah;
6267 tf->ctl = g->alt_status;
6268
6269 return true;
6270}
6271
6272static struct ata_port_operations ipr_sata_ops = {
6273 .phy_reset = ipr_ata_phy_reset,
6274 .hardreset = ipr_sata_reset,
6275 .post_internal_cmd = ipr_ata_post_internal,
6276 .qc_prep = ata_noop_qc_prep,
6277 .qc_issue = ipr_qc_issue,
6278 .qc_fill_rtf = ipr_qc_fill_rtf,
6279 .port_start = ata_sas_port_start,
6280 .port_stop = ata_sas_port_stop
6281};
6282
6283static struct ata_port_info sata_port_info = {
6284 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
6285 .pio_mask = ATA_PIO4_ONLY,
6286 .mwdma_mask = ATA_MWDMA2,
6287 .udma_mask = ATA_UDMA6,
6288 .port_ops = &ipr_sata_ops
6289};
6290
6291#ifdef CONFIG_PPC_PSERIES
6292static const u16 ipr_blocked_processors[] = {
6293 PV_NORTHSTAR,
6294 PV_PULSAR,
6295 PV_POWER4,
6296 PV_ICESTAR,
6297 PV_SSTAR,
6298 PV_POWER4p,
6299 PV_630,
6300 PV_630p
6301};
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314static int ipr_invalid_adapter(struct ipr_ioa_cfg *ioa_cfg)
6315{
6316 int i;
6317
6318 if ((ioa_cfg->type == 0x5702) && (ioa_cfg->pdev->revision < 4)) {
6319 for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++){
6320 if (__is_processor(ipr_blocked_processors[i]))
6321 return 1;
6322 }
6323 }
6324 return 0;
6325}
6326#else
6327#define ipr_invalid_adapter(ioa_cfg) 0
6328#endif
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340static int ipr_ioa_bringdown_done(struct ipr_cmnd *ipr_cmd)
6341{
6342 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6343
6344 ENTER;
6345 ioa_cfg->in_reset_reload = 0;
6346 ioa_cfg->reset_retries = 0;
6347 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
6348 wake_up_all(&ioa_cfg->reset_wait_q);
6349
6350 spin_unlock_irq(ioa_cfg->host->host_lock);
6351 scsi_unblock_requests(ioa_cfg->host);
6352 spin_lock_irq(ioa_cfg->host->host_lock);
6353 LEAVE;
6354
6355 return IPR_RC_JOB_RETURN;
6356}
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
6370{
6371 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6372 struct ipr_resource_entry *res;
6373 struct ipr_hostrcb *hostrcb, *temp;
6374 int i = 0;
6375
6376 ENTER;
6377 ioa_cfg->in_reset_reload = 0;
6378 ioa_cfg->allow_cmds = 1;
6379 ioa_cfg->reset_cmd = NULL;
6380 ioa_cfg->doorbell |= IPR_RUNTIME_RESET;
6381
6382 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
6383 if (ioa_cfg->allow_ml_add_del && (res->add_to_ml || res->del_from_ml)) {
6384 ipr_trace;
6385 break;
6386 }
6387 }
6388 schedule_work(&ioa_cfg->work_q);
6389
6390 list_for_each_entry_safe(hostrcb, temp, &ioa_cfg->hostrcb_free_q, queue) {
6391 list_del(&hostrcb->queue);
6392 if (i++ < IPR_NUM_LOG_HCAMS)
6393 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
6394 else
6395 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
6396 }
6397
6398 scsi_report_bus_reset(ioa_cfg->host, IPR_VSET_BUS);
6399 dev_info(&ioa_cfg->pdev->dev, "IOA initialized.\n");
6400
6401 ioa_cfg->reset_retries = 0;
6402 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
6403 wake_up_all(&ioa_cfg->reset_wait_q);
6404
6405 spin_unlock(ioa_cfg->host->host_lock);
6406 scsi_unblock_requests(ioa_cfg->host);
6407 spin_lock(ioa_cfg->host->host_lock);
6408
6409 if (!ioa_cfg->allow_cmds)
6410 scsi_block_requests(ioa_cfg->host);
6411
6412 LEAVE;
6413 return IPR_RC_JOB_RETURN;
6414}
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424static void ipr_set_sup_dev_dflt(struct ipr_supported_device *supported_dev,
6425 struct ipr_std_inq_vpids *vpids)
6426{
6427 memset(supported_dev, 0, sizeof(struct ipr_supported_device));
6428 memcpy(&supported_dev->vpids, vpids, sizeof(struct ipr_std_inq_vpids));
6429 supported_dev->num_records = 1;
6430 supported_dev->data_length =
6431 cpu_to_be16(sizeof(struct ipr_supported_device));
6432 supported_dev->reserved = 0;
6433}
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd)
6445{
6446 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6447 struct ipr_supported_device *supp_dev = &ioa_cfg->vpd_cbs->supp_dev;
6448 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6449 struct ipr_resource_entry *res = ipr_cmd->u.res;
6450
6451 ipr_cmd->job_step = ipr_ioa_reset_done;
6452
6453 list_for_each_entry_continue(res, &ioa_cfg->used_res_q, queue) {
6454 if (!ipr_is_scsi_disk(res))
6455 continue;
6456
6457 ipr_cmd->u.res = res;
6458 ipr_set_sup_dev_dflt(supp_dev, &res->std_inq_data.vpids);
6459
6460 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
6461 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6462 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6463
6464 ioarcb->cmd_pkt.cdb[0] = IPR_SET_SUPPORTED_DEVICES;
6465 ioarcb->cmd_pkt.cdb[1] = IPR_SET_ALL_SUPPORTED_DEVICES;
6466 ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff;
6467 ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff;
6468
6469 ipr_init_ioadl(ipr_cmd,
6470 ioa_cfg->vpd_cbs_dma +
6471 offsetof(struct ipr_misc_cbs, supp_dev),
6472 sizeof(struct ipr_supported_device),
6473 IPR_IOADL_FLAGS_WRITE_LAST);
6474
6475 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
6476 IPR_SET_SUP_DEVICE_TIMEOUT);
6477
6478 if (!ioa_cfg->sis64)
6479 ipr_cmd->job_step = ipr_set_supported_devs;
6480 return IPR_RC_JOB_RETURN;
6481 }
6482
6483 return IPR_RC_JOB_CONTINUE;
6484}
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495static void *ipr_get_mode_page(struct ipr_mode_pages *mode_pages,
6496 u32 page_code, u32 len)
6497{
6498 struct ipr_mode_page_hdr *mode_hdr;
6499 u32 page_length;
6500 u32 length;
6501
6502 if (!mode_pages || (mode_pages->hdr.length == 0))
6503 return NULL;
6504
6505 length = (mode_pages->hdr.length + 1) - 4 - mode_pages->hdr.block_desc_len;
6506 mode_hdr = (struct ipr_mode_page_hdr *)
6507 (mode_pages->data + mode_pages->hdr.block_desc_len);
6508
6509 while (length) {
6510 if (IPR_GET_MODE_PAGE_CODE(mode_hdr) == page_code) {
6511 if (mode_hdr->page_length >= (len - sizeof(struct ipr_mode_page_hdr)))
6512 return mode_hdr;
6513 break;
6514 } else {
6515 page_length = (sizeof(struct ipr_mode_page_hdr) +
6516 mode_hdr->page_length);
6517 length -= page_length;
6518 mode_hdr = (struct ipr_mode_page_hdr *)
6519 ((unsigned long)mode_hdr + page_length);
6520 }
6521 }
6522 return NULL;
6523}
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535static void ipr_check_term_power(struct ipr_ioa_cfg *ioa_cfg,
6536 struct ipr_mode_pages *mode_pages)
6537{
6538 int i;
6539 int entry_length;
6540 struct ipr_dev_bus_entry *bus;
6541 struct ipr_mode_page28 *mode_page;
6542
6543 mode_page = ipr_get_mode_page(mode_pages, 0x28,
6544 sizeof(struct ipr_mode_page28));
6545
6546 entry_length = mode_page->entry_length;
6547
6548 bus = mode_page->bus;
6549
6550 for (i = 0; i < mode_page->num_entries; i++) {
6551 if (bus->flags & IPR_SCSI_ATTR_NO_TERM_PWR) {
6552 dev_err(&ioa_cfg->pdev->dev,
6553 "Term power is absent on scsi bus %d\n",
6554 bus->res_addr.bus);
6555 }
6556
6557 bus = (struct ipr_dev_bus_entry *)((char *)bus + entry_length);
6558 }
6559}
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572static void ipr_scsi_bus_speed_limit(struct ipr_ioa_cfg *ioa_cfg)
6573{
6574 u32 max_xfer_rate;
6575 int i;
6576
6577 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
6578 max_xfer_rate = ipr_get_max_scsi_speed(ioa_cfg, i,
6579 ioa_cfg->bus_attr[i].bus_width);
6580
6581 if (max_xfer_rate < ioa_cfg->bus_attr[i].max_xfer_rate)
6582 ioa_cfg->bus_attr[i].max_xfer_rate = max_xfer_rate;
6583 }
6584}
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596static void ipr_modify_ioafp_mode_page_28(struct ipr_ioa_cfg *ioa_cfg,
6597 struct ipr_mode_pages *mode_pages)
6598{
6599 int i, entry_length;
6600 struct ipr_dev_bus_entry *bus;
6601 struct ipr_bus_attributes *bus_attr;
6602 struct ipr_mode_page28 *mode_page;
6603
6604 mode_page = ipr_get_mode_page(mode_pages, 0x28,
6605 sizeof(struct ipr_mode_page28));
6606
6607 entry_length = mode_page->entry_length;
6608
6609
6610 for (i = 0, bus = mode_page->bus;
6611 i < mode_page->num_entries;
6612 i++, bus = (struct ipr_dev_bus_entry *)((u8 *)bus + entry_length)) {
6613 if (bus->res_addr.bus > IPR_MAX_NUM_BUSES) {
6614 dev_err(&ioa_cfg->pdev->dev,
6615 "Invalid resource address reported: 0x%08X\n",
6616 IPR_GET_PHYS_LOC(bus->res_addr));
6617 continue;
6618 }
6619
6620 bus_attr = &ioa_cfg->bus_attr[i];
6621 bus->extended_reset_delay = IPR_EXTENDED_RESET_DELAY;
6622 bus->bus_width = bus_attr->bus_width;
6623 bus->max_xfer_rate = cpu_to_be32(bus_attr->max_xfer_rate);
6624 bus->flags &= ~IPR_SCSI_ATTR_QAS_MASK;
6625 if (bus_attr->qas_enabled)
6626 bus->flags |= IPR_SCSI_ATTR_ENABLE_QAS;
6627 else
6628 bus->flags |= IPR_SCSI_ATTR_DISABLE_QAS;
6629 }
6630}
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd,
6644 __be32 res_handle, u8 parm,
6645 dma_addr_t dma_addr, u8 xfer_len)
6646{
6647 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6648
6649 ioarcb->res_handle = res_handle;
6650 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
6651 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6652 ioarcb->cmd_pkt.cdb[0] = MODE_SELECT;
6653 ioarcb->cmd_pkt.cdb[1] = parm;
6654 ioarcb->cmd_pkt.cdb[4] = xfer_len;
6655
6656 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_WRITE_LAST);
6657}
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd)
6670{
6671 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6672 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
6673 int length;
6674
6675 ENTER;
6676 ipr_scsi_bus_speed_limit(ioa_cfg);
6677 ipr_check_term_power(ioa_cfg, mode_pages);
6678 ipr_modify_ioafp_mode_page_28(ioa_cfg, mode_pages);
6679 length = mode_pages->hdr.length + 1;
6680 mode_pages->hdr.length = 0;
6681
6682 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
6683 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
6684 length);
6685
6686 ipr_cmd->job_step = ipr_set_supported_devs;
6687 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
6688 struct ipr_resource_entry, queue);
6689 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
6690
6691 LEAVE;
6692 return IPR_RC_JOB_RETURN;
6693}
6694
6695
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd,
6707 __be32 res_handle,
6708 u8 parm, dma_addr_t dma_addr, u8 xfer_len)
6709{
6710 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6711
6712 ioarcb->res_handle = res_handle;
6713 ioarcb->cmd_pkt.cdb[0] = MODE_SENSE;
6714 ioarcb->cmd_pkt.cdb[2] = parm;
6715 ioarcb->cmd_pkt.cdb[4] = xfer_len;
6716 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
6717
6718 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
6719}
6720
6721
6722
6723
6724
6725
6726
6727
6728
6729
6730static int ipr_reset_cmd_failed(struct ipr_cmnd *ipr_cmd)
6731{
6732 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6733 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6734
6735 dev_err(&ioa_cfg->pdev->dev,
6736 "0x%02X failed with IOASC: 0x%08X\n",
6737 ipr_cmd->ioarcb.cmd_pkt.cdb[0], ioasc);
6738
6739 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
6740 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
6741 return IPR_RC_JOB_RETURN;
6742}
6743
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754static int ipr_reset_mode_sense_failed(struct ipr_cmnd *ipr_cmd)
6755{
6756 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6757 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6758
6759 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
6760 ipr_cmd->job_step = ipr_set_supported_devs;
6761 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
6762 struct ipr_resource_entry, queue);
6763 return IPR_RC_JOB_CONTINUE;
6764 }
6765
6766 return ipr_reset_cmd_failed(ipr_cmd);
6767}
6768
6769
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779static int ipr_ioafp_mode_sense_page28(struct ipr_cmnd *ipr_cmd)
6780{
6781 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6782
6783 ENTER;
6784 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
6785 0x28, ioa_cfg->vpd_cbs_dma +
6786 offsetof(struct ipr_misc_cbs, mode_pages),
6787 sizeof(struct ipr_mode_pages));
6788
6789 ipr_cmd->job_step = ipr_ioafp_mode_select_page28;
6790 ipr_cmd->job_step_failed = ipr_reset_mode_sense_failed;
6791
6792 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
6793
6794 LEAVE;
6795 return IPR_RC_JOB_RETURN;
6796}
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807static int ipr_ioafp_mode_select_page24(struct ipr_cmnd *ipr_cmd)
6808{
6809 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6810 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
6811 struct ipr_mode_page24 *mode_page;
6812 int length;
6813
6814 ENTER;
6815 mode_page = ipr_get_mode_page(mode_pages, 0x24,
6816 sizeof(struct ipr_mode_page24));
6817
6818 if (mode_page)
6819 mode_page->flags |= IPR_ENABLE_DUAL_IOA_AF;
6820
6821 length = mode_pages->hdr.length + 1;
6822 mode_pages->hdr.length = 0;
6823
6824 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
6825 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
6826 length);
6827
6828 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
6829 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
6830
6831 LEAVE;
6832 return IPR_RC_JOB_RETURN;
6833}
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845static int ipr_reset_mode_sense_page24_failed(struct ipr_cmnd *ipr_cmd)
6846{
6847 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6848
6849 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
6850 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
6851 return IPR_RC_JOB_CONTINUE;
6852 }
6853
6854 return ipr_reset_cmd_failed(ipr_cmd);
6855}
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867static int ipr_ioafp_mode_sense_page24(struct ipr_cmnd *ipr_cmd)
6868{
6869 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6870
6871 ENTER;
6872 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
6873 0x24, ioa_cfg->vpd_cbs_dma +
6874 offsetof(struct ipr_misc_cbs, mode_pages),
6875 sizeof(struct ipr_mode_pages));
6876
6877 ipr_cmd->job_step = ipr_ioafp_mode_select_page24;
6878 ipr_cmd->job_step_failed = ipr_reset_mode_sense_page24_failed;
6879
6880 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
6881
6882 LEAVE;
6883 return IPR_RC_JOB_RETURN;
6884}
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896
6897
6898static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd)
6899{
6900 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6901 struct ipr_resource_entry *res, *temp;
6902 struct ipr_config_table_entry_wrapper cfgtew;
6903 int entries, found, flag, i;
6904 LIST_HEAD(old_res);
6905
6906 ENTER;
6907 if (ioa_cfg->sis64)
6908 flag = ioa_cfg->u.cfg_table64->hdr64.flags;
6909 else
6910 flag = ioa_cfg->u.cfg_table->hdr.flags;
6911
6912 if (flag & IPR_UCODE_DOWNLOAD_REQ)
6913 dev_err(&ioa_cfg->pdev->dev, "Microcode download required\n");
6914
6915 list_for_each_entry_safe(res, temp, &ioa_cfg->used_res_q, queue)
6916 list_move_tail(&res->queue, &old_res);
6917
6918 if (ioa_cfg->sis64)
6919 entries = be16_to_cpu(ioa_cfg->u.cfg_table64->hdr64.num_entries);
6920 else
6921 entries = ioa_cfg->u.cfg_table->hdr.num_entries;
6922
6923 for (i = 0; i < entries; i++) {
6924 if (ioa_cfg->sis64)
6925 cfgtew.u.cfgte64 = &ioa_cfg->u.cfg_table64->dev[i];
6926 else
6927 cfgtew.u.cfgte = &ioa_cfg->u.cfg_table->dev[i];
6928 found = 0;
6929
6930 list_for_each_entry_safe(res, temp, &old_res, queue) {
6931 if (ipr_is_same_device(res, &cfgtew)) {
6932 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
6933 found = 1;
6934 break;
6935 }
6936 }
6937
6938 if (!found) {
6939 if (list_empty(&ioa_cfg->free_res_q)) {
6940 dev_err(&ioa_cfg->pdev->dev, "Too many devices attached\n");
6941 break;
6942 }
6943
6944 found = 1;
6945 res = list_entry(ioa_cfg->free_res_q.next,
6946 struct ipr_resource_entry, queue);
6947 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
6948 ipr_init_res_entry(res, &cfgtew);
6949 res->add_to_ml = 1;
6950 } else if (res->sdev && (ipr_is_vset_device(res) || ipr_is_scsi_disk(res)))
6951 res->sdev->allow_restart = 1;
6952
6953 if (found)
6954 ipr_update_res_entry(res, &cfgtew);
6955 }
6956
6957 list_for_each_entry_safe(res, temp, &old_res, queue) {
6958 if (res->sdev) {
6959 res->del_from_ml = 1;
6960 res->res_handle = IPR_INVALID_RES_HANDLE;
6961 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
6962 }
6963 }
6964
6965 list_for_each_entry_safe(res, temp, &old_res, queue) {
6966 ipr_clear_res_target(res);
6967 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
6968 }
6969
6970 if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
6971 ipr_cmd->job_step = ipr_ioafp_mode_sense_page24;
6972 else
6973 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
6974
6975 LEAVE;
6976 return IPR_RC_JOB_CONTINUE;
6977}
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd)
6990{
6991 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6992 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6993 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
6994 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
6995
6996 ENTER;
6997 if (cap->cap & IPR_CAP_DUAL_IOA_RAID)
6998 ioa_cfg->dual_raid = 1;
6999 dev_info(&ioa_cfg->pdev->dev, "Adapter firmware version: %02X%02X%02X%02X\n",
7000 ucode_vpd->major_release, ucode_vpd->card_type,
7001 ucode_vpd->minor_release[0], ucode_vpd->minor_release[1]);
7002 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7003 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7004
7005 ioarcb->cmd_pkt.cdb[0] = IPR_QUERY_IOA_CONFIG;
7006 ioarcb->cmd_pkt.cdb[6] = (ioa_cfg->cfg_table_size >> 16) & 0xff;
7007 ioarcb->cmd_pkt.cdb[7] = (ioa_cfg->cfg_table_size >> 8) & 0xff;
7008 ioarcb->cmd_pkt.cdb[8] = ioa_cfg->cfg_table_size & 0xff;
7009
7010 ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, ioa_cfg->cfg_table_size,
7011 IPR_IOADL_FLAGS_READ_LAST);
7012
7013 ipr_cmd->job_step = ipr_init_res_table;
7014
7015 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7016
7017 LEAVE;
7018 return IPR_RC_JOB_RETURN;
7019}
7020
7021
7022
7023
7024
7025
7026
7027
7028
7029
7030static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page,
7031 dma_addr_t dma_addr, u8 xfer_len)
7032{
7033 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7034
7035 ENTER;
7036 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7037 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7038
7039 ioarcb->cmd_pkt.cdb[0] = INQUIRY;
7040 ioarcb->cmd_pkt.cdb[1] = flags;
7041 ioarcb->cmd_pkt.cdb[2] = page;
7042 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7043
7044 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7045
7046 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7047 LEAVE;
7048}
7049
7050
7051
7052
7053
7054
7055
7056
7057
7058
7059
7060static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page)
7061{
7062 int i;
7063
7064 for (i = 0; i < min_t(u8, page0->len, IPR_INQUIRY_PAGE0_ENTRIES); i++)
7065 if (page0->page[i] == page)
7066 return 1;
7067
7068 return 0;
7069}
7070
7071
7072
7073
7074
7075
7076
7077
7078
7079
7080
7081static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd)
7082{
7083 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7084 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
7085 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7086
7087 ENTER;
7088 ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg;
7089 memset(cap, 0, sizeof(*cap));
7090
7091 if (ipr_inquiry_page_supported(page0, 0xD0)) {
7092 ipr_ioafp_inquiry(ipr_cmd, 1, 0xD0,
7093 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, cap),
7094 sizeof(struct ipr_inquiry_cap));
7095 return IPR_RC_JOB_RETURN;
7096 }
7097
7098 LEAVE;
7099 return IPR_RC_JOB_CONTINUE;
7100}
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112static int ipr_ioafp_page3_inquiry(struct ipr_cmnd *ipr_cmd)
7113{
7114 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7115
7116 ENTER;
7117
7118 ipr_cmd->job_step = ipr_ioafp_cap_inquiry;
7119
7120 ipr_ioafp_inquiry(ipr_cmd, 1, 3,
7121 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page3_data),
7122 sizeof(struct ipr_inquiry_page3));
7123
7124 LEAVE;
7125 return IPR_RC_JOB_RETURN;
7126}
7127
7128
7129
7130
7131
7132
7133
7134
7135
7136
7137
7138static int ipr_ioafp_page0_inquiry(struct ipr_cmnd *ipr_cmd)
7139{
7140 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7141 char type[5];
7142
7143 ENTER;
7144
7145
7146 memcpy(type, ioa_cfg->vpd_cbs->ioa_vpd.std_inq_data.vpids.product_id, 4);
7147 type[4] = '\0';
7148 ioa_cfg->type = simple_strtoul((char *)type, NULL, 16);
7149
7150 ipr_cmd->job_step = ipr_ioafp_page3_inquiry;
7151
7152 ipr_ioafp_inquiry(ipr_cmd, 1, 0,
7153 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page0_data),
7154 sizeof(struct ipr_inquiry_page0));
7155
7156 LEAVE;
7157 return IPR_RC_JOB_RETURN;
7158}
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
7170{
7171 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7172
7173 ENTER;
7174 ipr_cmd->job_step = ipr_ioafp_page0_inquiry;
7175
7176 ipr_ioafp_inquiry(ipr_cmd, 0, 0,
7177 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, ioa_vpd),
7178 sizeof(struct ipr_ioa_vpd));
7179
7180 LEAVE;
7181 return IPR_RC_JOB_RETURN;
7182}
7183
7184
7185
7186
7187
7188
7189
7190
7191
7192
7193
7194static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd)
7195{
7196 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7197 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7198
7199 ENTER;
7200 dev_info(&ioa_cfg->pdev->dev, "Starting IOA initialization sequence.\n");
7201
7202 ioarcb->cmd_pkt.cdb[0] = IPR_ID_HOST_RR_Q;
7203 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7204
7205 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7206 if (ioa_cfg->sis64)
7207 ioarcb->cmd_pkt.cdb[1] = 0x1;
7208 ioarcb->cmd_pkt.cdb[2] =
7209 ((u64) ioa_cfg->host_rrq_dma >> 24) & 0xff;
7210 ioarcb->cmd_pkt.cdb[3] =
7211 ((u64) ioa_cfg->host_rrq_dma >> 16) & 0xff;
7212 ioarcb->cmd_pkt.cdb[4] =
7213 ((u64) ioa_cfg->host_rrq_dma >> 8) & 0xff;
7214 ioarcb->cmd_pkt.cdb[5] =
7215 ((u64) ioa_cfg->host_rrq_dma) & 0xff;
7216 ioarcb->cmd_pkt.cdb[7] =
7217 ((sizeof(u32) * IPR_NUM_CMD_BLKS) >> 8) & 0xff;
7218 ioarcb->cmd_pkt.cdb[8] =
7219 (sizeof(u32) * IPR_NUM_CMD_BLKS) & 0xff;
7220
7221 if (ioa_cfg->sis64) {
7222 ioarcb->cmd_pkt.cdb[10] =
7223 ((u64) ioa_cfg->host_rrq_dma >> 56) & 0xff;
7224 ioarcb->cmd_pkt.cdb[11] =
7225 ((u64) ioa_cfg->host_rrq_dma >> 48) & 0xff;
7226 ioarcb->cmd_pkt.cdb[12] =
7227 ((u64) ioa_cfg->host_rrq_dma >> 40) & 0xff;
7228 ioarcb->cmd_pkt.cdb[13] =
7229 ((u64) ioa_cfg->host_rrq_dma >> 32) & 0xff;
7230 }
7231
7232 ipr_cmd->job_step = ipr_ioafp_std_inquiry;
7233
7234 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7235
7236 LEAVE;
7237 return IPR_RC_JOB_RETURN;
7238}
7239
7240
7241
7242
7243
7244
7245
7246
7247
7248
7249
7250
7251
7252
7253static void ipr_reset_timer_done(struct ipr_cmnd *ipr_cmd)
7254{
7255 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7256 unsigned long lock_flags = 0;
7257
7258 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
7259
7260 if (ioa_cfg->reset_cmd == ipr_cmd) {
7261 list_del(&ipr_cmd->queue);
7262 ipr_cmd->done(ipr_cmd);
7263 }
7264
7265 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
7266}
7267
7268
7269
7270
7271
7272
7273
7274
7275
7276
7277
7278
7279
7280
7281
7282static void ipr_reset_start_timer(struct ipr_cmnd *ipr_cmd,
7283 unsigned long timeout)
7284{
7285 list_add_tail(&ipr_cmd->queue, &ipr_cmd->ioa_cfg->pending_q);
7286 ipr_cmd->done = ipr_reset_ioa_job;
7287
7288 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7289 ipr_cmd->timer.expires = jiffies + timeout;
7290 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_reset_timer_done;
7291 add_timer(&ipr_cmd->timer);
7292}
7293
7294
7295
7296
7297
7298
7299
7300
7301static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg)
7302{
7303 memset(ioa_cfg->host_rrq, 0, sizeof(u32) * IPR_NUM_CMD_BLKS);
7304
7305
7306 ioa_cfg->hrrq_start = ioa_cfg->host_rrq;
7307 ioa_cfg->hrrq_end = &ioa_cfg->host_rrq[IPR_NUM_CMD_BLKS - 1];
7308 ioa_cfg->hrrq_curr = ioa_cfg->hrrq_start;
7309 ioa_cfg->toggle_bit = 1;
7310
7311
7312 memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size);
7313}
7314
7315
7316
7317
7318
7319
7320
7321
7322static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd)
7323{
7324 unsigned long stage, stage_time;
7325 u32 feedback;
7326 volatile u32 int_reg;
7327 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7328 u64 maskval = 0;
7329
7330 feedback = readl(ioa_cfg->regs.init_feedback_reg);
7331 stage = feedback & IPR_IPL_INIT_STAGE_MASK;
7332 stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK;
7333
7334 ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time);
7335
7336
7337 if (stage_time == 0)
7338 stage_time = IPR_IPL_INIT_DEFAULT_STAGE_TIME;
7339 else if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME)
7340 stage_time = IPR_IPL_INIT_MIN_STAGE_TIME;
7341 else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT)
7342 stage_time = IPR_LONG_OPERATIONAL_TIMEOUT;
7343
7344 if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) {
7345 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
7346 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7347 stage_time = ioa_cfg->transop_timeout;
7348 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7349 } else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) {
7350 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
7351 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
7352 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7353 maskval = IPR_PCII_IPL_STAGE_CHANGE;
7354 maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER;
7355 writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);
7356 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7357 return IPR_RC_JOB_CONTINUE;
7358 }
7359 }
7360
7361 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7362 ipr_cmd->timer.expires = jiffies + stage_time * HZ;
7363 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
7364 ipr_cmd->done = ipr_reset_ioa_job;
7365 add_timer(&ipr_cmd->timer);
7366 list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q);
7367
7368 return IPR_RC_JOB_RETURN;
7369}
7370
7371
7372
7373
7374
7375
7376
7377
7378
7379
7380
7381static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
7382{
7383 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7384 volatile u32 int_reg;
7385 volatile u64 maskval;
7386
7387 ENTER;
7388 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7389 ipr_init_ioa_mem(ioa_cfg);
7390
7391 ioa_cfg->allow_interrupts = 1;
7392 if (ioa_cfg->sis64) {
7393
7394 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
7395 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
7396 }
7397
7398 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
7399
7400 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
7401 writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
7402 ioa_cfg->regs.clr_interrupt_mask_reg32);
7403 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7404 return IPR_RC_JOB_CONTINUE;
7405 }
7406
7407
7408 writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
7409
7410 if (ioa_cfg->sis64) {
7411 maskval = IPR_PCII_IPL_STAGE_CHANGE;
7412 maskval = (maskval << 32) | IPR_PCII_OPER_INTERRUPTS;
7413 writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg);
7414 } else
7415 writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
7416
7417 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7418
7419 dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n");
7420
7421 if (ioa_cfg->sis64) {
7422 ipr_cmd->job_step = ipr_reset_next_stage;
7423 return IPR_RC_JOB_CONTINUE;
7424 }
7425
7426 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7427 ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ);
7428 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
7429 ipr_cmd->done = ipr_reset_ioa_job;
7430 add_timer(&ipr_cmd->timer);
7431 list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q);
7432
7433 LEAVE;
7434 return IPR_RC_JOB_RETURN;
7435}
7436
7437
7438
7439
7440
7441
7442
7443
7444
7445
7446
7447static int ipr_reset_wait_for_dump(struct ipr_cmnd *ipr_cmd)
7448{
7449 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7450
7451 if (ioa_cfg->sdt_state == GET_DUMP)
7452 ioa_cfg->sdt_state = ABORT_DUMP;
7453
7454 ipr_cmd->job_step = ipr_reset_alert;
7455
7456 return IPR_RC_JOB_CONTINUE;
7457}
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469static void ipr_unit_check_no_data(struct ipr_ioa_cfg *ioa_cfg)
7470{
7471 ioa_cfg->errors_logged++;
7472 dev_err(&ioa_cfg->pdev->dev, "IOA unit check with no data\n");
7473}
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg)
7486{
7487 unsigned long mailbox;
7488 struct ipr_hostrcb *hostrcb;
7489 struct ipr_uc_sdt sdt;
7490 int rc, length;
7491 u32 ioasc;
7492
7493 mailbox = readl(ioa_cfg->ioa_mailbox);
7494
7495 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(mailbox)) {
7496 ipr_unit_check_no_data(ioa_cfg);
7497 return;
7498 }
7499
7500 memset(&sdt, 0, sizeof(struct ipr_uc_sdt));
7501 rc = ipr_get_ldump_data_section(ioa_cfg, mailbox, (__be32 *) &sdt,
7502 (sizeof(struct ipr_uc_sdt)) / sizeof(__be32));
7503
7504 if (rc || !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY) ||
7505 ((be32_to_cpu(sdt.hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
7506 (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
7507 ipr_unit_check_no_data(ioa_cfg);
7508 return;
7509 }
7510
7511
7512 if (be32_to_cpu(sdt.hdr.state) == IPR_FMT3_SDT_READY_TO_USE)
7513 length = be32_to_cpu(sdt.entry[0].end_token);
7514 else
7515 length = (be32_to_cpu(sdt.entry[0].end_token) -
7516 be32_to_cpu(sdt.entry[0].start_token)) &
7517 IPR_FMT2_MBX_ADDR_MASK;
7518
7519 hostrcb = list_entry(ioa_cfg->hostrcb_free_q.next,
7520 struct ipr_hostrcb, queue);
7521 list_del(&hostrcb->queue);
7522 memset(&hostrcb->hcam, 0, sizeof(hostrcb->hcam));
7523
7524 rc = ipr_get_ldump_data_section(ioa_cfg,
7525 be32_to_cpu(sdt.entry[0].start_token),
7526 (__be32 *)&hostrcb->hcam,
7527 min(length, (int)sizeof(hostrcb->hcam)) / sizeof(__be32));
7528
7529 if (!rc) {
7530 ipr_handle_log_data(ioa_cfg, hostrcb);
7531 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
7532 if (ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED &&
7533 ioa_cfg->sdt_state == GET_DUMP)
7534 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
7535 } else
7536 ipr_unit_check_no_data(ioa_cfg);
7537
7538 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
7539}
7540
7541
7542
7543
7544
7545
7546
7547
7548
7549
7550static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd)
7551{
7552 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7553
7554 ENTER;
7555 ioa_cfg->ioa_unit_checked = 0;
7556 ipr_get_unit_check_buffer(ioa_cfg);
7557 ipr_cmd->job_step = ipr_reset_alert;
7558 ipr_reset_start_timer(ipr_cmd, 0);
7559
7560 LEAVE;
7561 return IPR_RC_JOB_RETURN;
7562}
7563
7564
7565
7566
7567
7568
7569
7570
7571
7572
7573
7574
7575static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
7576{
7577 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7578 u32 int_reg;
7579
7580 ENTER;
7581 ioa_cfg->pdev->state_saved = true;
7582 pci_restore_state(ioa_cfg->pdev);
7583
7584 if (ipr_set_pcix_cmd_reg(ioa_cfg)) {
7585 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
7586 return IPR_RC_JOB_CONTINUE;
7587 }
7588
7589 ipr_fail_all_ops(ioa_cfg);
7590
7591 if (ioa_cfg->sis64) {
7592
7593 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
7594 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
7595 }
7596
7597 if (ioa_cfg->ioa_unit_checked) {
7598 if (ioa_cfg->sis64) {
7599 ipr_cmd->job_step = ipr_reset_get_unit_check_job;
7600 ipr_reset_start_timer(ipr_cmd, IPR_DUMP_DELAY_TIMEOUT);
7601 return IPR_RC_JOB_RETURN;
7602 } else {
7603 ioa_cfg->ioa_unit_checked = 0;
7604 ipr_get_unit_check_buffer(ioa_cfg);
7605 ipr_cmd->job_step = ipr_reset_alert;
7606 ipr_reset_start_timer(ipr_cmd, 0);
7607 return IPR_RC_JOB_RETURN;
7608 }
7609 }
7610
7611 if (ioa_cfg->in_ioa_bringdown) {
7612 ipr_cmd->job_step = ipr_ioa_bringdown_done;
7613 } else {
7614 ipr_cmd->job_step = ipr_reset_enable_ioa;
7615
7616 if (GET_DUMP == ioa_cfg->sdt_state) {
7617 if (ioa_cfg->sis64)
7618 ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
7619 else
7620 ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
7621 ipr_cmd->job_step = ipr_reset_wait_for_dump;
7622 schedule_work(&ioa_cfg->work_q);
7623 return IPR_RC_JOB_RETURN;
7624 }
7625 }
7626
7627 LEAVE;
7628 return IPR_RC_JOB_CONTINUE;
7629}
7630
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640static int ipr_reset_bist_done(struct ipr_cmnd *ipr_cmd)
7641{
7642 ENTER;
7643 pci_unblock_user_cfg_access(ipr_cmd->ioa_cfg->pdev);
7644 ipr_cmd->job_step = ipr_reset_restore_cfg_space;
7645 LEAVE;
7646 return IPR_RC_JOB_CONTINUE;
7647}
7648
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658static int ipr_reset_start_bist(struct ipr_cmnd *ipr_cmd)
7659{
7660 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7661 int rc = PCIBIOS_SUCCESSFUL;
7662
7663 ENTER;
7664 pci_block_user_cfg_access(ioa_cfg->pdev);
7665
7666 if (ioa_cfg->ipr_chip->bist_method == IPR_MMIO)
7667 writel(IPR_UPROCI_SIS64_START_BIST,
7668 ioa_cfg->regs.set_uproc_interrupt_reg32);
7669 else
7670 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START);
7671
7672 if (rc == PCIBIOS_SUCCESSFUL) {
7673 ipr_cmd->job_step = ipr_reset_bist_done;
7674 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
7675 rc = IPR_RC_JOB_RETURN;
7676 } else {
7677 pci_unblock_user_cfg_access(ipr_cmd->ioa_cfg->pdev);
7678 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
7679 rc = IPR_RC_JOB_CONTINUE;
7680 }
7681
7682 LEAVE;
7683 return rc;
7684}
7685
7686
7687
7688
7689
7690
7691
7692
7693
7694
7695static int ipr_reset_slot_reset_done(struct ipr_cmnd *ipr_cmd)
7696{
7697 ENTER;
7698 pci_set_pcie_reset_state(ipr_cmd->ioa_cfg->pdev, pcie_deassert_reset);
7699 ipr_cmd->job_step = ipr_reset_bist_done;
7700 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
7701 LEAVE;
7702 return IPR_RC_JOB_RETURN;
7703}
7704
7705
7706
7707
7708
7709
7710
7711
7712
7713
7714static int ipr_reset_slot_reset(struct ipr_cmnd *ipr_cmd)
7715{
7716 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7717 struct pci_dev *pdev = ioa_cfg->pdev;
7718
7719 ENTER;
7720 pci_block_user_cfg_access(pdev);
7721 pci_set_pcie_reset_state(pdev, pcie_warm_reset);
7722 ipr_cmd->job_step = ipr_reset_slot_reset_done;
7723 ipr_reset_start_timer(ipr_cmd, IPR_PCI_RESET_TIMEOUT);
7724 LEAVE;
7725 return IPR_RC_JOB_RETURN;
7726}
7727
7728
7729
7730
7731
7732
7733
7734
7735static int ipr_reset_allowed(struct ipr_ioa_cfg *ioa_cfg)
7736{
7737 volatile u32 temp_reg;
7738
7739 temp_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
7740 return ((temp_reg & IPR_PCII_CRITICAL_OPERATION) == 0);
7741}
7742
7743
7744
7745
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756
7757
7758static int ipr_reset_wait_to_start_bist(struct ipr_cmnd *ipr_cmd)
7759{
7760 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7761 int rc = IPR_RC_JOB_RETURN;
7762
7763 if (!ipr_reset_allowed(ioa_cfg) && ipr_cmd->u.time_left) {
7764 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
7765 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
7766 } else {
7767 ipr_cmd->job_step = ioa_cfg->reset;
7768 rc = IPR_RC_JOB_CONTINUE;
7769 }
7770
7771 return rc;
7772}
7773
7774
7775
7776
7777
7778
7779
7780
7781
7782
7783
7784
7785
7786static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd)
7787{
7788 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7789 u16 cmd_reg;
7790 int rc;
7791
7792 ENTER;
7793 rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg);
7794
7795 if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
7796 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
7797 writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
7798 ipr_cmd->job_step = ipr_reset_wait_to_start_bist;
7799 } else {
7800 ipr_cmd->job_step = ioa_cfg->reset;
7801 }
7802
7803 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
7804 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
7805
7806 LEAVE;
7807 return IPR_RC_JOB_RETURN;
7808}
7809
7810
7811
7812
7813
7814
7815
7816
7817
7818
7819static int ipr_reset_ucode_download_done(struct ipr_cmnd *ipr_cmd)
7820{
7821 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7822 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
7823
7824 pci_unmap_sg(ioa_cfg->pdev, sglist->scatterlist,
7825 sglist->num_sg, DMA_TO_DEVICE);
7826
7827 ipr_cmd->job_step = ipr_reset_alert;
7828 return IPR_RC_JOB_CONTINUE;
7829}
7830
7831
7832
7833
7834
7835
7836
7837
7838
7839
7840
7841static int ipr_reset_ucode_download(struct ipr_cmnd *ipr_cmd)
7842{
7843 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7844 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
7845
7846 ENTER;
7847 ipr_cmd->job_step = ipr_reset_alert;
7848
7849 if (!sglist)
7850 return IPR_RC_JOB_CONTINUE;
7851
7852 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7853 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7854 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = WRITE_BUFFER;
7855 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_WR_BUF_DOWNLOAD_AND_SAVE;
7856 ipr_cmd->ioarcb.cmd_pkt.cdb[6] = (sglist->buffer_len & 0xff0000) >> 16;
7857 ipr_cmd->ioarcb.cmd_pkt.cdb[7] = (sglist->buffer_len & 0x00ff00) >> 8;
7858 ipr_cmd->ioarcb.cmd_pkt.cdb[8] = sglist->buffer_len & 0x0000ff;
7859
7860 if (ioa_cfg->sis64)
7861 ipr_build_ucode_ioadl64(ipr_cmd, sglist);
7862 else
7863 ipr_build_ucode_ioadl(ipr_cmd, sglist);
7864 ipr_cmd->job_step = ipr_reset_ucode_download_done;
7865
7866 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7867 IPR_WRITE_BUFFER_TIMEOUT);
7868
7869 LEAVE;
7870 return IPR_RC_JOB_RETURN;
7871}
7872
7873
7874
7875
7876
7877
7878
7879
7880
7881
7882
7883
7884static int ipr_reset_shutdown_ioa(struct ipr_cmnd *ipr_cmd)
7885{
7886 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7887 enum ipr_shutdown_type shutdown_type = ipr_cmd->u.shutdown_type;
7888 unsigned long timeout;
7889 int rc = IPR_RC_JOB_CONTINUE;
7890
7891 ENTER;
7892 if (shutdown_type != IPR_SHUTDOWN_NONE && !ioa_cfg->ioa_is_dead) {
7893 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7894 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7895 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
7896 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = shutdown_type;
7897
7898 if (shutdown_type == IPR_SHUTDOWN_NORMAL)
7899 timeout = IPR_SHUTDOWN_TIMEOUT;
7900 else if (shutdown_type == IPR_SHUTDOWN_PREPARE_FOR_NORMAL)
7901 timeout = IPR_INTERNAL_TIMEOUT;
7902 else if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
7903 timeout = IPR_DUAL_IOA_ABBR_SHUTDOWN_TO;
7904 else
7905 timeout = IPR_ABBREV_SHUTDOWN_TIMEOUT;
7906
7907 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, timeout);
7908
7909 rc = IPR_RC_JOB_RETURN;
7910 ipr_cmd->job_step = ipr_reset_ucode_download;
7911 } else
7912 ipr_cmd->job_step = ipr_reset_alert;
7913
7914 LEAVE;
7915 return rc;
7916}
7917
7918
7919
7920
7921
7922
7923
7924
7925
7926
7927static void ipr_reset_ioa_job(struct ipr_cmnd *ipr_cmd)
7928{
7929 u32 rc, ioasc;
7930 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7931
7932 do {
7933 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7934
7935 if (ioa_cfg->reset_cmd != ipr_cmd) {
7936
7937
7938
7939
7940 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
7941 return;
7942 }
7943
7944 if (IPR_IOASC_SENSE_KEY(ioasc)) {
7945 rc = ipr_cmd->job_step_failed(ipr_cmd);
7946 if (rc == IPR_RC_JOB_RETURN)
7947 return;
7948 }
7949
7950 ipr_reinit_ipr_cmnd(ipr_cmd);
7951 ipr_cmd->job_step_failed = ipr_reset_cmd_failed;
7952 rc = ipr_cmd->job_step(ipr_cmd);
7953 } while(rc == IPR_RC_JOB_CONTINUE);
7954}
7955
7956
7957
7958
7959
7960
7961
7962
7963
7964
7965
7966
7967
7968
7969
7970static void _ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
7971 int (*job_step) (struct ipr_cmnd *),
7972 enum ipr_shutdown_type shutdown_type)
7973{
7974 struct ipr_cmnd *ipr_cmd;
7975
7976 ioa_cfg->in_reset_reload = 1;
7977 ioa_cfg->allow_cmds = 0;
7978 scsi_block_requests(ioa_cfg->host);
7979
7980 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
7981 ioa_cfg->reset_cmd = ipr_cmd;
7982 ipr_cmd->job_step = job_step;
7983 ipr_cmd->u.shutdown_type = shutdown_type;
7984
7985 ipr_reset_ioa_job(ipr_cmd);
7986}
7987
7988
7989
7990
7991
7992
7993
7994
7995
7996
7997
7998
7999
8000static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
8001 enum ipr_shutdown_type shutdown_type)
8002{
8003 if (ioa_cfg->ioa_is_dead)
8004 return;
8005
8006 if (ioa_cfg->in_reset_reload && ioa_cfg->sdt_state == GET_DUMP)
8007 ioa_cfg->sdt_state = ABORT_DUMP;
8008
8009 if (ioa_cfg->reset_retries++ >= IPR_NUM_RESET_RELOAD_RETRIES) {
8010 dev_err(&ioa_cfg->pdev->dev,
8011 "IOA taken offline - error recovery failed\n");
8012
8013 ioa_cfg->reset_retries = 0;
8014 ioa_cfg->ioa_is_dead = 1;
8015
8016 if (ioa_cfg->in_ioa_bringdown) {
8017 ioa_cfg->reset_cmd = NULL;
8018 ioa_cfg->in_reset_reload = 0;
8019 ipr_fail_all_ops(ioa_cfg);
8020 wake_up_all(&ioa_cfg->reset_wait_q);
8021
8022 spin_unlock_irq(ioa_cfg->host->host_lock);
8023 scsi_unblock_requests(ioa_cfg->host);
8024 spin_lock_irq(ioa_cfg->host->host_lock);
8025 return;
8026 } else {
8027 ioa_cfg->in_ioa_bringdown = 1;
8028 shutdown_type = IPR_SHUTDOWN_NONE;
8029 }
8030 }
8031
8032 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_shutdown_ioa,
8033 shutdown_type);
8034}
8035
8036
8037
8038
8039
8040
8041
8042
8043
8044static int ipr_reset_freeze(struct ipr_cmnd *ipr_cmd)
8045{
8046
8047 ipr_cmd->ioa_cfg->allow_interrupts = 0;
8048 list_add_tail(&ipr_cmd->queue, &ipr_cmd->ioa_cfg->pending_q);
8049 ipr_cmd->done = ipr_reset_ioa_job;
8050 return IPR_RC_JOB_RETURN;
8051}
8052
8053
8054
8055
8056
8057
8058
8059
8060
8061static void ipr_pci_frozen(struct pci_dev *pdev)
8062{
8063 unsigned long flags = 0;
8064 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8065
8066 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8067 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_freeze, IPR_SHUTDOWN_NONE);
8068 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8069}
8070
8071
8072
8073
8074
8075
8076
8077
8078
8079static pci_ers_result_t ipr_pci_slot_reset(struct pci_dev *pdev)
8080{
8081 unsigned long flags = 0;
8082 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8083
8084 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8085 if (ioa_cfg->needs_warm_reset)
8086 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8087 else
8088 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_restore_cfg_space,
8089 IPR_SHUTDOWN_NONE);
8090 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8091 return PCI_ERS_RESULT_RECOVERED;
8092}
8093
8094
8095
8096
8097
8098
8099
8100
8101static void ipr_pci_perm_failure(struct pci_dev *pdev)
8102{
8103 unsigned long flags = 0;
8104 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8105
8106 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8107 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
8108 ioa_cfg->sdt_state = ABORT_DUMP;
8109 ioa_cfg->reset_retries = IPR_NUM_RESET_RELOAD_RETRIES;
8110 ioa_cfg->in_ioa_bringdown = 1;
8111 ioa_cfg->allow_cmds = 0;
8112 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8113 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8114}
8115
8116
8117
8118
8119
8120
8121
8122
8123
8124
8125
8126static pci_ers_result_t ipr_pci_error_detected(struct pci_dev *pdev,
8127 pci_channel_state_t state)
8128{
8129 switch (state) {
8130 case pci_channel_io_frozen:
8131 ipr_pci_frozen(pdev);
8132 return PCI_ERS_RESULT_NEED_RESET;
8133 case pci_channel_io_perm_failure:
8134 ipr_pci_perm_failure(pdev);
8135 return PCI_ERS_RESULT_DISCONNECT;
8136 break;
8137 default:
8138 break;
8139 }
8140 return PCI_ERS_RESULT_NEED_RESET;
8141}
8142
8143
8144
8145
8146
8147
8148
8149
8150
8151
8152
8153
8154static int __devinit ipr_probe_ioa_part2(struct ipr_ioa_cfg *ioa_cfg)
8155{
8156 int rc = 0;
8157 unsigned long host_lock_flags = 0;
8158
8159 ENTER;
8160 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8161 dev_dbg(&ioa_cfg->pdev->dev, "ioa_cfg adx: 0x%p\n", ioa_cfg);
8162 if (ioa_cfg->needs_hard_reset) {
8163 ioa_cfg->needs_hard_reset = 0;
8164 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8165 } else
8166 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_enable_ioa,
8167 IPR_SHUTDOWN_NONE);
8168
8169 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8170 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
8171 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8172
8173 if (ioa_cfg->ioa_is_dead) {
8174 rc = -EIO;
8175 } else if (ipr_invalid_adapter(ioa_cfg)) {
8176 if (!ipr_testmode)
8177 rc = -EIO;
8178
8179 dev_err(&ioa_cfg->pdev->dev,
8180 "Adapter not supported in this hardware configuration.\n");
8181 }
8182
8183 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8184
8185 LEAVE;
8186 return rc;
8187}
8188
8189
8190
8191
8192
8193
8194
8195
8196static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
8197{
8198 int i;
8199
8200 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
8201 if (ioa_cfg->ipr_cmnd_list[i])
8202 pci_pool_free(ioa_cfg->ipr_cmd_pool,
8203 ioa_cfg->ipr_cmnd_list[i],
8204 ioa_cfg->ipr_cmnd_list_dma[i]);
8205
8206 ioa_cfg->ipr_cmnd_list[i] = NULL;
8207 }
8208
8209 if (ioa_cfg->ipr_cmd_pool)
8210 pci_pool_destroy (ioa_cfg->ipr_cmd_pool);
8211
8212 ioa_cfg->ipr_cmd_pool = NULL;
8213}
8214
8215
8216
8217
8218
8219
8220
8221
8222static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
8223{
8224 int i;
8225
8226 kfree(ioa_cfg->res_entries);
8227 pci_free_consistent(ioa_cfg->pdev, sizeof(struct ipr_misc_cbs),
8228 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
8229 ipr_free_cmd_blks(ioa_cfg);
8230 pci_free_consistent(ioa_cfg->pdev, sizeof(u32) * IPR_NUM_CMD_BLKS,
8231 ioa_cfg->host_rrq, ioa_cfg->host_rrq_dma);
8232 pci_free_consistent(ioa_cfg->pdev, ioa_cfg->cfg_table_size,
8233 ioa_cfg->u.cfg_table,
8234 ioa_cfg->cfg_table_dma);
8235
8236 for (i = 0; i < IPR_NUM_HCAMS; i++) {
8237 pci_free_consistent(ioa_cfg->pdev,
8238 sizeof(struct ipr_hostrcb),
8239 ioa_cfg->hostrcb[i],
8240 ioa_cfg->hostrcb_dma[i]);
8241 }
8242
8243 ipr_free_dump(ioa_cfg);
8244 kfree(ioa_cfg->trace);
8245}
8246
8247
8248
8249
8250
8251
8252
8253
8254
8255
8256
8257static void ipr_free_all_resources(struct ipr_ioa_cfg *ioa_cfg)
8258{
8259 struct pci_dev *pdev = ioa_cfg->pdev;
8260
8261 ENTER;
8262 free_irq(pdev->irq, ioa_cfg);
8263 pci_disable_msi(pdev);
8264 iounmap(ioa_cfg->hdw_dma_regs);
8265 pci_release_regions(pdev);
8266 ipr_free_mem(ioa_cfg);
8267 scsi_host_put(ioa_cfg->host);
8268 pci_disable_device(pdev);
8269 LEAVE;
8270}
8271
8272
8273
8274
8275
8276
8277
8278
8279static int __devinit ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
8280{
8281 struct ipr_cmnd *ipr_cmd;
8282 struct ipr_ioarcb *ioarcb;
8283 dma_addr_t dma_addr;
8284 int i;
8285
8286 ioa_cfg->ipr_cmd_pool = pci_pool_create (IPR_NAME, ioa_cfg->pdev,
8287 sizeof(struct ipr_cmnd), 16, 0);
8288
8289 if (!ioa_cfg->ipr_cmd_pool)
8290 return -ENOMEM;
8291
8292 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
8293 ipr_cmd = pci_pool_alloc (ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr);
8294
8295 if (!ipr_cmd) {
8296 ipr_free_cmd_blks(ioa_cfg);
8297 return -ENOMEM;
8298 }
8299
8300 memset(ipr_cmd, 0, sizeof(*ipr_cmd));
8301 ioa_cfg->ipr_cmnd_list[i] = ipr_cmd;
8302 ioa_cfg->ipr_cmnd_list_dma[i] = dma_addr;
8303
8304 ioarcb = &ipr_cmd->ioarcb;
8305 ipr_cmd->dma_addr = dma_addr;
8306 if (ioa_cfg->sis64)
8307 ioarcb->a.ioarcb_host_pci_addr64 = cpu_to_be64(dma_addr);
8308 else
8309 ioarcb->a.ioarcb_host_pci_addr = cpu_to_be32(dma_addr);
8310
8311 ioarcb->host_response_handle = cpu_to_be32(i << 2);
8312 if (ioa_cfg->sis64) {
8313 ioarcb->u.sis64_addr_data.data_ioadl_addr =
8314 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
8315 ioarcb->u.sis64_addr_data.ioasa_host_pci_addr =
8316 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, s.ioasa64));
8317 } else {
8318 ioarcb->write_ioadl_addr =
8319 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
8320 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
8321 ioarcb->ioasa_host_pci_addr =
8322 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, s.ioasa));
8323 }
8324 ioarcb->ioasa_len = cpu_to_be16(sizeof(struct ipr_ioasa));
8325 ipr_cmd->cmd_index = i;
8326 ipr_cmd->ioa_cfg = ioa_cfg;
8327 ipr_cmd->sense_buffer_dma = dma_addr +
8328 offsetof(struct ipr_cmnd, sense_buffer);
8329
8330 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
8331 }
8332
8333 return 0;
8334}
8335
8336
8337
8338
8339
8340
8341
8342
8343static int __devinit ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
8344{
8345 struct pci_dev *pdev = ioa_cfg->pdev;
8346 int i, rc = -ENOMEM;
8347
8348 ENTER;
8349 ioa_cfg->res_entries = kzalloc(sizeof(struct ipr_resource_entry) *
8350 ioa_cfg->max_devs_supported, GFP_KERNEL);
8351
8352 if (!ioa_cfg->res_entries)
8353 goto out;
8354
8355 if (ioa_cfg->sis64) {
8356 ioa_cfg->target_ids = kzalloc(sizeof(unsigned long) *
8357 BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL);
8358 ioa_cfg->array_ids = kzalloc(sizeof(unsigned long) *
8359 BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL);
8360 ioa_cfg->vset_ids = kzalloc(sizeof(unsigned long) *
8361 BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL);
8362 }
8363
8364 for (i = 0; i < ioa_cfg->max_devs_supported; i++) {
8365 list_add_tail(&ioa_cfg->res_entries[i].queue, &ioa_cfg->free_res_q);
8366 ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg;
8367 }
8368
8369 ioa_cfg->vpd_cbs = pci_alloc_consistent(ioa_cfg->pdev,
8370 sizeof(struct ipr_misc_cbs),
8371 &ioa_cfg->vpd_cbs_dma);
8372
8373 if (!ioa_cfg->vpd_cbs)
8374 goto out_free_res_entries;
8375
8376 if (ipr_alloc_cmd_blks(ioa_cfg))
8377 goto out_free_vpd_cbs;
8378
8379 ioa_cfg->host_rrq = pci_alloc_consistent(ioa_cfg->pdev,
8380 sizeof(u32) * IPR_NUM_CMD_BLKS,
8381 &ioa_cfg->host_rrq_dma);
8382
8383 if (!ioa_cfg->host_rrq)
8384 goto out_ipr_free_cmd_blocks;
8385
8386 ioa_cfg->u.cfg_table = pci_alloc_consistent(ioa_cfg->pdev,
8387 ioa_cfg->cfg_table_size,
8388 &ioa_cfg->cfg_table_dma);
8389
8390 if (!ioa_cfg->u.cfg_table)
8391 goto out_free_host_rrq;
8392
8393 for (i = 0; i < IPR_NUM_HCAMS; i++) {
8394 ioa_cfg->hostrcb[i] = pci_alloc_consistent(ioa_cfg->pdev,
8395 sizeof(struct ipr_hostrcb),
8396 &ioa_cfg->hostrcb_dma[i]);
8397
8398 if (!ioa_cfg->hostrcb[i])
8399 goto out_free_hostrcb_dma;
8400
8401 ioa_cfg->hostrcb[i]->hostrcb_dma =
8402 ioa_cfg->hostrcb_dma[i] + offsetof(struct ipr_hostrcb, hcam);
8403 ioa_cfg->hostrcb[i]->ioa_cfg = ioa_cfg;
8404 list_add_tail(&ioa_cfg->hostrcb[i]->queue, &ioa_cfg->hostrcb_free_q);
8405 }
8406
8407 ioa_cfg->trace = kzalloc(sizeof(struct ipr_trace_entry) *
8408 IPR_NUM_TRACE_ENTRIES, GFP_KERNEL);
8409
8410 if (!ioa_cfg->trace)
8411 goto out_free_hostrcb_dma;
8412
8413 rc = 0;
8414out:
8415 LEAVE;
8416 return rc;
8417
8418out_free_hostrcb_dma:
8419 while (i-- > 0) {
8420 pci_free_consistent(pdev, sizeof(struct ipr_hostrcb),
8421 ioa_cfg->hostrcb[i],
8422 ioa_cfg->hostrcb_dma[i]);
8423 }
8424 pci_free_consistent(pdev, ioa_cfg->cfg_table_size,
8425 ioa_cfg->u.cfg_table,
8426 ioa_cfg->cfg_table_dma);
8427out_free_host_rrq:
8428 pci_free_consistent(pdev, sizeof(u32) * IPR_NUM_CMD_BLKS,
8429 ioa_cfg->host_rrq, ioa_cfg->host_rrq_dma);
8430out_ipr_free_cmd_blocks:
8431 ipr_free_cmd_blks(ioa_cfg);
8432out_free_vpd_cbs:
8433 pci_free_consistent(pdev, sizeof(struct ipr_misc_cbs),
8434 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
8435out_free_res_entries:
8436 kfree(ioa_cfg->res_entries);
8437 goto out;
8438}
8439
8440
8441
8442
8443
8444
8445
8446
8447static void __devinit ipr_initialize_bus_attr(struct ipr_ioa_cfg *ioa_cfg)
8448{
8449 int i;
8450
8451 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
8452 ioa_cfg->bus_attr[i].bus = i;
8453 ioa_cfg->bus_attr[i].qas_enabled = 0;
8454 ioa_cfg->bus_attr[i].bus_width = IPR_DEFAULT_BUS_WIDTH;
8455 if (ipr_max_speed < ARRAY_SIZE(ipr_max_bus_speeds))
8456 ioa_cfg->bus_attr[i].max_xfer_rate = ipr_max_bus_speeds[ipr_max_speed];
8457 else
8458 ioa_cfg->bus_attr[i].max_xfer_rate = IPR_U160_SCSI_RATE;
8459 }
8460}
8461
8462
8463
8464
8465
8466
8467
8468
8469
8470
8471static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
8472 struct Scsi_Host *host, struct pci_dev *pdev)
8473{
8474 const struct ipr_interrupt_offsets *p;
8475 struct ipr_interrupts *t;
8476 void __iomem *base;
8477
8478 ioa_cfg->host = host;
8479 ioa_cfg->pdev = pdev;
8480 ioa_cfg->log_level = ipr_log_level;
8481 ioa_cfg->doorbell = IPR_DOORBELL;
8482 sprintf(ioa_cfg->eye_catcher, IPR_EYECATCHER);
8483 sprintf(ioa_cfg->trace_start, IPR_TRACE_START_LABEL);
8484 sprintf(ioa_cfg->ipr_free_label, IPR_FREEQ_LABEL);
8485 sprintf(ioa_cfg->ipr_pending_label, IPR_PENDQ_LABEL);
8486 sprintf(ioa_cfg->cfg_table_start, IPR_CFG_TBL_START);
8487 sprintf(ioa_cfg->resource_table_label, IPR_RES_TABLE_LABEL);
8488 sprintf(ioa_cfg->ipr_hcam_label, IPR_HCAM_LABEL);
8489 sprintf(ioa_cfg->ipr_cmd_label, IPR_CMD_LABEL);
8490
8491 INIT_LIST_HEAD(&ioa_cfg->free_q);
8492 INIT_LIST_HEAD(&ioa_cfg->pending_q);
8493 INIT_LIST_HEAD(&ioa_cfg->hostrcb_free_q);
8494 INIT_LIST_HEAD(&ioa_cfg->hostrcb_pending_q);
8495 INIT_LIST_HEAD(&ioa_cfg->free_res_q);
8496 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
8497 INIT_WORK(&ioa_cfg->work_q, ipr_worker_thread);
8498 init_waitqueue_head(&ioa_cfg->reset_wait_q);
8499 init_waitqueue_head(&ioa_cfg->msi_wait_q);
8500 ioa_cfg->sdt_state = INACTIVE;
8501
8502 ipr_initialize_bus_attr(ioa_cfg);
8503 ioa_cfg->max_devs_supported = ipr_max_devs;
8504
8505 if (ioa_cfg->sis64) {
8506 host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS;
8507 host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET;
8508 if (ipr_max_devs > IPR_MAX_SIS64_DEVS)
8509 ioa_cfg->max_devs_supported = IPR_MAX_SIS64_DEVS;
8510 } else {
8511 host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS;
8512 host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET;
8513 if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS)
8514 ioa_cfg->max_devs_supported = IPR_MAX_PHYSICAL_DEVS;
8515 }
8516 host->max_channel = IPR_MAX_BUS_TO_SCAN;
8517 host->unique_id = host->host_no;
8518 host->max_cmd_len = IPR_MAX_CDB_LEN;
8519 pci_set_drvdata(pdev, ioa_cfg);
8520
8521 p = &ioa_cfg->chip_cfg->regs;
8522 t = &ioa_cfg->regs;
8523 base = ioa_cfg->hdw_dma_regs;
8524
8525 t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg;
8526 t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg;
8527 t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32;
8528 t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg;
8529 t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32;
8530 t->clr_interrupt_reg = base + p->clr_interrupt_reg;
8531 t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32;
8532 t->sense_interrupt_reg = base + p->sense_interrupt_reg;
8533 t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32;
8534 t->ioarrin_reg = base + p->ioarrin_reg;
8535 t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg;
8536 t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32;
8537 t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg;
8538 t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32;
8539 t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg;
8540 t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32;
8541
8542 if (ioa_cfg->sis64) {
8543 t->init_feedback_reg = base + p->init_feedback_reg;
8544 t->dump_addr_reg = base + p->dump_addr_reg;
8545 t->dump_data_reg = base + p->dump_data_reg;
8546 t->endian_swap_reg = base + p->endian_swap_reg;
8547 }
8548}
8549
8550
8551
8552
8553
8554
8555
8556
8557static const struct ipr_chip_t * __devinit
8558ipr_get_chip_info(const struct pci_device_id *dev_id)
8559{
8560 int i;
8561
8562 for (i = 0; i < ARRAY_SIZE(ipr_chip); i++)
8563 if (ipr_chip[i].vendor == dev_id->vendor &&
8564 ipr_chip[i].device == dev_id->device)
8565 return &ipr_chip[i];
8566 return NULL;
8567}
8568
8569
8570
8571
8572
8573
8574
8575
8576
8577
8578
8579static irqreturn_t __devinit ipr_test_intr(int irq, void *devp)
8580{
8581 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
8582 unsigned long lock_flags = 0;
8583 irqreturn_t rc = IRQ_HANDLED;
8584
8585 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8586
8587 ioa_cfg->msi_received = 1;
8588 wake_up(&ioa_cfg->msi_wait_q);
8589
8590 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8591 return rc;
8592}
8593
8594
8595
8596
8597
8598
8599
8600
8601
8602
8603
8604
8605
8606static int __devinit ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg,
8607 struct pci_dev *pdev)
8608{
8609 int rc;
8610 volatile u32 int_reg;
8611 unsigned long lock_flags = 0;
8612
8613 ENTER;
8614
8615 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8616 init_waitqueue_head(&ioa_cfg->msi_wait_q);
8617 ioa_cfg->msi_received = 0;
8618 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
8619 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
8620 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8621 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8622
8623 rc = request_irq(pdev->irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
8624 if (rc) {
8625 dev_err(&pdev->dev, "Can not assign irq %d\n", pdev->irq);
8626 return rc;
8627 } else if (ipr_debug)
8628 dev_info(&pdev->dev, "IRQ assigned: %d\n", pdev->irq);
8629
8630 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
8631 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
8632 wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ);
8633 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
8634
8635 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8636 if (!ioa_cfg->msi_received) {
8637
8638 dev_info(&pdev->dev, "MSI test failed. Falling back to LSI.\n");
8639 rc = -EOPNOTSUPP;
8640 } else if (ipr_debug)
8641 dev_info(&pdev->dev, "MSI test succeeded.\n");
8642
8643 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8644
8645 free_irq(pdev->irq, ioa_cfg);
8646
8647 LEAVE;
8648
8649 return rc;
8650}
8651
8652
8653
8654
8655
8656
8657
8658
8659
8660static int __devinit ipr_probe_ioa(struct pci_dev *pdev,
8661 const struct pci_device_id *dev_id)
8662{
8663 struct ipr_ioa_cfg *ioa_cfg;
8664 struct Scsi_Host *host;
8665 unsigned long ipr_regs_pci;
8666 void __iomem *ipr_regs;
8667 int rc = PCIBIOS_SUCCESSFUL;
8668 volatile u32 mask, uproc, interrupts;
8669
8670 ENTER;
8671
8672 if ((rc = pci_enable_device(pdev))) {
8673 dev_err(&pdev->dev, "Cannot enable adapter\n");
8674 goto out;
8675 }
8676
8677 dev_info(&pdev->dev, "Found IOA with IRQ: %d\n", pdev->irq);
8678
8679 host = scsi_host_alloc(&driver_template, sizeof(*ioa_cfg));
8680
8681 if (!host) {
8682 dev_err(&pdev->dev, "call to scsi_host_alloc failed!\n");
8683 rc = -ENOMEM;
8684 goto out_disable;
8685 }
8686
8687 ioa_cfg = (struct ipr_ioa_cfg *)host->hostdata;
8688 memset(ioa_cfg, 0, sizeof(struct ipr_ioa_cfg));
8689 ata_host_init(&ioa_cfg->ata_host, &pdev->dev,
8690 sata_port_info.flags, &ipr_sata_ops);
8691
8692 ioa_cfg->ipr_chip = ipr_get_chip_info(dev_id);
8693
8694 if (!ioa_cfg->ipr_chip) {
8695 dev_err(&pdev->dev, "Unknown adapter chipset 0x%04X 0x%04X\n",
8696 dev_id->vendor, dev_id->device);
8697 goto out_scsi_host_put;
8698 }
8699
8700
8701 ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
8702 ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
8703
8704 if (ipr_transop_timeout)
8705 ioa_cfg->transop_timeout = ipr_transop_timeout;
8706 else if (dev_id->driver_data & IPR_USE_LONG_TRANSOP_TIMEOUT)
8707 ioa_cfg->transop_timeout = IPR_LONG_OPERATIONAL_TIMEOUT;
8708 else
8709 ioa_cfg->transop_timeout = IPR_OPERATIONAL_TIMEOUT;
8710
8711 ioa_cfg->revid = pdev->revision;
8712
8713 ipr_regs_pci = pci_resource_start(pdev, 0);
8714
8715 rc = pci_request_regions(pdev, IPR_NAME);
8716 if (rc < 0) {
8717 dev_err(&pdev->dev,
8718 "Couldn't register memory range of registers\n");
8719 goto out_scsi_host_put;
8720 }
8721
8722 ipr_regs = pci_ioremap_bar(pdev, 0);
8723
8724 if (!ipr_regs) {
8725 dev_err(&pdev->dev,
8726 "Couldn't map memory range of registers\n");
8727 rc = -ENOMEM;
8728 goto out_release_regions;
8729 }
8730
8731 ioa_cfg->hdw_dma_regs = ipr_regs;
8732 ioa_cfg->hdw_dma_regs_pci = ipr_regs_pci;
8733 ioa_cfg->ioa_mailbox = ioa_cfg->chip_cfg->mailbox + ipr_regs;
8734
8735 ipr_init_ioa_cfg(ioa_cfg, host, pdev);
8736
8737 pci_set_master(pdev);
8738
8739 if (ioa_cfg->sis64) {
8740 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8741 if (rc < 0) {
8742 dev_dbg(&pdev->dev, "Failed to set 64 bit PCI DMA mask\n");
8743 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8744 }
8745
8746 } else
8747 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8748
8749 if (rc < 0) {
8750 dev_err(&pdev->dev, "Failed to set PCI DMA mask\n");
8751 goto cleanup_nomem;
8752 }
8753
8754 rc = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
8755 ioa_cfg->chip_cfg->cache_line_size);
8756
8757 if (rc != PCIBIOS_SUCCESSFUL) {
8758 dev_err(&pdev->dev, "Write of cache line size failed\n");
8759 rc = -EIO;
8760 goto cleanup_nomem;
8761 }
8762
8763
8764 if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI && !pci_enable_msi(pdev)) {
8765 rc = ipr_test_msi(ioa_cfg, pdev);
8766 if (rc == -EOPNOTSUPP)
8767 pci_disable_msi(pdev);
8768 else if (rc)
8769 goto out_msi_disable;
8770 else
8771 dev_info(&pdev->dev, "MSI enabled with IRQ: %d\n", pdev->irq);
8772 } else if (ipr_debug)
8773 dev_info(&pdev->dev, "Cannot enable MSI.\n");
8774
8775
8776 rc = pci_save_state(pdev);
8777
8778 if (rc != PCIBIOS_SUCCESSFUL) {
8779 dev_err(&pdev->dev, "Failed to save PCI config space\n");
8780 rc = -EIO;
8781 goto out_msi_disable;
8782 }
8783
8784 if ((rc = ipr_save_pcix_cmd_reg(ioa_cfg)))
8785 goto out_msi_disable;
8786
8787 if ((rc = ipr_set_pcix_cmd_reg(ioa_cfg)))
8788 goto out_msi_disable;
8789
8790 if (ioa_cfg->sis64)
8791 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr64)
8792 + ((sizeof(struct ipr_config_table_entry64)
8793 * ioa_cfg->max_devs_supported)));
8794 else
8795 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr)
8796 + ((sizeof(struct ipr_config_table_entry)
8797 * ioa_cfg->max_devs_supported)));
8798
8799 rc = ipr_alloc_mem(ioa_cfg);
8800 if (rc < 0) {
8801 dev_err(&pdev->dev,
8802 "Couldn't allocate enough memory for device driver!\n");
8803 goto out_msi_disable;
8804 }
8805
8806
8807
8808
8809
8810 mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
8811 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32);
8812 uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
8813 if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT))
8814 ioa_cfg->needs_hard_reset = 1;
8815 if (interrupts & IPR_PCII_ERROR_INTERRUPTS)
8816 ioa_cfg->needs_hard_reset = 1;
8817 if (interrupts & IPR_PCII_IOA_UNIT_CHECKED)
8818 ioa_cfg->ioa_unit_checked = 1;
8819
8820 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
8821 rc = request_irq(pdev->irq, ipr_isr,
8822 ioa_cfg->msi_received ? 0 : IRQF_SHARED,
8823 IPR_NAME, ioa_cfg);
8824
8825 if (rc) {
8826 dev_err(&pdev->dev, "Couldn't register IRQ %d! rc=%d\n",
8827 pdev->irq, rc);
8828 goto cleanup_nolog;
8829 }
8830
8831 if ((dev_id->driver_data & IPR_USE_PCI_WARM_RESET) ||
8832 (dev_id->device == PCI_DEVICE_ID_IBM_OBSIDIAN_E && !ioa_cfg->revid)) {
8833 ioa_cfg->needs_warm_reset = 1;
8834 ioa_cfg->reset = ipr_reset_slot_reset;
8835 } else
8836 ioa_cfg->reset = ipr_reset_start_bist;
8837
8838 spin_lock(&ipr_driver_lock);
8839 list_add_tail(&ioa_cfg->queue, &ipr_ioa_head);
8840 spin_unlock(&ipr_driver_lock);
8841
8842 LEAVE;
8843out:
8844 return rc;
8845
8846cleanup_nolog:
8847 ipr_free_mem(ioa_cfg);
8848out_msi_disable:
8849 pci_disable_msi(pdev);
8850cleanup_nomem:
8851 iounmap(ipr_regs);
8852out_release_regions:
8853 pci_release_regions(pdev);
8854out_scsi_host_put:
8855 scsi_host_put(host);
8856out_disable:
8857 pci_disable_device(pdev);
8858 goto out;
8859}
8860
8861
8862
8863
8864
8865
8866
8867
8868
8869
8870
8871static void ipr_scan_vsets(struct ipr_ioa_cfg *ioa_cfg)
8872{
8873 int target, lun;
8874
8875 for (target = 0; target < IPR_MAX_NUM_TARGETS_PER_BUS; target++)
8876 for (lun = 0; lun < IPR_MAX_NUM_VSET_LUNS_PER_TARGET; lun++ )
8877 scsi_add_device(ioa_cfg->host, IPR_VSET_BUS, target, lun);
8878}
8879
8880
8881
8882
8883
8884
8885
8886
8887
8888
8889
8890
8891
8892
8893
8894static void ipr_initiate_ioa_bringdown(struct ipr_ioa_cfg *ioa_cfg,
8895 enum ipr_shutdown_type shutdown_type)
8896{
8897 ENTER;
8898 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
8899 ioa_cfg->sdt_state = ABORT_DUMP;
8900 ioa_cfg->reset_retries = 0;
8901 ioa_cfg->in_ioa_bringdown = 1;
8902 ipr_initiate_ioa_reset(ioa_cfg, shutdown_type);
8903 LEAVE;
8904}
8905
8906
8907
8908
8909
8910
8911
8912
8913
8914
8915static void __ipr_remove(struct pci_dev *pdev)
8916{
8917 unsigned long host_lock_flags = 0;
8918 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8919 ENTER;
8920
8921 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8922 while(ioa_cfg->in_reset_reload) {
8923 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8924 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
8925 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8926 }
8927
8928 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
8929
8930 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8931 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
8932 flush_work_sync(&ioa_cfg->work_q);
8933 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8934
8935 spin_lock(&ipr_driver_lock);
8936 list_del(&ioa_cfg->queue);
8937 spin_unlock(&ipr_driver_lock);
8938
8939 if (ioa_cfg->sdt_state == ABORT_DUMP)
8940 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8941 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8942
8943 ipr_free_all_resources(ioa_cfg);
8944
8945 LEAVE;
8946}
8947
8948
8949
8950
8951
8952
8953
8954
8955
8956
8957static void __devexit ipr_remove(struct pci_dev *pdev)
8958{
8959 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8960
8961 ENTER;
8962
8963 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
8964 &ipr_trace_attr);
8965 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
8966 &ipr_dump_attr);
8967 scsi_remove_host(ioa_cfg->host);
8968
8969 __ipr_remove(pdev);
8970
8971 LEAVE;
8972}
8973
8974
8975
8976
8977
8978
8979
8980static int __devinit ipr_probe(struct pci_dev *pdev,
8981 const struct pci_device_id *dev_id)
8982{
8983 struct ipr_ioa_cfg *ioa_cfg;
8984 int rc;
8985
8986 rc = ipr_probe_ioa(pdev, dev_id);
8987
8988 if (rc)
8989 return rc;
8990
8991 ioa_cfg = pci_get_drvdata(pdev);
8992 rc = ipr_probe_ioa_part2(ioa_cfg);
8993
8994 if (rc) {
8995 __ipr_remove(pdev);
8996 return rc;
8997 }
8998
8999 rc = scsi_add_host(ioa_cfg->host, &pdev->dev);
9000
9001 if (rc) {
9002 __ipr_remove(pdev);
9003 return rc;
9004 }
9005
9006 rc = ipr_create_trace_file(&ioa_cfg->host->shost_dev.kobj,
9007 &ipr_trace_attr);
9008
9009 if (rc) {
9010 scsi_remove_host(ioa_cfg->host);
9011 __ipr_remove(pdev);
9012 return rc;
9013 }
9014
9015 rc = ipr_create_dump_file(&ioa_cfg->host->shost_dev.kobj,
9016 &ipr_dump_attr);
9017
9018 if (rc) {
9019 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
9020 &ipr_trace_attr);
9021 scsi_remove_host(ioa_cfg->host);
9022 __ipr_remove(pdev);
9023 return rc;
9024 }
9025
9026 scsi_scan_host(ioa_cfg->host);
9027 ipr_scan_vsets(ioa_cfg);
9028 scsi_add_device(ioa_cfg->host, IPR_IOA_BUS, IPR_IOA_TARGET, IPR_IOA_LUN);
9029 ioa_cfg->allow_ml_add_del = 1;
9030 ioa_cfg->host->max_channel = IPR_VSET_BUS;
9031 schedule_work(&ioa_cfg->work_q);
9032 return 0;
9033}
9034
9035
9036
9037
9038
9039
9040
9041
9042
9043
9044
9045static void ipr_shutdown(struct pci_dev *pdev)
9046{
9047 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9048 unsigned long lock_flags = 0;
9049
9050 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9051 while(ioa_cfg->in_reset_reload) {
9052 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9053 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9054 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9055 }
9056
9057 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
9058 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9059 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9060}
9061
9062static struct pci_device_id ipr_pci_table[] __devinitdata = {
9063 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9064 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5702, 0, 0, 0 },
9065 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9066 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5703, 0, 0, 0 },
9067 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9068 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573D, 0, 0, 0 },
9069 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9070 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573E, 0, 0, 0 },
9071 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9072 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571B, 0, 0, 0 },
9073 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9074 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572E, 0, 0, 0 },
9075 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9076 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571A, 0, 0, 0 },
9077 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9078 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575B, 0, 0,
9079 IPR_USE_LONG_TRANSOP_TIMEOUT },
9080 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9081 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
9082 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9083 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
9084 IPR_USE_LONG_TRANSOP_TIMEOUT },
9085 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9086 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
9087 IPR_USE_LONG_TRANSOP_TIMEOUT },
9088 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9089 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
9090 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9091 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
9092 IPR_USE_LONG_TRANSOP_TIMEOUT},
9093 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9094 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
9095 IPR_USE_LONG_TRANSOP_TIMEOUT },
9096 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9097 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574E, 0, 0,
9098 IPR_USE_LONG_TRANSOP_TIMEOUT },
9099 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9100 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B3, 0, 0, 0 },
9101 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9102 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CC, 0, 0, 0 },
9103 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9104 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B7, 0, 0,
9105 IPR_USE_LONG_TRANSOP_TIMEOUT | IPR_USE_PCI_WARM_RESET },
9106 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE,
9107 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2780, 0, 0, 0 },
9108 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9109 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571E, 0, 0, 0 },
9110 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9111 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571F, 0, 0,
9112 IPR_USE_LONG_TRANSOP_TIMEOUT },
9113 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9114 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572F, 0, 0,
9115 IPR_USE_LONG_TRANSOP_TIMEOUT },
9116 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9117 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B5, 0, 0, 0 },
9118 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9119 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, 0 },
9120 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9121 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B2, 0, 0, 0 },
9122 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9123 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },
9124 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,
9125 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },
9126 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,
9127 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },
9128 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,
9129 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },
9130 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,
9131 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575D, 0, 0, 0 },
9132 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,
9133 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },
9134 { }
9135};
9136MODULE_DEVICE_TABLE(pci, ipr_pci_table);
9137
9138static struct pci_error_handlers ipr_err_handler = {
9139 .error_detected = ipr_pci_error_detected,
9140 .slot_reset = ipr_pci_slot_reset,
9141};
9142
9143static struct pci_driver ipr_driver = {
9144 .name = IPR_NAME,
9145 .id_table = ipr_pci_table,
9146 .probe = ipr_probe,
9147 .remove = __devexit_p(ipr_remove),
9148 .shutdown = ipr_shutdown,
9149 .err_handler = &ipr_err_handler,
9150};
9151
9152
9153
9154
9155
9156
9157
9158static void ipr_halt_done(struct ipr_cmnd *ipr_cmd)
9159{
9160 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9161
9162 list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q);
9163}
9164
9165
9166
9167
9168
9169
9170
9171static int ipr_halt(struct notifier_block *nb, ulong event, void *buf)
9172{
9173 struct ipr_cmnd *ipr_cmd;
9174 struct ipr_ioa_cfg *ioa_cfg;
9175 unsigned long flags = 0;
9176
9177 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
9178 return NOTIFY_DONE;
9179
9180 spin_lock(&ipr_driver_lock);
9181
9182 list_for_each_entry(ioa_cfg, &ipr_ioa_head, queue) {
9183 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9184 if (!ioa_cfg->allow_cmds) {
9185 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9186 continue;
9187 }
9188
9189 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
9190 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
9191 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
9192 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
9193 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL;
9194
9195 ipr_do_req(ipr_cmd, ipr_halt_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
9196 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9197 }
9198 spin_unlock(&ipr_driver_lock);
9199
9200 return NOTIFY_OK;
9201}
9202
9203static struct notifier_block ipr_notifier = {
9204 ipr_halt, NULL, 0
9205};
9206
9207
9208
9209
9210
9211
9212
9213static int __init ipr_init(void)
9214{
9215 ipr_info("IBM Power RAID SCSI Device Driver version: %s %s\n",
9216 IPR_DRIVER_VERSION, IPR_DRIVER_DATE);
9217
9218 register_reboot_notifier(&ipr_notifier);
9219 return pci_register_driver(&ipr_driver);
9220}
9221
9222
9223
9224
9225
9226
9227
9228
9229
9230static void __exit ipr_exit(void)
9231{
9232 unregister_reboot_notifier(&ipr_notifier);
9233 pci_unregister_driver(&ipr_driver);
9234}
9235
9236module_init(ipr_init);
9237module_exit(ipr_exit);
9238
