1
2
3
4
5
6
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
23#include <linux/interrupt.h>
24#include <linux/workqueue.h>
25#include <linux/firmware.h>
26#include <linux/aer.h>
27#include <linux/mutex.h>
28
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_transport_fc.h>
34#include <scsi/scsi_bsg_fc.h>
35
36#include "qla_bsg.h"
37#include "qla_nx.h"
38#define QLA2XXX_DRIVER_NAME "qla2xxx"
39#define QLA2XXX_APIDEV "ql2xapidev"
40
41
42
43
44
45
46#define MAILBOX_REGISTER_COUNT_2100 8
47#define MAILBOX_REGISTER_COUNT 32
48
49#define QLA2200A_RISC_ROM_VER 4
50#define FPM_2300 6
51#define FPM_2310 7
52
53#include "qla_settings.h"
54
55
56
57
58#define BIT_0 0x1
59#define BIT_1 0x2
60#define BIT_2 0x4
61#define BIT_3 0x8
62#define BIT_4 0x10
63#define BIT_5 0x20
64#define BIT_6 0x40
65#define BIT_7 0x80
66#define BIT_8 0x100
67#define BIT_9 0x200
68#define BIT_10 0x400
69#define BIT_11 0x800
70#define BIT_12 0x1000
71#define BIT_13 0x2000
72#define BIT_14 0x4000
73#define BIT_15 0x8000
74#define BIT_16 0x10000
75#define BIT_17 0x20000
76#define BIT_18 0x40000
77#define BIT_19 0x80000
78#define BIT_20 0x100000
79#define BIT_21 0x200000
80#define BIT_22 0x400000
81#define BIT_23 0x800000
82#define BIT_24 0x1000000
83#define BIT_25 0x2000000
84#define BIT_26 0x4000000
85#define BIT_27 0x8000000
86#define BIT_28 0x10000000
87#define BIT_29 0x20000000
88#define BIT_30 0x40000000
89#define BIT_31 0x80000000
90
91#define LSB(x) ((uint8_t)(x))
92#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
93
94#define LSW(x) ((uint16_t)(x))
95#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
96
97#define LSD(x) ((uint32_t)((uint64_t)(x)))
98#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
99
100#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
101
102
103
104
105
106#define RD_REG_BYTE(addr) readb(addr)
107#define RD_REG_WORD(addr) readw(addr)
108#define RD_REG_DWORD(addr) readl(addr)
109#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
110#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
111#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
112#define WRT_REG_BYTE(addr, data) writeb(data,addr)
113#define WRT_REG_WORD(addr, data) writew(data,addr)
114#define WRT_REG_DWORD(addr, data) writel(data,addr)
115
116
117
118
119
120#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
121#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
122
123
124
125
126#define WWN_SIZE 8
127#define MAX_FIBRE_DEVICES 512
128#define MAX_FIBRE_LUNS 0xFFFF
129#define MAX_RSCN_COUNT 32
130#define MAX_HOST_COUNT 16
131
132
133
134
135#define MAX_BUSES 1
136#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
137#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
138#define MIN_LUNS 8
139#define MAX_LUNS MAX_FIBRE_LUNS
140#define MAX_CMDS_PER_LUN 255
141
142
143
144
145#define SNS_LAST_LOOP_ID_2100 0xfe
146#define SNS_LAST_LOOP_ID_2300 0x7ff
147
148#define LAST_LOCAL_LOOP_ID 0x7d
149#define SNS_FL_PORT 0x7e
150#define FABRIC_CONTROLLER 0x7f
151#define SIMPLE_NAME_SERVER 0x80
152#define SNS_FIRST_LOOP_ID 0x81
153#define MANAGEMENT_SERVER 0xfe
154#define BROADCAST 0xff
155
156
157
158
159
160#define NPH_LAST_HANDLE 0x7ef
161#define NPH_MGMT_SERVER 0x7fa
162#define NPH_SNS 0x7fc
163#define NPH_FABRIC_CONTROLLER 0x7fd
164#define NPH_F_PORT 0x7fe
165#define NPH_IP_BROADCAST 0x7ff
166
167#define MAX_CMDSZ 16
168#include "qla_fw.h"
169
170
171
172
173#define PORT_RETRY_TIME 1
174#define LOOP_DOWN_TIMEOUT 60
175#define LOOP_DOWN_TIME 255
176#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
177
178
179#define MAX_OUTSTANDING_COMMANDS 1024
180
181
182#define REQUEST_ENTRY_CNT_2100 128
183#define REQUEST_ENTRY_CNT_2200 2048
184#define REQUEST_ENTRY_CNT_24XX 2048
185#define RESPONSE_ENTRY_CNT_2100 64
186#define RESPONSE_ENTRY_CNT_2300 512
187#define RESPONSE_ENTRY_CNT_MQ 128
188
189struct req_que;
190
191
192
193
194
195struct sd_dif_tuple {
196 __be16 guard_tag;
197 __be16 app_tag;
198 __be32 ref_tag;
199};
200
201
202
203
204typedef struct srb {
205 atomic_t ref_count;
206 struct fc_port *fcport;
207 uint32_t handle;
208
209 struct scsi_cmnd *cmd;
210
211 uint16_t flags;
212
213 uint32_t request_sense_length;
214 uint8_t *request_sense_ptr;
215
216 void *ctx;
217} srb_t;
218
219
220
221
222#define SRB_DMA_VALID BIT_0
223#define SRB_FCP_CMND_DMA_VALID BIT_12
224#define SRB_CRC_CTX_DMA_VALID BIT_2
225#define SRB_CRC_PROT_DMA_VALID BIT_4
226#define SRB_CRC_CTX_DSD_VALID BIT_5
227
228
229#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
230
231
232
233
234struct srb_iocb {
235 union {
236 struct {
237 uint16_t flags;
238#define SRB_LOGIN_RETRIED BIT_0
239#define SRB_LOGIN_COND_PLOGI BIT_1
240#define SRB_LOGIN_SKIP_PRLI BIT_2
241 uint16_t data[2];
242 } logio;
243 struct {
244
245
246
247
248
249 uint32_t flags;
250 uint32_t lun;
251 uint32_t data;
252 } tmf;
253 } u;
254
255 struct timer_list timer;
256
257 void (*done)(srb_t *);
258 void (*free)(srb_t *);
259 void (*timeout)(srb_t *);
260};
261
262
263#define SRB_LOGIN_CMD 1
264#define SRB_LOGOUT_CMD 2
265#define SRB_ELS_CMD_RPT 3
266#define SRB_ELS_CMD_HST 4
267#define SRB_CT_CMD 5
268#define SRB_ADISC_CMD 6
269#define SRB_TM_CMD 7
270
271struct srb_ctx {
272 uint16_t type;
273 char *name;
274 union {
275 struct srb_iocb *iocb_cmd;
276 struct fc_bsg_job *bsg_job;
277 } u;
278};
279
280struct msg_echo_lb {
281 dma_addr_t send_dma;
282 dma_addr_t rcv_dma;
283 uint16_t req_sg_cnt;
284 uint16_t rsp_sg_cnt;
285 uint16_t options;
286 uint32_t transfer_size;
287};
288
289
290
291
292struct device_reg_2xxx {
293 uint16_t flash_address;
294 uint16_t flash_data;
295 uint16_t unused_1[1];
296 uint16_t ctrl_status;
297#define CSR_FLASH_64K_BANK BIT_3
298#define CSR_FLASH_ENABLE BIT_1
299#define CSR_ISP_SOFT_RESET BIT_0
300
301 uint16_t ictrl;
302#define ICR_EN_INT BIT_15
303#define ICR_EN_RISC BIT_3
304
305 uint16_t istatus;
306#define ISR_RISC_INT BIT_3
307
308 uint16_t semaphore;
309 uint16_t nvram;
310#define NVR_DESELECT 0
311#define NVR_BUSY BIT_15
312#define NVR_WRT_ENABLE BIT_14
313#define NVR_PR_ENABLE BIT_13
314#define NVR_DATA_IN BIT_3
315#define NVR_DATA_OUT BIT_2
316#define NVR_SELECT BIT_1
317#define NVR_CLOCK BIT_0
318
319#define NVR_WAIT_CNT 20000
320
321 union {
322 struct {
323 uint16_t mailbox0;
324 uint16_t mailbox1;
325 uint16_t mailbox2;
326 uint16_t mailbox3;
327 uint16_t mailbox4;
328 uint16_t mailbox5;
329 uint16_t mailbox6;
330 uint16_t mailbox7;
331 uint16_t unused_2[59];
332 } __attribute__((packed)) isp2100;
333 struct {
334
335 uint16_t req_q_in;
336 uint16_t req_q_out;
337
338 uint16_t rsp_q_in;
339 uint16_t rsp_q_out;
340
341
342 uint32_t host_status;
343#define HSR_RISC_INT BIT_15
344#define HSR_RISC_PAUSED BIT_8
345
346
347 uint16_t host_semaphore;
348 uint16_t unused_3[17];
349 uint16_t mailbox0;
350 uint16_t mailbox1;
351 uint16_t mailbox2;
352 uint16_t mailbox3;
353 uint16_t mailbox4;
354 uint16_t mailbox5;
355 uint16_t mailbox6;
356 uint16_t mailbox7;
357 uint16_t mailbox8;
358 uint16_t mailbox9;
359 uint16_t mailbox10;
360 uint16_t mailbox11;
361 uint16_t mailbox12;
362 uint16_t mailbox13;
363 uint16_t mailbox14;
364 uint16_t mailbox15;
365 uint16_t mailbox16;
366 uint16_t mailbox17;
367 uint16_t mailbox18;
368 uint16_t mailbox19;
369 uint16_t mailbox20;
370 uint16_t mailbox21;
371 uint16_t mailbox22;
372 uint16_t mailbox23;
373 uint16_t mailbox24;
374 uint16_t mailbox25;
375 uint16_t mailbox26;
376 uint16_t mailbox27;
377 uint16_t mailbox28;
378 uint16_t mailbox29;
379 uint16_t mailbox30;
380 uint16_t mailbox31;
381 uint16_t fb_cmd;
382 uint16_t unused_4[10];
383 } __attribute__((packed)) isp2300;
384 } u;
385
386 uint16_t fpm_diag_config;
387 uint16_t unused_5[0x4];
388 uint16_t risc_hw;
389 uint16_t unused_5_1;
390 uint16_t pcr;
391 uint16_t unused_6[0x5];
392 uint16_t mctr;
393 uint16_t unused_7[0x3];
394 uint16_t fb_cmd_2100;
395 uint16_t unused_8[0x3];
396 uint16_t hccr;
397#define HCCR_HOST_INT BIT_7
398#define HCCR_RISC_PAUSE BIT_5
399
400#define HCCR_RESET_RISC 0x1000
401#define HCCR_PAUSE_RISC 0x2000
402#define HCCR_RELEASE_RISC 0x3000
403#define HCCR_SET_HOST_INT 0x5000
404#define HCCR_CLR_HOST_INT 0x6000
405#define HCCR_CLR_RISC_INT 0x7000
406#define HCCR_DISABLE_PARITY_PAUSE 0x4001
407#define HCCR_ENABLE_PARITY 0xA000
408
409 uint16_t unused_9[5];
410 uint16_t gpiod;
411 uint16_t gpioe;
412#define GPIO_LED_MASK 0x00C0
413#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
414#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
415#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
416#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
417#define GPIO_LED_ALL_OFF 0x0000
418#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
419#define GPIO_LED_RGA_ON 0x00C1
420
421 union {
422 struct {
423 uint16_t unused_10[8];
424 uint16_t mailbox8;
425 uint16_t mailbox9;
426 uint16_t mailbox10;
427 uint16_t mailbox11;
428 uint16_t mailbox12;
429 uint16_t mailbox13;
430 uint16_t mailbox14;
431 uint16_t mailbox15;
432 uint16_t mailbox16;
433 uint16_t mailbox17;
434 uint16_t mailbox18;
435 uint16_t mailbox19;
436 uint16_t mailbox20;
437 uint16_t mailbox21;
438 uint16_t mailbox22;
439 uint16_t mailbox23;
440 } __attribute__((packed)) isp2200;
441 } u_end;
442};
443
444struct device_reg_25xxmq {
445 uint32_t req_q_in;
446 uint32_t req_q_out;
447 uint32_t rsp_q_in;
448 uint32_t rsp_q_out;
449};
450
451typedef union {
452 struct device_reg_2xxx isp;
453 struct device_reg_24xx isp24;
454 struct device_reg_25xxmq isp25mq;
455 struct device_reg_82xx isp82;
456} device_reg_t;
457
458#define ISP_REQ_Q_IN(ha, reg) \
459 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
460 &(reg)->u.isp2100.mailbox4 : \
461 &(reg)->u.isp2300.req_q_in)
462#define ISP_REQ_Q_OUT(ha, reg) \
463 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
464 &(reg)->u.isp2100.mailbox4 : \
465 &(reg)->u.isp2300.req_q_out)
466#define ISP_RSP_Q_IN(ha, reg) \
467 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
468 &(reg)->u.isp2100.mailbox5 : \
469 &(reg)->u.isp2300.rsp_q_in)
470#define ISP_RSP_Q_OUT(ha, reg) \
471 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
472 &(reg)->u.isp2100.mailbox5 : \
473 &(reg)->u.isp2300.rsp_q_out)
474
475#define MAILBOX_REG(ha, reg, num) \
476 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
477 (num < 8 ? \
478 &(reg)->u.isp2100.mailbox0 + (num) : \
479 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
480 &(reg)->u.isp2300.mailbox0 + (num))
481#define RD_MAILBOX_REG(ha, reg, num) \
482 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
483#define WRT_MAILBOX_REG(ha, reg, num, data) \
484 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
485
486#define FB_CMD_REG(ha, reg) \
487 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
488 &(reg)->fb_cmd_2100 : \
489 &(reg)->u.isp2300.fb_cmd)
490#define RD_FB_CMD_REG(ha, reg) \
491 RD_REG_WORD(FB_CMD_REG(ha, reg))
492#define WRT_FB_CMD_REG(ha, reg, data) \
493 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
494
495typedef struct {
496 uint32_t out_mb;
497 uint32_t in_mb;
498 uint16_t mb[MAILBOX_REGISTER_COUNT];
499 long buf_size;
500 void *bufp;
501 uint32_t tov;
502 uint8_t flags;
503#define MBX_DMA_IN BIT_0
504#define MBX_DMA_OUT BIT_1
505#define IOCTL_CMD BIT_2
506} mbx_cmd_t;
507
508#define MBX_TOV_SECONDS 30
509
510
511
512
513#define PROD_ID_1 0x4953
514#define PROD_ID_2 0x0000
515#define PROD_ID_2a 0x5020
516#define PROD_ID_3 0x2020
517
518
519
520
521#define MBS_FRM_ALIVE 0
522#define MBS_CHKSUM_ERR 1
523#define MBS_BUSY 4
524
525
526
527
528#define MBS_COMMAND_COMPLETE 0x4000
529#define MBS_INVALID_COMMAND 0x4001
530#define MBS_HOST_INTERFACE_ERROR 0x4002
531#define MBS_TEST_FAILED 0x4003
532#define MBS_COMMAND_ERROR 0x4005
533#define MBS_COMMAND_PARAMETER_ERROR 0x4006
534#define MBS_PORT_ID_USED 0x4007
535#define MBS_LOOP_ID_USED 0x4008
536#define MBS_ALL_IDS_IN_USE 0x4009
537#define MBS_NOT_LOGGED_IN 0x400A
538#define MBS_LINK_DOWN_ERROR 0x400B
539#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
540
541
542
543
544#define MBA_ASYNC_EVENT 0x8000
545#define MBA_RESET 0x8001
546#define MBA_SYSTEM_ERR 0x8002
547#define MBA_REQ_TRANSFER_ERR 0x8003
548#define MBA_RSP_TRANSFER_ERR 0x8004
549#define MBA_WAKEUP_THRES 0x8005
550#define MBA_LIP_OCCURRED 0x8010
551
552#define MBA_LOOP_UP 0x8011
553#define MBA_LOOP_DOWN 0x8012
554#define MBA_LIP_RESET 0x8013
555#define MBA_PORT_UPDATE 0x8014
556#define MBA_RSCN_UPDATE 0x8015
557#define MBA_LIP_F8 0x8016
558#define MBA_LOOP_INIT_ERR 0x8017
559#define MBA_FABRIC_AUTH_REQ 0x801b
560#define MBA_SCSI_COMPLETION 0x8020
561#define MBA_CTIO_COMPLETION 0x8021
562#define MBA_IP_COMPLETION 0x8022
563#define MBA_IP_RECEIVE 0x8023
564#define MBA_IP_BROADCAST 0x8024
565#define MBA_IP_LOW_WATER_MARK 0x8025
566#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
567#define MBA_IP_HDR_DATA_SPLIT 0x8027
568
569#define MBA_TRACE_NOTIFICATION 0x8028
570#define MBA_POINT_TO_POINT 0x8030
571#define MBA_CMPLT_1_16BIT 0x8031
572#define MBA_CMPLT_2_16BIT 0x8032
573#define MBA_CMPLT_3_16BIT 0x8033
574#define MBA_CMPLT_4_16BIT 0x8034
575#define MBA_CMPLT_5_16BIT 0x8035
576#define MBA_CHG_IN_CONNECTION 0x8036
577#define MBA_RIO_RESPONSE 0x8040
578#define MBA_ZIO_RESPONSE 0x8040
579#define MBA_CMPLT_2_32BIT 0x8042
580#define MBA_BYPASS_NOTIFICATION 0x8043
581#define MBA_DISCARD_RND_FRAME 0x8048
582#define MBA_REJECTED_FCP_CMD 0x8049
583
584
585#define MBS_LB_RESET 0x17
586
587
588
589#define FO1_AE_ON_LIPF8 BIT_0
590#define FO1_AE_ALL_LIP_RESET BIT_1
591#define FO1_CTIO_RETRY BIT_3
592#define FO1_DISABLE_LIP_F7_SW BIT_4
593#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
594#define FO1_DISABLE_GPIO6_7 BIT_6
595#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
596#define FO1_SET_EMPHASIS_SWING BIT_8
597#define FO1_AE_AUTO_BYPASS BIT_9
598#define FO1_ENABLE_PURE_IOCB BIT_10
599#define FO1_AE_PLOGI_RJT BIT_11
600#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
601#define FO1_AE_QUEUE_FULL BIT_13
602
603#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
604#define FO2_REV_LOOPBACK BIT_1
605
606#define FO3_ENABLE_EMERG_IOCB BIT_0
607#define FO3_AE_RND_ERROR BIT_1
608
609
610#define ADD_FO_COUNT 3
611#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
612#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
613
614#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
615
616#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
617
618
619
620
621#define MBC_LOAD_RAM 1
622#define MBC_EXECUTE_FIRMWARE 2
623#define MBC_WRITE_RAM_WORD 4
624#define MBC_READ_RAM_WORD 5
625#define MBC_MAILBOX_REGISTER_TEST 6
626#define MBC_VERIFY_CHECKSUM 7
627#define MBC_GET_FIRMWARE_VERSION 8
628#define MBC_LOAD_RISC_RAM 9
629#define MBC_DUMP_RISC_RAM 0xa
630#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
631#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
632#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
633#define MBC_READ_RAM_EXTENDED 0xf
634#define MBC_IOCB_COMMAND 0x12
635#define MBC_STOP_FIRMWARE 0x14
636#define MBC_ABORT_COMMAND 0x15
637#define MBC_ABORT_DEVICE 0x16
638#define MBC_ABORT_TARGET 0x17
639#define MBC_RESET 0x18
640#define MBC_GET_ADAPTER_LOOP_ID 0x20
641#define MBC_GET_RETRY_COUNT 0x22
642#define MBC_DISABLE_VI 0x24
643#define MBC_ENABLE_VI 0x25
644#define MBC_GET_FIRMWARE_OPTION 0x28
645#define MBC_SET_FIRMWARE_OPTION 0x38
646#define MBC_LOOP_PORT_BYPASS 0x40
647#define MBC_LOOP_PORT_ENABLE 0x41
648#define MBC_GET_RESOURCE_COUNTS 0x42
649#define MBC_NON_PARTICIPATE 0x43
650#define MBC_DIAGNOSTIC_ECHO 0x44
651#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
652#define MBC_ONLINE_SELF_TEST 0x46
653#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
654#define MBC_RESET_LINK_STATUS 0x52
655#define MBC_IOCB_COMMAND_A64 0x54
656#define MBC_SEND_RNID_ELS 0x57
657#define MBC_SET_RNID_PARAMS 0x59
658#define MBC_GET_RNID_PARAMS 0x5a
659#define MBC_DATA_RATE 0x5d
660#define MBC_INITIALIZE_FIRMWARE 0x60
661#define MBC_INITIATE_LIP 0x62
662
663#define MBC_GET_FC_AL_POSITION_MAP 0x63
664#define MBC_GET_PORT_DATABASE 0x64
665#define MBC_CLEAR_ACA 0x65
666#define MBC_TARGET_RESET 0x66
667#define MBC_CLEAR_TASK_SET 0x67
668#define MBC_ABORT_TASK_SET 0x68
669#define MBC_GET_FIRMWARE_STATE 0x69
670#define MBC_GET_PORT_NAME 0x6a
671#define MBC_GET_LINK_STATUS 0x6b
672#define MBC_LIP_RESET 0x6c
673#define MBC_SEND_SNS_COMMAND 0x6e
674
675#define MBC_LOGIN_FABRIC_PORT 0x6f
676#define MBC_SEND_CHANGE_REQUEST 0x70
677#define MBC_LOGOUT_FABRIC_PORT 0x71
678#define MBC_LIP_FULL_LOGIN 0x72
679#define MBC_LOGIN_LOOP_PORT 0x74
680#define MBC_PORT_NODE_NAME_LIST 0x75
681#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
682#define MBC_UNLOAD_IP 0x79
683#define MBC_GET_ID_LIST 0x7C
684#define MBC_SEND_LFA_COMMAND 0x7D
685#define MBC_LUN_RESET 0x7E
686
687
688
689
690#define MBC_SERDES_PARAMS 0x10
691#define MBC_GET_IOCB_STATUS 0x12
692#define MBC_PORT_PARAMS 0x1A
693#define MBC_GET_TIMEOUT_PARAMS 0x22
694#define MBC_TRACE_CONTROL 0x27
695#define MBC_GEN_SYSTEM_ERROR 0x2a
696#define MBC_WRITE_SFP 0x30
697#define MBC_READ_SFP 0x31
698#define MBC_SET_TIMEOUT_PARAMS 0x32
699#define MBC_MID_INITIALIZE_FIRMWARE 0x48
700#define MBC_MID_GET_VP_DATABASE 0x49
701#define MBC_MID_GET_VP_ENTRY 0x4a
702#define MBC_HOST_MEMORY_COPY 0x53
703#define MBC_SEND_RNFT_ELS 0x5e
704#define MBC_GET_LINK_PRIV_STATS 0x6d
705#define MBC_SET_VENDOR_ID 0x76
706#define MBC_SET_PORT_CONFIG 0x122
707#define MBC_GET_PORT_CONFIG 0x123
708
709
710
711
712#define MBC_WRITE_MPI_REGISTER 0x01
713
714
715#define FCAL_MAP_SIZE 128
716
717
718#define MBX_31 BIT_31
719#define MBX_30 BIT_30
720#define MBX_29 BIT_29
721#define MBX_28 BIT_28
722#define MBX_27 BIT_27
723#define MBX_26 BIT_26
724#define MBX_25 BIT_25
725#define MBX_24 BIT_24
726#define MBX_23 BIT_23
727#define MBX_22 BIT_22
728#define MBX_21 BIT_21
729#define MBX_20 BIT_20
730#define MBX_19 BIT_19
731#define MBX_18 BIT_18
732#define MBX_17 BIT_17
733#define MBX_16 BIT_16
734#define MBX_15 BIT_15
735#define MBX_14 BIT_14
736#define MBX_13 BIT_13
737#define MBX_12 BIT_12
738#define MBX_11 BIT_11
739#define MBX_10 BIT_10
740#define MBX_9 BIT_9
741#define MBX_8 BIT_8
742#define MBX_7 BIT_7
743#define MBX_6 BIT_6
744#define MBX_5 BIT_5
745#define MBX_4 BIT_4
746#define MBX_3 BIT_3
747#define MBX_2 BIT_2
748#define MBX_1 BIT_1
749#define MBX_0 BIT_0
750
751
752
753
754#define FSTATE_CONFIG_WAIT 0
755#define FSTATE_WAIT_AL_PA 1
756#define FSTATE_WAIT_LOGIN 2
757#define FSTATE_READY 3
758#define FSTATE_LOSS_OF_SYNC 4
759#define FSTATE_ERROR 5
760#define FSTATE_REINIT 6
761#define FSTATE_NON_PART 7
762
763#define FSTATE_CONFIG_CORRECT 0
764#define FSTATE_P2P_RCV_LIP 1
765#define FSTATE_P2P_CHOOSE_LOOP 2
766#define FSTATE_P2P_RCV_UNIDEN_LIP 3
767#define FSTATE_FATAL_ERROR 4
768#define FSTATE_LOOP_BACK_CONN 5
769
770
771
772
773
774#define PORT_DATABASE_SIZE 128
775typedef struct {
776 uint8_t options;
777 uint8_t control;
778 uint8_t master_state;
779 uint8_t slave_state;
780 uint8_t reserved[2];
781 uint8_t hard_address;
782 uint8_t reserved_1;
783 uint8_t port_id[4];
784 uint8_t node_name[WWN_SIZE];
785 uint8_t port_name[WWN_SIZE];
786 uint16_t execution_throttle;
787 uint16_t execution_count;
788 uint8_t reset_count;
789 uint8_t reserved_2;
790 uint16_t resource_allocation;
791 uint16_t current_allocation;
792 uint16_t queue_head;
793 uint16_t queue_tail;
794 uint16_t transmit_execution_list_next;
795 uint16_t transmit_execution_list_previous;
796 uint16_t common_features;
797 uint16_t total_concurrent_sequences;
798 uint16_t RO_by_information_category;
799 uint8_t recipient;
800 uint8_t initiator;
801 uint16_t receive_data_size;
802 uint16_t concurrent_sequences;
803 uint16_t open_sequences_per_exchange;
804 uint16_t lun_abort_flags;
805 uint16_t lun_stop_flags;
806 uint16_t stop_queue_head;
807 uint16_t stop_queue_tail;
808 uint16_t port_retry_timer;
809 uint16_t next_sequence_id;
810 uint16_t frame_count;
811 uint16_t PRLI_payload_length;
812 uint8_t prli_svc_param_word_0[2];
813
814 uint8_t prli_svc_param_word_3[2];
815
816 uint16_t loop_id;
817 uint16_t extended_lun_info_list_pointer;
818 uint16_t extended_lun_stop_list_pointer;
819} port_database_t;
820
821
822
823
824#define PD_STATE_DISCOVERY 0
825#define PD_STATE_WAIT_DISCOVERY_ACK 1
826#define PD_STATE_PORT_LOGIN 2
827#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
828#define PD_STATE_PROCESS_LOGIN 4
829#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
830#define PD_STATE_PORT_LOGGED_IN 6
831#define PD_STATE_PORT_UNAVAILABLE 7
832#define PD_STATE_PROCESS_LOGOUT 8
833#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
834#define PD_STATE_PORT_LOGOUT 10
835#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
836
837
838#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
839#define QLA_ZIO_DISABLED 0
840#define QLA_ZIO_DEFAULT_TIMER 2
841
842
843
844
845
846#define ICB_VERSION 1
847typedef struct {
848 uint8_t version;
849 uint8_t reserved_1;
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870 uint8_t firmware_options[2];
871
872 uint16_t frame_payload_size;
873 uint16_t max_iocb_allocation;
874 uint16_t execution_throttle;
875 uint8_t retry_count;
876 uint8_t retry_delay;
877 uint8_t port_name[WWN_SIZE];
878 uint16_t hard_address;
879 uint8_t inquiry_data;
880 uint8_t login_timeout;
881 uint8_t node_name[WWN_SIZE];
882
883 uint16_t request_q_outpointer;
884 uint16_t response_q_inpointer;
885 uint16_t request_q_length;
886 uint16_t response_q_length;
887 uint32_t request_q_address[2];
888 uint32_t response_q_address[2];
889
890 uint16_t lun_enables;
891 uint8_t command_resource_count;
892 uint8_t immediate_notify_resource_count;
893 uint16_t timeout;
894 uint8_t reserved_2[2];
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915 uint8_t add_firmware_options[2];
916
917 uint8_t response_accumulation_timer;
918 uint8_t interrupt_delay_timer;
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939 uint8_t special_options[2];
940
941 uint8_t reserved_3[26];
942} init_cb_t;
943
944
945
946
947#define GLSO_SEND_RPS BIT_0
948#define GLSO_USE_DID BIT_3
949
950struct link_statistics {
951 uint32_t link_fail_cnt;
952 uint32_t loss_sync_cnt;
953 uint32_t loss_sig_cnt;
954 uint32_t prim_seq_err_cnt;
955 uint32_t inval_xmit_word_cnt;
956 uint32_t inval_crc_cnt;
957 uint32_t lip_cnt;
958 uint32_t unused1[0x1a];
959 uint32_t tx_frames;
960 uint32_t rx_frames;
961 uint32_t dumped_frames;
962 uint32_t unused2[2];
963 uint32_t nos_rcvd;
964};
965
966
967
968
969#define NV_START_BIT BIT_2
970#define NV_WRITE_OP (BIT_26+BIT_24)
971#define NV_READ_OP (BIT_26+BIT_25)
972#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
973#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
974#define NV_DELAY_COUNT 10
975
976
977
978
979typedef struct {
980
981
982
983 uint8_t id[4];
984 uint8_t nvram_version;
985 uint8_t reserved_0;
986
987
988
989
990 uint8_t parameter_block_version;
991 uint8_t reserved_1;
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012 uint8_t firmware_options[2];
1013
1014 uint16_t frame_payload_size;
1015 uint16_t max_iocb_allocation;
1016 uint16_t execution_throttle;
1017 uint8_t retry_count;
1018 uint8_t retry_delay;
1019 uint8_t port_name[WWN_SIZE];
1020 uint16_t hard_address;
1021 uint8_t inquiry_data;
1022 uint8_t login_timeout;
1023 uint8_t node_name[WWN_SIZE];
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044 uint8_t add_firmware_options[2];
1045
1046 uint8_t response_accumulation_timer;
1047 uint8_t interrupt_delay_timer;
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068 uint8_t special_options[2];
1069
1070
1071 uint8_t reserved_2[22];
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110 uint8_t seriallink_options[4];
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133 uint8_t host_p[2];
1134
1135 uint8_t boot_node_name[WWN_SIZE];
1136 uint8_t boot_lun_number;
1137 uint8_t reset_delay;
1138 uint8_t port_down_retry_count;
1139 uint8_t boot_id_number;
1140 uint16_t max_luns_per_target;
1141 uint8_t fcode_boot_port_name[WWN_SIZE];
1142 uint8_t alternate_port_name[WWN_SIZE];
1143 uint8_t alternate_node_name[WWN_SIZE];
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155 uint8_t efi_parameters;
1156
1157 uint8_t link_down_timeout;
1158
1159 uint8_t adapter_id[16];
1160
1161 uint8_t alt1_boot_node_name[WWN_SIZE];
1162 uint16_t alt1_boot_lun_number;
1163 uint8_t alt2_boot_node_name[WWN_SIZE];
1164 uint16_t alt2_boot_lun_number;
1165 uint8_t alt3_boot_node_name[WWN_SIZE];
1166 uint16_t alt3_boot_lun_number;
1167 uint8_t alt4_boot_node_name[WWN_SIZE];
1168 uint16_t alt4_boot_lun_number;
1169 uint8_t alt5_boot_node_name[WWN_SIZE];
1170 uint16_t alt5_boot_lun_number;
1171 uint8_t alt6_boot_node_name[WWN_SIZE];
1172 uint16_t alt6_boot_lun_number;
1173 uint8_t alt7_boot_node_name[WWN_SIZE];
1174 uint16_t alt7_boot_lun_number;
1175
1176 uint8_t reserved_3[2];
1177
1178
1179 uint8_t model_number[16];
1180
1181
1182 uint8_t oem_specific[16];
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205 uint8_t adapter_features[2];
1206
1207 uint8_t reserved_4[16];
1208
1209
1210 uint16_t subsystem_vendor_id_2200;
1211
1212
1213 uint16_t subsystem_device_id_2200;
1214
1215 uint8_t reserved_5;
1216 uint8_t checksum;
1217} nvram_t;
1218
1219
1220
1221
1222typedef struct {
1223 uint8_t data[60];
1224 uint32_t signature;
1225#define RESPONSE_PROCESSED 0xDEADDEAD
1226} response_t;
1227
1228typedef union {
1229 uint16_t extended;
1230 struct {
1231 uint8_t reserved;
1232 uint8_t standard;
1233 } id;
1234} target_id_t;
1235
1236#define SET_TARGET_ID(ha, to, from) \
1237do { \
1238 if (HAS_EXTENDED_IDS(ha)) \
1239 to.extended = cpu_to_le16(from); \
1240 else \
1241 to.id.standard = (uint8_t)from; \
1242} while (0)
1243
1244
1245
1246
1247#define COMMAND_TYPE 0x11
1248typedef struct {
1249 uint8_t entry_type;
1250 uint8_t entry_count;
1251 uint8_t sys_define;
1252 uint8_t entry_status;
1253 uint32_t handle;
1254 target_id_t target;
1255 uint16_t lun;
1256 uint16_t control_flags;
1257#define CF_WRITE BIT_6
1258#define CF_READ BIT_5
1259#define CF_SIMPLE_TAG BIT_3
1260#define CF_ORDERED_TAG BIT_2
1261#define CF_HEAD_TAG BIT_1
1262 uint16_t reserved_1;
1263 uint16_t timeout;
1264 uint16_t dseg_count;
1265 uint8_t scsi_cdb[MAX_CMDSZ];
1266 uint32_t byte_count;
1267 uint32_t dseg_0_address;
1268 uint32_t dseg_0_length;
1269 uint32_t dseg_1_address;
1270 uint32_t dseg_1_length;
1271 uint32_t dseg_2_address;
1272 uint32_t dseg_2_length;
1273} cmd_entry_t;
1274
1275
1276
1277
1278#define COMMAND_A64_TYPE 0x19
1279typedef struct {
1280 uint8_t entry_type;
1281 uint8_t entry_count;
1282 uint8_t sys_define;
1283 uint8_t entry_status;
1284 uint32_t handle;
1285 target_id_t target;
1286 uint16_t lun;
1287 uint16_t control_flags;
1288 uint16_t reserved_1;
1289 uint16_t timeout;
1290 uint16_t dseg_count;
1291 uint8_t scsi_cdb[MAX_CMDSZ];
1292 uint32_t byte_count;
1293 uint32_t dseg_0_address[2];
1294 uint32_t dseg_0_length;
1295 uint32_t dseg_1_address[2];
1296 uint32_t dseg_1_length;
1297} cmd_a64_entry_t, request_t;
1298
1299
1300
1301
1302#define CONTINUE_TYPE 0x02
1303typedef struct {
1304 uint8_t entry_type;
1305 uint8_t entry_count;
1306 uint8_t sys_define;
1307 uint8_t entry_status;
1308 uint32_t reserved;
1309 uint32_t dseg_0_address;
1310 uint32_t dseg_0_length;
1311 uint32_t dseg_1_address;
1312 uint32_t dseg_1_length;
1313 uint32_t dseg_2_address;
1314 uint32_t dseg_2_length;
1315 uint32_t dseg_3_address;
1316 uint32_t dseg_3_length;
1317 uint32_t dseg_4_address;
1318 uint32_t dseg_4_length;
1319 uint32_t dseg_5_address;
1320 uint32_t dseg_5_length;
1321 uint32_t dseg_6_address;
1322 uint32_t dseg_6_length;
1323} cont_entry_t;
1324
1325
1326
1327
1328#define CONTINUE_A64_TYPE 0x0A
1329typedef struct {
1330 uint8_t entry_type;
1331 uint8_t entry_count;
1332 uint8_t sys_define;
1333 uint8_t entry_status;
1334 uint32_t dseg_0_address[2];
1335 uint32_t dseg_0_length;
1336 uint32_t dseg_1_address[2];
1337 uint32_t dseg_1_length;
1338 uint32_t dseg_2_address [2];
1339 uint32_t dseg_2_length;
1340 uint32_t dseg_3_address[2];
1341 uint32_t dseg_3_length;
1342 uint32_t dseg_4_address[2];
1343 uint32_t dseg_4_length;
1344} cont_a64_entry_t;
1345
1346#define PO_MODE_DIF_INSERT 0
1347#define PO_MODE_DIF_REMOVE BIT_0
1348#define PO_MODE_DIF_PASS BIT_1
1349#define PO_MODE_DIF_REPLACE (BIT_0 + BIT_1)
1350#define PO_ENABLE_DIF_BUNDLING BIT_8
1351#define PO_ENABLE_INCR_GUARD_SEED BIT_3
1352#define PO_DISABLE_INCR_REF_TAG BIT_5
1353#define PO_DISABLE_GUARD_CHECK BIT_4
1354
1355
1356
1357struct crc_context {
1358 uint32_t handle;
1359 uint32_t ref_tag;
1360 uint16_t app_tag;
1361 uint8_t ref_tag_mask[4];
1362 uint8_t app_tag_mask[2];
1363 uint16_t guard_seed;
1364 uint16_t prot_opts;
1365 uint16_t blk_size;
1366 uint16_t runt_blk_guard;
1367
1368 uint32_t byte_count;
1369
1370 union {
1371 struct {
1372 uint32_t reserved_1;
1373 uint16_t reserved_2;
1374 uint16_t reserved_3;
1375 uint32_t reserved_4;
1376 uint32_t data_address[2];
1377 uint32_t data_length;
1378 uint32_t reserved_5[2];
1379 uint32_t reserved_6;
1380 } nobundling;
1381 struct {
1382 uint32_t dif_byte_count;
1383
1384 uint16_t reserved_1;
1385 uint16_t dseg_count;
1386 uint32_t reserved_2;
1387 uint32_t data_address[2];
1388 uint32_t data_length;
1389 uint32_t dif_address[2];
1390 uint32_t dif_length;
1391
1392 } bundling;
1393 } u;
1394
1395 struct fcp_cmnd fcp_cmnd;
1396 dma_addr_t crc_ctx_dma;
1397
1398 struct list_head dsd_list;
1399
1400
1401};
1402
1403#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1404#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1405
1406
1407
1408
1409#define STATUS_TYPE 0x03
1410typedef struct {
1411 uint8_t entry_type;
1412 uint8_t entry_count;
1413 uint8_t sys_define;
1414 uint8_t entry_status;
1415 uint32_t handle;
1416 uint16_t scsi_status;
1417 uint16_t comp_status;
1418 uint16_t state_flags;
1419 uint16_t status_flags;
1420 uint16_t rsp_info_len;
1421 uint16_t req_sense_length;
1422 uint32_t residual_length;
1423 uint8_t rsp_info[8];
1424 uint8_t req_sense_data[32];
1425} sts_entry_t;
1426
1427
1428
1429
1430#define RF_RQ_DMA_ERROR BIT_6
1431#define RF_INV_E_ORDER BIT_5
1432#define RF_INV_E_COUNT BIT_4
1433#define RF_INV_E_PARAM BIT_3
1434#define RF_INV_E_TYPE BIT_2
1435#define RF_BUSY BIT_1
1436#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1437 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1438#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1439 RF_INV_E_TYPE)
1440
1441
1442
1443
1444#define SS_MASK 0xfff
1445#define SS_RESIDUAL_UNDER BIT_11
1446#define SS_RESIDUAL_OVER BIT_10
1447#define SS_SENSE_LEN_VALID BIT_9
1448#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1449
1450#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1451#define SS_BUSY_CONDITION BIT_3
1452#define SS_CONDITION_MET BIT_2
1453#define SS_CHECK_CONDITION BIT_1
1454
1455
1456
1457
1458#define CS_COMPLETE 0x0
1459#define CS_INCOMPLETE 0x1
1460#define CS_DMA 0x2
1461#define CS_TRANSPORT 0x3
1462#define CS_RESET 0x4
1463#define CS_ABORTED 0x5
1464#define CS_TIMEOUT 0x6
1465#define CS_DATA_OVERRUN 0x7
1466#define CS_DIF_ERROR 0xC
1467
1468#define CS_DATA_UNDERRUN 0x15
1469#define CS_QUEUE_FULL 0x1C
1470#define CS_PORT_UNAVAILABLE 0x28
1471
1472#define CS_PORT_LOGGED_OUT 0x29
1473#define CS_PORT_CONFIG_CHG 0x2A
1474#define CS_PORT_BUSY 0x2B
1475#define CS_COMPLETE_CHKCOND 0x30
1476#define CS_BAD_PAYLOAD 0x80
1477#define CS_UNKNOWN 0x81
1478#define CS_RETRY 0x82
1479#define CS_LOOP_DOWN_ABORT 0x83
1480
1481
1482
1483
1484#define SF_ABTS_TERMINATED BIT_10
1485#define SF_LOGOUT_SENT BIT_13
1486
1487
1488
1489
1490#define STATUS_CONT_TYPE 0x10
1491typedef struct {
1492 uint8_t entry_type;
1493 uint8_t entry_count;
1494 uint8_t sys_define;
1495 uint8_t entry_status;
1496 uint8_t data[60];
1497} sts_cont_entry_t;
1498
1499
1500
1501
1502
1503#define STATUS_TYPE_21 0x21
1504typedef struct {
1505 uint8_t entry_type;
1506 uint8_t entry_count;
1507 uint8_t handle_count;
1508 uint8_t entry_status;
1509 uint32_t handle[15];
1510} sts21_entry_t;
1511
1512
1513
1514
1515
1516#define STATUS_TYPE_22 0x22
1517typedef struct {
1518 uint8_t entry_type;
1519 uint8_t entry_count;
1520 uint8_t handle_count;
1521 uint8_t entry_status;
1522 uint16_t handle[30];
1523} sts22_entry_t;
1524
1525
1526
1527
1528#define MARKER_TYPE 0x04
1529typedef struct {
1530 uint8_t entry_type;
1531 uint8_t entry_count;
1532 uint8_t handle_count;
1533 uint8_t entry_status;
1534 uint32_t sys_define_2;
1535 target_id_t target;
1536 uint8_t modifier;
1537#define MK_SYNC_ID_LUN 0
1538#define MK_SYNC_ID 1
1539#define MK_SYNC_ALL 2
1540#define MK_SYNC_LIP 3
1541
1542
1543 uint8_t reserved_1;
1544 uint16_t sequence_number;
1545 uint16_t lun;
1546 uint8_t reserved_2[48];
1547} mrk_entry_t;
1548
1549
1550
1551
1552#define MS_IOCB_TYPE 0x29
1553typedef struct {
1554 uint8_t entry_type;
1555 uint8_t entry_count;
1556 uint8_t handle_count;
1557 uint8_t entry_status;
1558 uint32_t handle1;
1559 target_id_t loop_id;
1560 uint16_t status;
1561 uint16_t control_flags;
1562 uint16_t reserved2;
1563 uint16_t timeout;
1564 uint16_t cmd_dsd_count;
1565 uint16_t total_dsd_count;
1566 uint8_t type;
1567 uint8_t r_ctl;
1568 uint16_t rx_id;
1569 uint16_t reserved3;
1570 uint32_t handle2;
1571 uint32_t rsp_bytecount;
1572 uint32_t req_bytecount;
1573 uint32_t dseg_req_address[2];
1574 uint32_t dseg_req_length;
1575 uint32_t dseg_rsp_address[2];
1576 uint32_t dseg_rsp_length;
1577} ms_iocb_entry_t;
1578
1579
1580
1581
1582
1583#define MBX_IOCB_TYPE 0x39
1584struct mbx_entry {
1585 uint8_t entry_type;
1586 uint8_t entry_count;
1587 uint8_t sys_define1;
1588
1589#define SOURCE_SCSI 0x00
1590#define SOURCE_IP 0x01
1591#define SOURCE_VI 0x02
1592#define SOURCE_SCTP 0x03
1593#define SOURCE_MP 0x04
1594#define SOURCE_MPIOCTL 0x05
1595#define SOURCE_ASYNC_IOCB 0x07
1596
1597 uint8_t entry_status;
1598
1599 uint32_t handle;
1600 target_id_t loop_id;
1601
1602 uint16_t status;
1603 uint16_t state_flags;
1604 uint16_t status_flags;
1605
1606 uint32_t sys_define2[2];
1607
1608 uint16_t mb0;
1609 uint16_t mb1;
1610 uint16_t mb2;
1611 uint16_t mb3;
1612 uint16_t mb6;
1613 uint16_t mb7;
1614 uint16_t mb9;
1615 uint16_t mb10;
1616 uint32_t reserved_2[2];
1617 uint8_t node_name[WWN_SIZE];
1618 uint8_t port_name[WWN_SIZE];
1619};
1620
1621
1622
1623
1624#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1625#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1626
1627
1628
1629
1630
1631typedef union {
1632 uint32_t b24 : 24;
1633
1634 struct {
1635#ifdef __BIG_ENDIAN
1636 uint8_t domain;
1637 uint8_t area;
1638 uint8_t al_pa;
1639#elif defined(__LITTLE_ENDIAN)
1640 uint8_t al_pa;
1641 uint8_t area;
1642 uint8_t domain;
1643#else
1644#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1645#endif
1646 uint8_t rsvd_1;
1647 } b;
1648} port_id_t;
1649#define INVALID_PORT_ID 0xFFFFFF
1650
1651
1652
1653
1654typedef struct {
1655 port_id_t d_id;
1656 uint8_t node_name[WWN_SIZE];
1657 uint8_t port_name[WWN_SIZE];
1658 uint8_t fabric_port_name[WWN_SIZE];
1659 uint16_t fp_speed;
1660 uint8_t fc4_type;
1661} sw_info_t;
1662
1663
1664#define FC4_TYPE_FCP_SCSI 0x08
1665#define FC4_TYPE_OTHER 0x0
1666#define FC4_TYPE_UNKNOWN 0xff
1667
1668
1669
1670
1671 typedef enum {
1672 FCT_UNKNOWN,
1673 FCT_RSCN,
1674 FCT_SWITCH,
1675 FCT_BROADCAST,
1676 FCT_INITIATOR,
1677 FCT_TARGET
1678} fc_port_type_t;
1679
1680
1681
1682
1683typedef struct fc_port {
1684 struct list_head list;
1685 struct scsi_qla_host *vha;
1686
1687 uint8_t node_name[WWN_SIZE];
1688 uint8_t port_name[WWN_SIZE];
1689 port_id_t d_id;
1690 uint16_t loop_id;
1691 uint16_t old_loop_id;
1692
1693 uint8_t fcp_prio;
1694
1695 uint8_t fabric_port_name[WWN_SIZE];
1696 uint16_t fp_speed;
1697
1698 fc_port_type_t port_type;
1699
1700 atomic_t state;
1701 uint32_t flags;
1702
1703 int login_retry;
1704
1705 struct fc_rport *rport, *drport;
1706 u32 supported_classes;
1707
1708 uint16_t vp_idx;
1709 uint8_t fc4_type;
1710} fc_port_t;
1711
1712
1713
1714
1715#define FCS_UNCONFIGURED 1
1716#define FCS_DEVICE_DEAD 2
1717#define FCS_DEVICE_LOST 3
1718#define FCS_ONLINE 4
1719
1720static const char * const port_state_str[] = {
1721 "Unknown",
1722 "UNCONFIGURED",
1723 "DEAD",
1724 "LOST",
1725 "ONLINE"
1726};
1727
1728
1729
1730
1731#define FCF_FABRIC_DEVICE BIT_0
1732#define FCF_LOGIN_NEEDED BIT_1
1733#define FCF_FCP2_DEVICE BIT_2
1734#define FCF_ASYNC_SENT BIT_3
1735
1736
1737#define FC_NO_LOOP_ID 0x1000
1738
1739
1740
1741
1742
1743
1744
1745#define CT_REJECT_RESPONSE 0x8001
1746#define CT_ACCEPT_RESPONSE 0x8002
1747#define CT_REASON_INVALID_COMMAND_CODE 0x01
1748#define CT_REASON_CANNOT_PERFORM 0x09
1749#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1750#define CT_EXPL_ALREADY_REGISTERED 0x10
1751
1752#define NS_N_PORT_TYPE 0x01
1753#define NS_NL_PORT_TYPE 0x02
1754#define NS_NX_PORT_TYPE 0x7F
1755
1756#define GA_NXT_CMD 0x100
1757#define GA_NXT_REQ_SIZE (16 + 4)
1758#define GA_NXT_RSP_SIZE (16 + 620)
1759
1760#define GID_PT_CMD 0x1A1
1761#define GID_PT_REQ_SIZE (16 + 4)
1762#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1763
1764#define GPN_ID_CMD 0x112
1765#define GPN_ID_REQ_SIZE (16 + 4)
1766#define GPN_ID_RSP_SIZE (16 + 8)
1767
1768#define GNN_ID_CMD 0x113
1769#define GNN_ID_REQ_SIZE (16 + 4)
1770#define GNN_ID_RSP_SIZE (16 + 8)
1771
1772#define GFT_ID_CMD 0x117
1773#define GFT_ID_REQ_SIZE (16 + 4)
1774#define GFT_ID_RSP_SIZE (16 + 32)
1775
1776#define RFT_ID_CMD 0x217
1777#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1778#define RFT_ID_RSP_SIZE 16
1779
1780#define RFF_ID_CMD 0x21F
1781#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1782#define RFF_ID_RSP_SIZE 16
1783
1784#define RNN_ID_CMD 0x213
1785#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1786#define RNN_ID_RSP_SIZE 16
1787
1788#define RSNN_NN_CMD 0x239
1789#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1790#define RSNN_NN_RSP_SIZE 16
1791
1792#define GFPN_ID_CMD 0x11C
1793#define GFPN_ID_REQ_SIZE (16 + 4)
1794#define GFPN_ID_RSP_SIZE (16 + 8)
1795
1796#define GPSC_CMD 0x127
1797#define GPSC_REQ_SIZE (16 + 8)
1798#define GPSC_RSP_SIZE (16 + 2 + 2)
1799
1800#define GFF_ID_CMD 0x011F
1801#define GFF_ID_REQ_SIZE (16 + 4)
1802#define GFF_ID_RSP_SIZE (16 + 128)
1803
1804
1805
1806
1807#define FDMI_HBA_ATTR_COUNT 9
1808#define FDMI_HBA_NODE_NAME 1
1809#define FDMI_HBA_MANUFACTURER 2
1810#define FDMI_HBA_SERIAL_NUMBER 3
1811#define FDMI_HBA_MODEL 4
1812#define FDMI_HBA_MODEL_DESCRIPTION 5
1813#define FDMI_HBA_HARDWARE_VERSION 6
1814#define FDMI_HBA_DRIVER_VERSION 7
1815#define FDMI_HBA_OPTION_ROM_VERSION 8
1816#define FDMI_HBA_FIRMWARE_VERSION 9
1817#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1818#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1819
1820struct ct_fdmi_hba_attr {
1821 uint16_t type;
1822 uint16_t len;
1823 union {
1824 uint8_t node_name[WWN_SIZE];
1825 uint8_t manufacturer[32];
1826 uint8_t serial_num[8];
1827 uint8_t model[16];
1828 uint8_t model_desc[80];
1829 uint8_t hw_version[16];
1830 uint8_t driver_version[32];
1831 uint8_t orom_version[16];
1832 uint8_t fw_version[16];
1833 uint8_t os_version[128];
1834 uint8_t max_ct_len[4];
1835 } a;
1836};
1837
1838struct ct_fdmi_hba_attributes {
1839 uint32_t count;
1840 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1841};
1842
1843
1844
1845
1846#define FDMI_PORT_ATTR_COUNT 6
1847#define FDMI_PORT_FC4_TYPES 1
1848#define FDMI_PORT_SUPPORT_SPEED 2
1849#define FDMI_PORT_CURRENT_SPEED 3
1850#define FDMI_PORT_MAX_FRAME_SIZE 4
1851#define FDMI_PORT_OS_DEVICE_NAME 5
1852#define FDMI_PORT_HOST_NAME 6
1853
1854#define FDMI_PORT_SPEED_1GB 0x1
1855#define FDMI_PORT_SPEED_2GB 0x2
1856#define FDMI_PORT_SPEED_10GB 0x4
1857#define FDMI_PORT_SPEED_4GB 0x8
1858#define FDMI_PORT_SPEED_8GB 0x10
1859#define FDMI_PORT_SPEED_16GB 0x20
1860#define FDMI_PORT_SPEED_UNKNOWN 0x8000
1861
1862struct ct_fdmi_port_attr {
1863 uint16_t type;
1864 uint16_t len;
1865 union {
1866 uint8_t fc4_types[32];
1867 uint32_t sup_speed;
1868 uint32_t cur_speed;
1869 uint32_t max_frame_size;
1870 uint8_t os_dev_name[32];
1871 uint8_t host_name[32];
1872 } a;
1873};
1874
1875
1876
1877
1878struct ct_fdmi_port_attributes {
1879 uint32_t count;
1880 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1881};
1882
1883
1884#define GRHL_CMD 0x100
1885#define GHAT_CMD 0x101
1886#define GRPL_CMD 0x102
1887#define GPAT_CMD 0x110
1888
1889#define RHBA_CMD 0x200
1890#define RHBA_RSP_SIZE 16
1891
1892#define RHAT_CMD 0x201
1893#define RPRT_CMD 0x210
1894
1895#define RPA_CMD 0x211
1896#define RPA_RSP_SIZE 16
1897
1898#define DHBA_CMD 0x300
1899#define DHBA_REQ_SIZE (16 + 8)
1900#define DHBA_RSP_SIZE 16
1901
1902#define DHAT_CMD 0x301
1903#define DPRT_CMD 0x310
1904#define DPA_CMD 0x311
1905
1906
1907struct ct_cmd_hdr {
1908 uint8_t revision;
1909 uint8_t in_id[3];
1910 uint8_t gs_type;
1911 uint8_t gs_subtype;
1912 uint8_t options;
1913 uint8_t reserved;
1914};
1915
1916
1917struct ct_sns_req {
1918 struct ct_cmd_hdr header;
1919 uint16_t command;
1920 uint16_t max_rsp_size;
1921 uint8_t fragment_id;
1922 uint8_t reserved[3];
1923
1924 union {
1925
1926 struct {
1927 uint8_t reserved;
1928 uint8_t port_id[3];
1929 } port_id;
1930
1931 struct {
1932 uint8_t port_type;
1933 uint8_t domain;
1934 uint8_t area;
1935 uint8_t reserved;
1936 } gid_pt;
1937
1938 struct {
1939 uint8_t reserved;
1940 uint8_t port_id[3];
1941 uint8_t fc4_types[32];
1942 } rft_id;
1943
1944 struct {
1945 uint8_t reserved;
1946 uint8_t port_id[3];
1947 uint16_t reserved2;
1948 uint8_t fc4_feature;
1949 uint8_t fc4_type;
1950 } rff_id;
1951
1952 struct {
1953 uint8_t reserved;
1954 uint8_t port_id[3];
1955 uint8_t node_name[8];
1956 } rnn_id;
1957
1958 struct {
1959 uint8_t node_name[8];
1960 uint8_t name_len;
1961 uint8_t sym_node_name[255];
1962 } rsnn_nn;
1963
1964 struct {
1965 uint8_t hba_indentifier[8];
1966 } ghat;
1967
1968 struct {
1969 uint8_t hba_identifier[8];
1970 uint32_t entry_count;
1971 uint8_t port_name[8];
1972 struct ct_fdmi_hba_attributes attrs;
1973 } rhba;
1974
1975 struct {
1976 uint8_t hba_identifier[8];
1977 struct ct_fdmi_hba_attributes attrs;
1978 } rhat;
1979
1980 struct {
1981 uint8_t port_name[8];
1982 struct ct_fdmi_port_attributes attrs;
1983 } rpa;
1984
1985 struct {
1986 uint8_t port_name[8];
1987 } dhba;
1988
1989 struct {
1990 uint8_t port_name[8];
1991 } dhat;
1992
1993 struct {
1994 uint8_t port_name[8];
1995 } dprt;
1996
1997 struct {
1998 uint8_t port_name[8];
1999 } dpa;
2000
2001 struct {
2002 uint8_t port_name[8];
2003 } gpsc;
2004
2005 struct {
2006 uint8_t reserved;
2007 uint8_t port_name[3];
2008 } gff_id;
2009 } req;
2010};
2011
2012
2013struct ct_rsp_hdr {
2014 struct ct_cmd_hdr header;
2015 uint16_t response;
2016 uint16_t residual;
2017 uint8_t fragment_id;
2018 uint8_t reason_code;
2019 uint8_t explanation_code;
2020 uint8_t vendor_unique;
2021};
2022
2023struct ct_sns_gid_pt_data {
2024 uint8_t control_byte;
2025 uint8_t port_id[3];
2026};
2027
2028struct ct_sns_rsp {
2029 struct ct_rsp_hdr header;
2030
2031 union {
2032 struct {
2033 uint8_t port_type;
2034 uint8_t port_id[3];
2035 uint8_t port_name[8];
2036 uint8_t sym_port_name_len;
2037 uint8_t sym_port_name[255];
2038 uint8_t node_name[8];
2039 uint8_t sym_node_name_len;
2040 uint8_t sym_node_name[255];
2041 uint8_t init_proc_assoc[8];
2042 uint8_t node_ip_addr[16];
2043 uint8_t class_of_service[4];
2044 uint8_t fc4_types[32];
2045 uint8_t ip_address[16];
2046 uint8_t fabric_port_name[8];
2047 uint8_t reserved;
2048 uint8_t hard_address[3];
2049 } ga_nxt;
2050
2051 struct {
2052 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2053 } gid_pt;
2054
2055 struct {
2056 uint8_t port_name[8];
2057 } gpn_id;
2058
2059 struct {
2060 uint8_t node_name[8];
2061 } gnn_id;
2062
2063 struct {
2064 uint8_t fc4_types[32];
2065 } gft_id;
2066
2067 struct {
2068 uint32_t entry_count;
2069 uint8_t port_name[8];
2070 struct ct_fdmi_hba_attributes attrs;
2071 } ghat;
2072
2073 struct {
2074 uint8_t port_name[8];
2075 } gfpn_id;
2076
2077 struct {
2078 uint16_t speeds;
2079 uint16_t speed;
2080 } gpsc;
2081
2082#define GFF_FCP_SCSI_OFFSET 7
2083 struct {
2084 uint8_t fc4_features[128];
2085 } gff_id;
2086 } rsp;
2087};
2088
2089struct ct_sns_pkt {
2090 union {
2091 struct ct_sns_req req;
2092 struct ct_sns_rsp rsp;
2093 } p;
2094};
2095
2096
2097
2098
2099#define RFT_ID_SNS_SCMD_LEN 22
2100#define RFT_ID_SNS_CMD_SIZE 60
2101#define RFT_ID_SNS_DATA_SIZE 16
2102
2103#define RNN_ID_SNS_SCMD_LEN 10
2104#define RNN_ID_SNS_CMD_SIZE 36
2105#define RNN_ID_SNS_DATA_SIZE 16
2106
2107#define GA_NXT_SNS_SCMD_LEN 6
2108#define GA_NXT_SNS_CMD_SIZE 28
2109#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2110
2111#define GID_PT_SNS_SCMD_LEN 6
2112#define GID_PT_SNS_CMD_SIZE 28
2113#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2114
2115#define GPN_ID_SNS_SCMD_LEN 6
2116#define GPN_ID_SNS_CMD_SIZE 28
2117#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2118
2119#define GNN_ID_SNS_SCMD_LEN 6
2120#define GNN_ID_SNS_CMD_SIZE 28
2121#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2122
2123struct sns_cmd_pkt {
2124 union {
2125 struct {
2126 uint16_t buffer_length;
2127 uint16_t reserved_1;
2128 uint32_t buffer_address[2];
2129 uint16_t subcommand_length;
2130 uint16_t reserved_2;
2131 uint16_t subcommand;
2132 uint16_t size;
2133 uint32_t reserved_3;
2134 uint8_t param[36];
2135 } cmd;
2136
2137 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2138 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2139 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2140 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2141 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2142 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2143 } p;
2144};
2145
2146struct fw_blob {
2147 char *name;
2148 uint32_t segs[4];
2149 const struct firmware *fw;
2150};
2151
2152
2153struct gid_list_info {
2154 uint8_t al_pa;
2155 uint8_t area;
2156 uint8_t domain;
2157 uint8_t loop_id_2100;
2158 uint16_t loop_id;
2159 uint16_t reserved_1;
2160};
2161#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2162
2163
2164typedef struct vport_info {
2165 uint8_t port_name[WWN_SIZE];
2166 uint8_t node_name[WWN_SIZE];
2167 int vp_id;
2168 uint16_t loop_id;
2169 unsigned long host_no;
2170 uint8_t port_id[3];
2171 int loop_state;
2172} vport_info_t;
2173
2174typedef struct vport_params {
2175 uint8_t port_name[WWN_SIZE];
2176 uint8_t node_name[WWN_SIZE];
2177 uint32_t options;
2178#define VP_OPTS_RETRY_ENABLE BIT_0
2179#define VP_OPTS_VP_DISABLE BIT_1
2180} vport_params_t;
2181
2182
2183#define VP_RET_CODE_OK 0
2184#define VP_RET_CODE_FATAL 1
2185#define VP_RET_CODE_WRONG_ID 2
2186#define VP_RET_CODE_WWPN 3
2187#define VP_RET_CODE_RESOURCES 4
2188#define VP_RET_CODE_NO_MEM 5
2189#define VP_RET_CODE_NOT_FOUND 6
2190
2191struct qla_hw_data;
2192struct rsp_que;
2193
2194
2195
2196struct isp_operations {
2197
2198 int (*pci_config) (struct scsi_qla_host *);
2199 void (*reset_chip) (struct scsi_qla_host *);
2200 int (*chip_diag) (struct scsi_qla_host *);
2201 void (*config_rings) (struct scsi_qla_host *);
2202 void (*reset_adapter) (struct scsi_qla_host *);
2203 int (*nvram_config) (struct scsi_qla_host *);
2204 void (*update_fw_options) (struct scsi_qla_host *);
2205 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2206
2207 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2208 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2209
2210 irq_handler_t intr_handler;
2211 void (*enable_intrs) (struct qla_hw_data *);
2212 void (*disable_intrs) (struct qla_hw_data *);
2213
2214 int (*abort_command) (srb_t *);
2215 int (*target_reset) (struct fc_port *, unsigned int, int);
2216 int (*lun_reset) (struct fc_port *, unsigned int, int);
2217 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2218 uint8_t, uint8_t, uint16_t *, uint8_t);
2219 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2220 uint8_t, uint8_t);
2221
2222 uint16_t (*calc_req_entries) (uint16_t);
2223 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2224 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2225 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2226 uint32_t);
2227
2228 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2229 uint32_t, uint32_t);
2230 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2231 uint32_t);
2232
2233 void (*fw_dump) (struct scsi_qla_host *, int);
2234
2235 int (*beacon_on) (struct scsi_qla_host *);
2236 int (*beacon_off) (struct scsi_qla_host *);
2237 void (*beacon_blink) (struct scsi_qla_host *);
2238
2239 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2240 uint32_t, uint32_t);
2241 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2242 uint32_t);
2243
2244 int (*get_flash_version) (struct scsi_qla_host *, void *);
2245 int (*start_scsi) (srb_t *);
2246 int (*abort_isp) (struct scsi_qla_host *);
2247};
2248
2249
2250
2251#define QLA_MSIX_CHIP_REV_24XX 3
2252#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2253#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2254
2255#define QLA_MSIX_DEFAULT 0x00
2256#define QLA_MSIX_RSP_Q 0x01
2257
2258#define QLA_MIDX_DEFAULT 0
2259#define QLA_MIDX_RSP_Q 1
2260#define QLA_PCI_MSIX_CONTROL 0xa2
2261
2262struct scsi_qla_host;
2263
2264struct qla_msix_entry {
2265 int have_irq;
2266 uint32_t vector;
2267 uint16_t entry;
2268 struct rsp_que *rsp;
2269};
2270
2271#define WATCH_INTERVAL 1
2272
2273
2274enum qla_work_type {
2275 QLA_EVT_AEN,
2276 QLA_EVT_IDC_ACK,
2277 QLA_EVT_ASYNC_LOGIN,
2278 QLA_EVT_ASYNC_LOGIN_DONE,
2279 QLA_EVT_ASYNC_LOGOUT,
2280 QLA_EVT_ASYNC_LOGOUT_DONE,
2281 QLA_EVT_ASYNC_ADISC,
2282 QLA_EVT_ASYNC_ADISC_DONE,
2283 QLA_EVT_UEVENT,
2284};
2285
2286
2287struct qla_work_evt {
2288 struct list_head list;
2289 enum qla_work_type type;
2290 u32 flags;
2291#define QLA_EVT_FLAG_FREE 0x1
2292
2293 union {
2294 struct {
2295 enum fc_host_event_code code;
2296 u32 data;
2297 } aen;
2298 struct {
2299#define QLA_IDC_ACK_REGS 7
2300 uint16_t mb[QLA_IDC_ACK_REGS];
2301 } idc_ack;
2302 struct {
2303 struct fc_port *fcport;
2304#define QLA_LOGIO_LOGIN_RETRIED BIT_0
2305 u16 data[2];
2306 } logio;
2307 struct {
2308 u32 code;
2309#define QLA_UEVENT_CODE_FW_DUMP 0
2310 } uevent;
2311 } u;
2312};
2313
2314struct qla_chip_state_84xx {
2315 struct list_head list;
2316 struct kref kref;
2317
2318 void *bus;
2319 spinlock_t access_lock;
2320 struct mutex fw_update_mutex;
2321 uint32_t fw_update;
2322 uint32_t op_fw_version;
2323 uint32_t op_fw_size;
2324 uint32_t op_fw_seq_size;
2325 uint32_t diag_fw_version;
2326 uint32_t gold_fw_version;
2327};
2328
2329struct qla_statistics {
2330 uint32_t total_isp_aborts;
2331 uint64_t input_bytes;
2332 uint64_t output_bytes;
2333};
2334
2335
2336#define MBC_INITIALIZE_MULTIQ 0x1f
2337#define QLA_QUE_PAGE 0X1000
2338#define QLA_MQ_SIZE 32
2339#define QLA_MAX_QUEUES 256
2340#define ISP_QUE_REG(ha, id) \
2341 ((ha->mqenable) ? \
2342 ((void *)(ha->mqiobase) +\
2343 (QLA_QUE_PAGE * id)) :\
2344 ((void *)(ha->iobase)))
2345#define QLA_REQ_QUE_ID(tag) \
2346 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2347#define QLA_DEFAULT_QUE_QOS 5
2348#define QLA_PRECONFIG_VPORTS 32
2349#define QLA_MAX_VPORTS_QLA24XX 128
2350#define QLA_MAX_VPORTS_QLA25XX 256
2351
2352struct rsp_que {
2353 dma_addr_t dma;
2354 response_t *ring;
2355 response_t *ring_ptr;
2356 uint32_t __iomem *rsp_q_in;
2357 uint32_t __iomem *rsp_q_out;
2358 uint16_t ring_index;
2359 uint16_t out_ptr;
2360 uint16_t length;
2361 uint16_t options;
2362 uint16_t rid;
2363 uint16_t id;
2364 uint16_t vp_idx;
2365 struct qla_hw_data *hw;
2366 struct qla_msix_entry *msix;
2367 struct req_que *req;
2368 srb_t *status_srb;
2369 struct work_struct q_work;
2370};
2371
2372
2373struct req_que {
2374 dma_addr_t dma;
2375 request_t *ring;
2376 request_t *ring_ptr;
2377 uint32_t __iomem *req_q_in;
2378 uint32_t __iomem *req_q_out;
2379 uint16_t ring_index;
2380 uint16_t in_ptr;
2381 uint16_t cnt;
2382 uint16_t length;
2383 uint16_t options;
2384 uint16_t rid;
2385 uint16_t id;
2386 uint16_t qos;
2387 uint16_t vp_idx;
2388 struct rsp_que *rsp;
2389 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2390 uint32_t current_outstanding_cmd;
2391 int max_q_depth;
2392};
2393
2394
2395struct qlfc_fw {
2396 void *fw_buf;
2397 dma_addr_t fw_dma;
2398 uint32_t len;
2399};
2400
2401
2402
2403
2404struct qla_hw_data {
2405 struct pci_dev *pdev;
2406
2407#define SRB_MIN_REQ 128
2408 mempool_t *srb_mempool;
2409
2410 volatile struct {
2411 uint32_t mbox_int :1;
2412 uint32_t mbox_busy :1;
2413 uint32_t disable_risc_code_load :1;
2414 uint32_t enable_64bit_addressing :1;
2415 uint32_t enable_lip_reset :1;
2416 uint32_t enable_target_reset :1;
2417 uint32_t enable_lip_full_login :1;
2418 uint32_t enable_led_scheme :1;
2419
2420 uint32_t msi_enabled :1;
2421 uint32_t msix_enabled :1;
2422 uint32_t disable_serdes :1;
2423 uint32_t gpsc_supported :1;
2424 uint32_t npiv_supported :1;
2425 uint32_t pci_channel_io_perm_failure :1;
2426 uint32_t fce_enabled :1;
2427 uint32_t fac_supported :1;
2428
2429 uint32_t chip_reset_done :1;
2430 uint32_t port0 :1;
2431 uint32_t running_gold_fw :1;
2432 uint32_t eeh_busy :1;
2433 uint32_t cpu_affinity_enabled :1;
2434 uint32_t disable_msix_handshake :1;
2435 uint32_t fcp_prio_enabled :1;
2436 uint32_t isp82xx_fw_hung:1;
2437
2438 uint32_t quiesce_owner:1;
2439 uint32_t thermal_supported:1;
2440 uint32_t isp82xx_reset_hdlr_active:1;
2441
2442 } flags;
2443
2444
2445
2446
2447
2448
2449
2450
2451 spinlock_t hardware_lock ____cacheline_aligned;
2452 int bars;
2453 int mem_only;
2454 device_reg_t __iomem *iobase;
2455 resource_size_t pio_address;
2456
2457#define MIN_IOBASE_LEN 0x100
2458
2459 device_reg_t __iomem *mqiobase;
2460 uint16_t msix_count;
2461 uint8_t mqenable;
2462 struct req_que **req_q_map;
2463 struct rsp_que **rsp_q_map;
2464 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2465 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2466 uint8_t max_req_queues;
2467 uint8_t max_rsp_queues;
2468 struct qla_npiv_entry *npiv_info;
2469 uint16_t nvram_npiv_size;
2470
2471 uint16_t switch_cap;
2472#define FLOGI_SEQ_DEL BIT_8
2473#define FLOGI_MID_SUPPORT BIT_10
2474#define FLOGI_VSAN_SUPPORT BIT_12
2475#define FLOGI_SP_SUPPORT BIT_13
2476
2477 uint8_t port_no;
2478
2479
2480 uint8_t loop_down_abort_time;
2481 atomic_t loop_down_timer;
2482 uint8_t link_down_timeout;
2483 uint16_t max_loop_id;
2484
2485 uint16_t fb_rev;
2486 uint16_t min_external_loopid;
2487
2488#define PORT_SPEED_UNKNOWN 0xFFFF
2489#define PORT_SPEED_1GB 0x00
2490#define PORT_SPEED_2GB 0x01
2491#define PORT_SPEED_4GB 0x03
2492#define PORT_SPEED_8GB 0x04
2493#define PORT_SPEED_10GB 0x13
2494 uint16_t link_data_rate;
2495
2496 uint8_t current_topology;
2497 uint8_t prev_topology;
2498#define ISP_CFG_NL 1
2499#define ISP_CFG_N 2
2500#define ISP_CFG_FL 4
2501#define ISP_CFG_F 8
2502
2503 uint8_t operating_mode;
2504#define LOOP 0
2505#define P2P 1
2506#define LOOP_P2P 2
2507#define P2P_LOOP 3
2508 uint8_t interrupts_on;
2509 uint32_t isp_abort_cnt;
2510
2511#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2512#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2513#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2514 uint32_t device_type;
2515#define DT_ISP2100 BIT_0
2516#define DT_ISP2200 BIT_1
2517#define DT_ISP2300 BIT_2
2518#define DT_ISP2312 BIT_3
2519#define DT_ISP2322 BIT_4
2520#define DT_ISP6312 BIT_5
2521#define DT_ISP6322 BIT_6
2522#define DT_ISP2422 BIT_7
2523#define DT_ISP2432 BIT_8
2524#define DT_ISP5422 BIT_9
2525#define DT_ISP5432 BIT_10
2526#define DT_ISP2532 BIT_11
2527#define DT_ISP8432 BIT_12
2528#define DT_ISP8001 BIT_13
2529#define DT_ISP8021 BIT_14
2530#define DT_ISP_LAST (DT_ISP8021 << 1)
2531
2532#define DT_T10_PI BIT_25
2533#define DT_IIDMA BIT_26
2534#define DT_FWI2 BIT_27
2535#define DT_ZIO_SUPPORTED BIT_28
2536#define DT_OEM_001 BIT_29
2537#define DT_ISP2200A BIT_30
2538#define DT_EXTENDED_IDS BIT_31
2539#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2540#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2541#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2542#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2543#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2544#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2545#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2546#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2547#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2548#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2549#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2550#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2551#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2552#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2553#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2554#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2555
2556#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2557 IS_QLA6312(ha) || IS_QLA6322(ha))
2558#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2559#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2560#define IS_QLA25XX(ha) (IS_QLA2532(ha))
2561#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2562#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2563 IS_QLA84XX(ha))
2564#define IS_QLA81XX(ha) (IS_QLA8001(ha))
2565#define IS_QLA8XXX_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha))
2566#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2567 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2568 IS_QLA82XX(ha))
2569#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha))
2570#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2571 (ha)->flags.msix_enabled)
2572#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2573#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2574#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2575
2576#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
2577#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2578#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2579#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2580#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2581#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2582
2583
2584 uint8_t serial0;
2585 uint8_t serial1;
2586 uint8_t serial2;
2587
2588
2589#define MAX_NVRAM_SIZE 4096
2590#define VPD_OFFSET MAX_NVRAM_SIZE / 2
2591 uint16_t nvram_size;
2592 uint16_t nvram_base;
2593 void *nvram;
2594 uint16_t vpd_size;
2595 uint16_t vpd_base;
2596 void *vpd;
2597
2598 uint16_t loop_reset_delay;
2599 uint8_t retry_count;
2600 uint8_t login_timeout;
2601 uint16_t r_a_tov;
2602 int port_down_retry_count;
2603 uint8_t mbx_count;
2604
2605 uint32_t login_retry_count;
2606
2607 ms_iocb_entry_t *ms_iocb;
2608 dma_addr_t ms_iocb_dma;
2609 struct ct_sns_pkt *ct_sns;
2610 dma_addr_t ct_sns_dma;
2611
2612 struct sns_cmd_pkt *sns_cmd;
2613 dma_addr_t sns_cmd_dma;
2614
2615#define SFP_DEV_SIZE 256
2616#define SFP_BLOCK_SIZE 64
2617 void *sfp_data;
2618 dma_addr_t sfp_data_dma;
2619
2620 uint8_t *edc_data;
2621 dma_addr_t edc_data_dma;
2622 uint16_t edc_data_len;
2623
2624#define XGMAC_DATA_SIZE 4096
2625 void *xgmac_data;
2626 dma_addr_t xgmac_data_dma;
2627
2628#define DCBX_TLV_DATA_SIZE 4096
2629 void *dcbx_tlv;
2630 dma_addr_t dcbx_tlv_dma;
2631
2632 struct task_struct *dpc_thread;
2633 uint8_t dpc_active;
2634
2635 dma_addr_t gid_list_dma;
2636 struct gid_list_info *gid_list;
2637 int gid_list_info_size;
2638
2639
2640#define DMA_POOL_SIZE 256
2641 struct dma_pool *s_dma_pool;
2642
2643 dma_addr_t init_cb_dma;
2644 init_cb_t *init_cb;
2645 int init_cb_size;
2646 dma_addr_t ex_init_cb_dma;
2647 struct ex_init_cb_81xx *ex_init_cb;
2648
2649 void *async_pd;
2650 dma_addr_t async_pd_dma;
2651
2652
2653 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2654
2655 mbx_cmd_t *mcp;
2656 unsigned long mbx_cmd_flags;
2657#define MBX_INTERRUPT 1
2658#define MBX_INTR_WAIT 2
2659#define MBX_UPDATE_FLASH_ACTIVE 3
2660
2661 struct mutex vport_lock;
2662 spinlock_t vport_slock;
2663 struct completion mbx_cmd_comp;
2664 struct completion mbx_intr_comp;
2665 struct completion dcbx_comp;
2666 int notify_dcbx_comp;
2667
2668
2669 uint16_t fw_major_version;
2670 uint16_t fw_minor_version;
2671 uint16_t fw_subminor_version;
2672 uint16_t fw_attributes;
2673 uint32_t fw_memory_size;
2674 uint32_t fw_transfer_size;
2675 uint32_t fw_srisc_address;
2676#define RISC_START_ADDRESS_2100 0x1000
2677#define RISC_START_ADDRESS_2300 0x800
2678#define RISC_START_ADDRESS_2400 0x100000
2679 uint16_t fw_xcb_count;
2680
2681 uint16_t fw_options[16];
2682 uint8_t fw_seriallink_options[4];
2683 uint16_t fw_seriallink_options24[4];
2684
2685 uint8_t mpi_version[3];
2686 uint32_t mpi_capabilities;
2687 uint8_t phy_version[3];
2688
2689
2690 struct qla2xxx_fw_dump *fw_dump;
2691 uint32_t fw_dump_len;
2692 int fw_dumped;
2693 int fw_dump_reading;
2694 dma_addr_t eft_dma;
2695 void *eft;
2696
2697 uint32_t chain_offset;
2698 struct dentry *dfs_dir;
2699 struct dentry *dfs_fce;
2700 dma_addr_t fce_dma;
2701 void *fce;
2702 uint32_t fce_bufs;
2703 uint16_t fce_mb[8];
2704 uint64_t fce_wr, fce_rd;
2705 struct mutex fce_mutex;
2706
2707 uint32_t pci_attr;
2708 uint16_t chip_revision;
2709
2710 uint16_t product_id[4];
2711
2712 uint8_t model_number[16+1];
2713#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2714 char model_desc[80];
2715 uint8_t adapter_id[16+1];
2716
2717
2718 char *optrom_buffer;
2719 uint32_t optrom_size;
2720 int optrom_state;
2721#define QLA_SWAITING 0
2722#define QLA_SREADING 1
2723#define QLA_SWRITING 2
2724 uint32_t optrom_region_start;
2725 uint32_t optrom_region_size;
2726
2727
2728#define ROM_CODE_TYPE_BIOS 0
2729#define ROM_CODE_TYPE_FCODE 1
2730#define ROM_CODE_TYPE_EFI 3
2731 uint8_t bios_revision[2];
2732 uint8_t efi_revision[2];
2733 uint8_t fcode_revision[16];
2734 uint32_t fw_revision[4];
2735
2736 uint32_t gold_fw_version[4];
2737
2738
2739 uint32_t flash_conf_off;
2740 uint32_t flash_data_off;
2741 uint32_t nvram_conf_off;
2742 uint32_t nvram_data_off;
2743
2744 uint32_t fdt_wrt_disable;
2745 uint32_t fdt_erase_cmd;
2746 uint32_t fdt_block_size;
2747 uint32_t fdt_unprotect_sec_cmd;
2748 uint32_t fdt_protect_sec_cmd;
2749
2750 uint32_t flt_region_flt;
2751 uint32_t flt_region_fdt;
2752 uint32_t flt_region_boot;
2753 uint32_t flt_region_fw;
2754 uint32_t flt_region_vpd_nvram;
2755 uint32_t flt_region_vpd;
2756 uint32_t flt_region_nvram;
2757 uint32_t flt_region_npiv_conf;
2758 uint32_t flt_region_gold_fw;
2759 uint32_t flt_region_fcp_prio;
2760 uint32_t flt_region_bootload;
2761
2762
2763 uint16_t beacon_blink_led;
2764 uint8_t beacon_color_state;
2765#define QLA_LED_GRN_ON 0x01
2766#define QLA_LED_YLW_ON 0x02
2767#define QLA_LED_ABR_ON 0x04
2768#define QLA_LED_ALL_ON 0x07
2769
2770 uint16_t zio_mode;
2771 uint16_t zio_timer;
2772 struct fc_host_statistics fc_host_stat;
2773
2774 struct qla_msix_entry *msix_entries;
2775
2776 struct list_head vp_list;
2777 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2778 sizeof(unsigned long)];
2779 uint16_t num_vhosts;
2780 uint16_t num_vsans;
2781 uint16_t max_npiv_vports;
2782 int cur_vport_count;
2783
2784 struct qla_chip_state_84xx *cs84xx;
2785 struct qla_statistics qla_stats;
2786 struct isp_operations *isp_ops;
2787 struct workqueue_struct *wq;
2788 struct qlfc_fw fw_buf;
2789
2790
2791 struct qla_fcp_prio_cfg *fcp_prio_cfg;
2792
2793 struct dma_pool *dl_dma_pool;
2794#define DSD_LIST_DMA_POOL_SIZE 512
2795
2796 struct dma_pool *fcp_cmnd_dma_pool;
2797 mempool_t *ctx_mempool;
2798#define FCP_CMND_DMA_POOL_SIZE 512
2799
2800 unsigned long nx_pcibase;
2801 uint8_t *nxdb_rd_ptr;
2802 unsigned long nxdb_wr_ptr;
2803
2804 uint32_t crb_win;
2805 uint32_t curr_window;
2806 uint32_t ddr_mn_window;
2807 unsigned long mn_win_crb;
2808 unsigned long ms_win_crb;
2809 int qdr_sn_window;
2810 uint32_t nx_dev_init_timeout;
2811 uint32_t nx_reset_timeout;
2812 rwlock_t hw_lock;
2813 uint16_t portnum;
2814 int link_width;
2815 struct fw_blob *hablob;
2816 struct qla82xx_legacy_intr_set nx_legacy_intr;
2817
2818 uint16_t gbl_dsd_inuse;
2819 uint16_t gbl_dsd_avail;
2820 struct list_head gbl_dsd_list;
2821#define NUM_DSD_CHAIN 4096
2822
2823 uint8_t fw_type;
2824 __le32 file_prd_off;
2825};
2826
2827
2828
2829
2830typedef struct scsi_qla_host {
2831 struct list_head list;
2832 struct list_head vp_fcports;
2833 struct list_head work_list;
2834 spinlock_t work_lock;
2835
2836
2837 struct Scsi_Host *host;
2838 unsigned long host_no;
2839 uint8_t host_str[16];
2840
2841 volatile struct {
2842 uint32_t init_done :1;
2843 uint32_t online :1;
2844 uint32_t rscn_queue_overflow :1;
2845 uint32_t reset_active :1;
2846
2847 uint32_t management_server_logged_in :1;
2848 uint32_t process_response_queue :1;
2849 uint32_t difdix_supported:1;
2850 uint32_t delete_progress:1;
2851 } flags;
2852
2853 atomic_t loop_state;
2854#define LOOP_TIMEOUT 1
2855#define LOOP_DOWN 2
2856#define LOOP_UP 3
2857#define LOOP_UPDATE 4
2858#define LOOP_READY 5
2859#define LOOP_DEAD 6
2860
2861 unsigned long dpc_flags;
2862#define RESET_MARKER_NEEDED 0
2863#define RESET_ACTIVE 1
2864#define ISP_ABORT_NEEDED 2
2865#define ABORT_ISP_ACTIVE 3
2866#define LOOP_RESYNC_NEEDED 4
2867#define LOOP_RESYNC_ACTIVE 5
2868#define LOCAL_LOOP_UPDATE 6
2869#define RSCN_UPDATE 7
2870#define RELOGIN_NEEDED 8
2871#define REGISTER_FC4_NEEDED 9
2872#define ISP_ABORT_RETRY 10
2873#define BEACON_BLINK_NEEDED 11
2874#define REGISTER_FDMI_NEEDED 12
2875#define FCPORT_UPDATE_NEEDED 13
2876#define VP_DPC_NEEDED 14
2877#define UNLOADING 15
2878#define NPIV_CONFIG_NEEDED 16
2879#define ISP_UNRECOVERABLE 17
2880#define FCOE_CTX_RESET_NEEDED 18
2881#define MPI_RESET_NEEDED 19
2882#define ISP_QUIESCE_NEEDED 20
2883
2884 uint32_t device_flags;
2885#define SWITCH_FOUND BIT_0
2886#define DFLG_NO_CABLE BIT_1
2887#define DFLG_DEV_FAILED BIT_5
2888
2889
2890 uint16_t loop_id;
2891
2892 port_id_t d_id;
2893 uint8_t marker_needed;
2894 uint16_t mgmt_svr_loop_id;
2895
2896
2897
2898
2899 uint32_t rscn_queue[MAX_RSCN_COUNT];
2900 uint8_t rscn_in_ptr;
2901 uint8_t rscn_out_ptr;
2902
2903
2904 uint8_t loop_down_abort_time;
2905 atomic_t loop_down_timer;
2906 uint8_t link_down_timeout;
2907
2908 uint32_t timer_active;
2909 struct timer_list timer;
2910
2911 uint8_t node_name[WWN_SIZE];
2912 uint8_t port_name[WWN_SIZE];
2913 uint8_t fabric_node_name[WWN_SIZE];
2914
2915 uint16_t fcoe_vlan_id;
2916 uint16_t fcoe_fcf_idx;
2917 uint8_t fcoe_vn_port_mac[6];
2918
2919 uint32_t vp_abort_cnt;
2920
2921 struct fc_vport *fc_vport;
2922 uint16_t vp_idx;
2923
2924 unsigned long vp_flags;
2925#define VP_IDX_ACQUIRED 0
2926#define VP_CREATE_NEEDED 1
2927#define VP_BIND_NEEDED 2
2928#define VP_DELETE_NEEDED 3
2929#define VP_SCR_NEEDED 4
2930 atomic_t vp_state;
2931#define VP_OFFLINE 0
2932#define VP_ACTIVE 1
2933#define VP_FAILED 2
2934
2935 uint16_t vp_err_state;
2936 uint16_t vp_prev_err_state;
2937#define VP_ERR_UNKWN 0
2938#define VP_ERR_PORTDWN 1
2939#define VP_ERR_FAB_UNSUPPORTED 2
2940#define VP_ERR_FAB_NORESOURCES 3
2941#define VP_ERR_FAB_LOGOUT 4
2942#define VP_ERR_ADAP_NORESOURCES 5
2943 struct qla_hw_data *hw;
2944 struct req_que *req;
2945 int fw_heartbeat_counter;
2946 int seconds_since_last_heartbeat;
2947
2948 atomic_t vref_count;
2949} scsi_qla_host_t;
2950
2951
2952
2953
2954#define LOOP_TRANSITION(ha) \
2955 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2956 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2957 atomic_read(&ha->loop_state) == LOOP_DOWN)
2958
2959#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
2960 atomic_inc(&__vha->vref_count); \
2961 mb(); \
2962 if (__vha->flags.delete_progress) { \
2963 atomic_dec(&__vha->vref_count); \
2964 __bail = 1; \
2965 } else { \
2966 __bail = 0; \
2967 } \
2968} while (0)
2969
2970#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
2971 atomic_dec(&__vha->vref_count); \
2972} while (0)
2973
2974
2975#define qla_printk(level, ha, format, arg...) \
2976 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2977
2978
2979
2980
2981#define MBS_MASK 0x3fff
2982
2983#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2984#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2985#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2986#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2987#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2988#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2989#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2990#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2991#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2992#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2993
2994#define QLA_FUNCTION_TIMEOUT 0x100
2995#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2996#define QLA_FUNCTION_FAILED 0x102
2997#define QLA_MEMORY_ALLOC_FAILED 0x103
2998#define QLA_LOCK_TIMEOUT 0x104
2999#define QLA_ABORTED 0x105
3000#define QLA_SUSPENDED 0x106
3001#define QLA_BUSY 0x107
3002#define QLA_RSCNS_HANDLED 0x108
3003#define QLA_ALREADY_REGISTERED 0x109
3004
3005#define NVRAM_DELAY() udelay(10)
3006
3007#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
3008
3009
3010
3011
3012#define OPTROM_SIZE_2300 0x20000
3013#define OPTROM_SIZE_2322 0x100000
3014#define OPTROM_SIZE_24XX 0x100000
3015#define OPTROM_SIZE_25XX 0x200000
3016#define OPTROM_SIZE_81XX 0x400000
3017#define OPTROM_SIZE_82XX 0x800000
3018
3019#define OPTROM_BURST_SIZE 0x1000
3020#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3021
3022#define QLA_DSDS_PER_IOCB 37
3023
3024#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3025
3026#define QLA_SG_ALL 1024
3027
3028enum nexus_wait_type {
3029 WAIT_HOST = 0,
3030 WAIT_TARGET,
3031 WAIT_LUN,
3032};
3033
3034#include "qla_gbl.h"
3035#include "qla_dbg.h"
3036#include "qla_inline.h"
3037#endif
3038