1
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5
6
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
11#include <linux/delay.h>
12#include <linux/kthread.h>
13#include <linux/mutex.h>
14#include <linux/kobject.h>
15#include <linux/slab.h>
16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22
23
24
25char qla2x00_version_str[40];
26
27static int apidev_major;
28
29
30
31
32static struct kmem_cache *srb_cachep;
33
34
35
36
37static struct kmem_cache *ctx_cachep;
38
39
40
41int ql_errlev = ql_log_all;
42
43int ql2xlogintimeout = 20;
44module_param(ql2xlogintimeout, int, S_IRUGO);
45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
48int qlport_down_retry;
49module_param(qlport_down_retry, int, S_IRUGO);
50MODULE_PARM_DESC(qlport_down_retry,
51 "Maximum number of command retries to a port that returns "
52 "a PORT-DOWN status.");
53
54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
58 "a Fabric scan. This is needed for several broken switches. "
59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
61int ql2xloginretrycount = 0;
62module_param(ql2xloginretrycount, int, S_IRUGO);
63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
66int ql2xallocfwdump = 1;
67module_param(ql2xallocfwdump, int, S_IRUGO);
68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
73int ql2xextended_error_logging;
74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(ql2xextended_error_logging,
76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\tDo LOGICAL OR of the value to enable more than one level");
87
88int ql2xshiftctondsd = 6;
89module_param(ql2xshiftctondsd, int, S_IRUGO);
90MODULE_PARM_DESC(ql2xshiftctondsd,
91 "Set to control shifting of command type processing "
92 "based on total number of SG elements.");
93
94static void qla2x00_free_device(scsi_qla_host_t *);
95
96int ql2xfdmienable=1;
97module_param(ql2xfdmienable, int, S_IRUGO);
98MODULE_PARM_DESC(ql2xfdmienable,
99 "Enables FDMI registrations. "
100 "0 - no FDMI. Default is 1 - perform FDMI.");
101
102#define MAX_Q_DEPTH 32
103static int ql2xmaxqdepth = MAX_Q_DEPTH;
104module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(ql2xmaxqdepth,
106 "Maximum queue depth to report for target devices.");
107
108
109int ql2xenabledif = 0;
110module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
111MODULE_PARM_DESC(ql2xenabledif,
112 " Enable T10-CRC-DIF "
113 " Default is 0 - No DIF Support. 1 - Enable it"
114 ", 2 - Enable DIF for all types, except Type 0.");
115
116int ql2xenablehba_err_chk = 2;
117module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xenablehba_err_chk,
119 " Enable T10-CRC-DIF Error isolation by HBA:\n"
120 " Default is 1.\n"
121 " 0 -- Error isolation disabled\n"
122 " 1 -- Error isolation enabled only for DIX Type 0\n"
123 " 2 -- Error isolation enabled for all Types\n");
124
125int ql2xiidmaenable=1;
126module_param(ql2xiidmaenable, int, S_IRUGO);
127MODULE_PARM_DESC(ql2xiidmaenable,
128 "Enables iIDMA settings "
129 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
130
131int ql2xmaxqueues = 1;
132module_param(ql2xmaxqueues, int, S_IRUGO);
133MODULE_PARM_DESC(ql2xmaxqueues,
134 "Enables MQ settings "
135 "Default is 1 for single queue. Set it to number "
136 "of queues in MQ mode.");
137
138int ql2xmultique_tag;
139module_param(ql2xmultique_tag, int, S_IRUGO);
140MODULE_PARM_DESC(ql2xmultique_tag,
141 "Enables CPU affinity settings for the driver "
142 "Default is 0 for no affinity of request and response IO. "
143 "Set it to 1 to turn on the cpu affinity.");
144
145int ql2xfwloadbin;
146module_param(ql2xfwloadbin, int, S_IRUGO);
147MODULE_PARM_DESC(ql2xfwloadbin,
148 "Option to specify location from which to load ISP firmware:.\n"
149 " 2 -- load firmware via the request_firmware() (hotplug).\n"
150 " interface.\n"
151 " 1 -- load firmware from flash.\n"
152 " 0 -- use default semantics.\n");
153
154int ql2xetsenable;
155module_param(ql2xetsenable, int, S_IRUGO);
156MODULE_PARM_DESC(ql2xetsenable,
157 "Enables firmware ETS burst."
158 "Default is 0 - skip ETS enablement.");
159
160int ql2xdbwr = 1;
161module_param(ql2xdbwr, int, S_IRUGO);
162MODULE_PARM_DESC(ql2xdbwr,
163 "Option to specify scheme for request queue posting.\n"
164 " 0 -- Regular doorbell.\n"
165 " 1 -- CAMRAM doorbell (faster).\n");
166
167int ql2xtargetreset = 1;
168module_param(ql2xtargetreset, int, S_IRUGO);
169MODULE_PARM_DESC(ql2xtargetreset,
170 "Enable target reset."
171 "Default is 1 - use hw defaults.");
172
173int ql2xgffidenable;
174module_param(ql2xgffidenable, int, S_IRUGO);
175MODULE_PARM_DESC(ql2xgffidenable,
176 "Enables GFF_ID checks of port type. "
177 "Default is 0 - Do not use GFF_ID information.");
178
179int ql2xasynctmfenable;
180module_param(ql2xasynctmfenable, int, S_IRUGO);
181MODULE_PARM_DESC(ql2xasynctmfenable,
182 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
183 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
184
185int ql2xdontresethba;
186module_param(ql2xdontresethba, int, S_IRUGO);
187MODULE_PARM_DESC(ql2xdontresethba,
188 "Option to specify reset behaviour.\n"
189 " 0 (Default) -- Reset on failure.\n"
190 " 1 -- Do not reset on failure.\n");
191
192uint ql2xmaxlun = MAX_LUNS;
193module_param(ql2xmaxlun, uint, S_IRUGO);
194MODULE_PARM_DESC(ql2xmaxlun,
195 "Defines the maximum LU number to register with the SCSI "
196 "midlayer. Default is 65535.");
197
198
199
200
201static int qla2xxx_slave_configure(struct scsi_device * device);
202static int qla2xxx_slave_alloc(struct scsi_device *);
203static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
204static void qla2xxx_scan_start(struct Scsi_Host *);
205static void qla2xxx_slave_destroy(struct scsi_device *);
206static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
207static int qla2xxx_eh_abort(struct scsi_cmnd *);
208static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
209static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
210static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
211static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
212
213static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
214static int qla2x00_change_queue_type(struct scsi_device *, int);
215
216struct scsi_host_template qla2xxx_driver_template = {
217 .module = THIS_MODULE,
218 .name = QLA2XXX_DRIVER_NAME,
219 .queuecommand = qla2xxx_queuecommand,
220
221 .eh_abort_handler = qla2xxx_eh_abort,
222 .eh_device_reset_handler = qla2xxx_eh_device_reset,
223 .eh_target_reset_handler = qla2xxx_eh_target_reset,
224 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
225 .eh_host_reset_handler = qla2xxx_eh_host_reset,
226
227 .slave_configure = qla2xxx_slave_configure,
228
229 .slave_alloc = qla2xxx_slave_alloc,
230 .slave_destroy = qla2xxx_slave_destroy,
231 .scan_finished = qla2xxx_scan_finished,
232 .scan_start = qla2xxx_scan_start,
233 .change_queue_depth = qla2x00_change_queue_depth,
234 .change_queue_type = qla2x00_change_queue_type,
235 .this_id = -1,
236 .cmd_per_lun = 3,
237 .use_clustering = ENABLE_CLUSTERING,
238 .sg_tablesize = SG_ALL,
239
240 .max_sectors = 0xFFFF,
241 .shost_attrs = qla2x00_host_attrs,
242};
243
244static struct scsi_transport_template *qla2xxx_transport_template = NULL;
245struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
246
247
248
249
250
251
252__inline__ void
253qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
254{
255 init_timer(&vha->timer);
256 vha->timer.expires = jiffies + interval * HZ;
257 vha->timer.data = (unsigned long)vha;
258 vha->timer.function = (void (*)(unsigned long))func;
259 add_timer(&vha->timer);
260 vha->timer_active = 1;
261}
262
263static inline void
264qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
265{
266
267 if (vha->device_flags & DFLG_DEV_FAILED) {
268 ql_dbg(ql_dbg_timer, vha, 0x600d,
269 "Device in a failed state, returning.\n");
270 return;
271 }
272
273 mod_timer(&vha->timer, jiffies + interval * HZ);
274}
275
276static __inline__ void
277qla2x00_stop_timer(scsi_qla_host_t *vha)
278{
279 del_timer_sync(&vha->timer);
280 vha->timer_active = 0;
281}
282
283static int qla2x00_do_dpc(void *data);
284
285static void qla2x00_rst_aen(scsi_qla_host_t *);
286
287static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
288 struct req_que **, struct rsp_que **);
289static void qla2x00_free_fw_dump(struct qla_hw_data *);
290static void qla2x00_mem_free(struct qla_hw_data *);
291static void qla2x00_sp_free_dma(srb_t *);
292
293
294static int qla2x00_alloc_queues(struct qla_hw_data *ha)
295{
296 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
297 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
298 GFP_KERNEL);
299 if (!ha->req_q_map) {
300 ql_log(ql_log_fatal, vha, 0x003b,
301 "Unable to allocate memory for request queue ptrs.\n");
302 goto fail_req_map;
303 }
304
305 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
306 GFP_KERNEL);
307 if (!ha->rsp_q_map) {
308 ql_log(ql_log_fatal, vha, 0x003c,
309 "Unable to allocate memory for response queue ptrs.\n");
310 goto fail_rsp_map;
311 }
312 set_bit(0, ha->rsp_qid_map);
313 set_bit(0, ha->req_qid_map);
314 return 1;
315
316fail_rsp_map:
317 kfree(ha->req_q_map);
318 ha->req_q_map = NULL;
319fail_req_map:
320 return -ENOMEM;
321}
322
323static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
324{
325 if (req && req->ring)
326 dma_free_coherent(&ha->pdev->dev,
327 (req->length + 1) * sizeof(request_t),
328 req->ring, req->dma);
329
330 kfree(req);
331 req = NULL;
332}
333
334static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
335{
336 if (rsp && rsp->ring)
337 dma_free_coherent(&ha->pdev->dev,
338 (rsp->length + 1) * sizeof(response_t),
339 rsp->ring, rsp->dma);
340
341 kfree(rsp);
342 rsp = NULL;
343}
344
345static void qla2x00_free_queues(struct qla_hw_data *ha)
346{
347 struct req_que *req;
348 struct rsp_que *rsp;
349 int cnt;
350
351 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
352 req = ha->req_q_map[cnt];
353 qla2x00_free_req_que(ha, req);
354 }
355 kfree(ha->req_q_map);
356 ha->req_q_map = NULL;
357
358 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
359 rsp = ha->rsp_q_map[cnt];
360 qla2x00_free_rsp_que(ha, rsp);
361 }
362 kfree(ha->rsp_q_map);
363 ha->rsp_q_map = NULL;
364}
365
366static int qla25xx_setup_mode(struct scsi_qla_host *vha)
367{
368 uint16_t options = 0;
369 int ques, req, ret;
370 struct qla_hw_data *ha = vha->hw;
371
372 if (!(ha->fw_attributes & BIT_6)) {
373 ql_log(ql_log_warn, vha, 0x00d8,
374 "Firmware is not multi-queue capable.\n");
375 goto fail;
376 }
377 if (ql2xmultique_tag) {
378
379 options |= BIT_7;
380 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
381 QLA_DEFAULT_QUE_QOS);
382 if (!req) {
383 ql_log(ql_log_warn, vha, 0x00e0,
384 "Failed to create request queue.\n");
385 goto fail;
386 }
387 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
388 vha->req = ha->req_q_map[req];
389 options |= BIT_1;
390 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
391 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
392 if (!ret) {
393 ql_log(ql_log_warn, vha, 0x00e8,
394 "Failed to create response queue.\n");
395 goto fail2;
396 }
397 }
398 ha->flags.cpu_affinity_enabled = 1;
399 ql_dbg(ql_dbg_multiq, vha, 0xc007,
400 "CPU affinity mode enalbed, "
401 "no. of response queues:%d no. of request queues:%d.\n",
402 ha->max_rsp_queues, ha->max_req_queues);
403 ql_dbg(ql_dbg_init, vha, 0x00e9,
404 "CPU affinity mode enalbed, "
405 "no. of response queues:%d no. of request queues:%d.\n",
406 ha->max_rsp_queues, ha->max_req_queues);
407 }
408 return 0;
409fail2:
410 qla25xx_delete_queues(vha);
411 destroy_workqueue(ha->wq);
412 ha->wq = NULL;
413fail:
414 ha->mqenable = 0;
415 kfree(ha->req_q_map);
416 kfree(ha->rsp_q_map);
417 ha->max_req_queues = ha->max_rsp_queues = 1;
418 return 1;
419}
420
421static char *
422qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
423{
424 struct qla_hw_data *ha = vha->hw;
425 static char *pci_bus_modes[] = {
426 "33", "66", "100", "133",
427 };
428 uint16_t pci_bus;
429
430 strcpy(str, "PCI");
431 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
432 if (pci_bus) {
433 strcat(str, "-X (");
434 strcat(str, pci_bus_modes[pci_bus]);
435 } else {
436 pci_bus = (ha->pci_attr & BIT_8) >> 8;
437 strcat(str, " (");
438 strcat(str, pci_bus_modes[pci_bus]);
439 }
440 strcat(str, " MHz)");
441
442 return (str);
443}
444
445static char *
446qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
447{
448 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
449 struct qla_hw_data *ha = vha->hw;
450 uint32_t pci_bus;
451 int pcie_reg;
452
453 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
454 if (pcie_reg) {
455 char lwstr[6];
456 uint16_t pcie_lstat, lspeed, lwidth;
457
458 pcie_reg += 0x12;
459 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
460 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
461 lwidth = (pcie_lstat &
462 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
463
464 strcpy(str, "PCIe (");
465 if (lspeed == 1)
466 strcat(str, "2.5GT/s ");
467 else if (lspeed == 2)
468 strcat(str, "5.0GT/s ");
469 else
470 strcat(str, "<unknown> ");
471 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
472 strcat(str, lwstr);
473
474 return str;
475 }
476
477 strcpy(str, "PCI");
478 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
479 if (pci_bus == 0 || pci_bus == 8) {
480 strcat(str, " (");
481 strcat(str, pci_bus_modes[pci_bus >> 3]);
482 } else {
483 strcat(str, "-X ");
484 if (pci_bus & BIT_2)
485 strcat(str, "Mode 2");
486 else
487 strcat(str, "Mode 1");
488 strcat(str, " (");
489 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
490 }
491 strcat(str, " MHz)");
492
493 return str;
494}
495
496static char *
497qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
498{
499 char un_str[10];
500 struct qla_hw_data *ha = vha->hw;
501
502 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
503 ha->fw_minor_version,
504 ha->fw_subminor_version);
505
506 if (ha->fw_attributes & BIT_9) {
507 strcat(str, "FLX");
508 return (str);
509 }
510
511 switch (ha->fw_attributes & 0xFF) {
512 case 0x7:
513 strcat(str, "EF");
514 break;
515 case 0x17:
516 strcat(str, "TP");
517 break;
518 case 0x37:
519 strcat(str, "IP");
520 break;
521 case 0x77:
522 strcat(str, "VI");
523 break;
524 default:
525 sprintf(un_str, "(%x)", ha->fw_attributes);
526 strcat(str, un_str);
527 break;
528 }
529 if (ha->fw_attributes & 0x100)
530 strcat(str, "X");
531
532 return (str);
533}
534
535static char *
536qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
537{
538 struct qla_hw_data *ha = vha->hw;
539
540 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
541 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
542 return str;
543}
544
545static inline srb_t *
546qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
547 struct scsi_cmnd *cmd)
548{
549 srb_t *sp;
550 struct qla_hw_data *ha = vha->hw;
551
552 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
553 if (!sp) {
554 ql_log(ql_log_warn, vha, 0x3006,
555 "Memory allocation failed for sp.\n");
556 return sp;
557 }
558
559 atomic_set(&sp->ref_count, 1);
560 sp->fcport = fcport;
561 sp->cmd = cmd;
562 sp->flags = 0;
563 CMD_SP(cmd) = (void *)sp;
564 sp->ctx = NULL;
565
566 return sp;
567}
568
569static int
570qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
571{
572 scsi_qla_host_t *vha = shost_priv(host);
573 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
574 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
575 struct qla_hw_data *ha = vha->hw;
576 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
577 srb_t *sp;
578 int rval;
579
580 if (ha->flags.eeh_busy) {
581 if (ha->flags.pci_channel_io_perm_failure) {
582 ql_dbg(ql_dbg_io, vha, 0x3001,
583 "PCI Channel IO permanent failure, exiting "
584 "cmd=%p.\n", cmd);
585 cmd->result = DID_NO_CONNECT << 16;
586 } else {
587 ql_dbg(ql_dbg_io, vha, 0x3002,
588 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
589 cmd->result = DID_REQUEUE << 16;
590 }
591 goto qc24_fail_command;
592 }
593
594 rval = fc_remote_port_chkready(rport);
595 if (rval) {
596 cmd->result = rval;
597 ql_dbg(ql_dbg_io, vha, 0x3003,
598 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
599 cmd, rval);
600 goto qc24_fail_command;
601 }
602
603 if (!vha->flags.difdix_supported &&
604 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
605 ql_dbg(ql_dbg_io, vha, 0x3004,
606 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
607 cmd);
608 cmd->result = DID_NO_CONNECT << 16;
609 goto qc24_fail_command;
610 }
611 if (atomic_read(&fcport->state) != FCS_ONLINE) {
612 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
613 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
614 ql_dbg(ql_dbg_io, vha, 0x3005,
615 "Returning DNC, fcport_state=%d loop_state=%d.\n",
616 atomic_read(&fcport->state),
617 atomic_read(&base_vha->loop_state));
618 cmd->result = DID_NO_CONNECT << 16;
619 goto qc24_fail_command;
620 }
621 goto qc24_target_busy;
622 }
623
624 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
625 if (!sp)
626 goto qc24_host_busy;
627
628 rval = ha->isp_ops->start_scsi(sp);
629 if (rval != QLA_SUCCESS) {
630 ql_dbg(ql_dbg_io, vha, 0x3013,
631 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
632 goto qc24_host_busy_free_sp;
633 }
634
635 return 0;
636
637qc24_host_busy_free_sp:
638 qla2x00_sp_free_dma(sp);
639 mempool_free(sp, ha->srb_mempool);
640
641qc24_host_busy:
642 return SCSI_MLQUEUE_HOST_BUSY;
643
644qc24_target_busy:
645 return SCSI_MLQUEUE_TARGET_BUSY;
646
647qc24_fail_command:
648 cmd->scsi_done(cmd);
649
650 return 0;
651}
652
653
654
655
656
657
658
659
660
661
662
663
664
665static int
666qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
667{
668#define ABORT_POLLING_PERIOD 1000
669#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
670 unsigned long wait_iter = ABORT_WAIT_ITER;
671 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
672 struct qla_hw_data *ha = vha->hw;
673 int ret = QLA_SUCCESS;
674
675 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
676 ql_dbg(ql_dbg_taskm, vha, 0x8005,
677 "Return:eh_wait.\n");
678 return ret;
679 }
680
681 while (CMD_SP(cmd) && wait_iter--) {
682 msleep(ABORT_POLLING_PERIOD);
683 }
684 if (CMD_SP(cmd))
685 ret = QLA_FUNCTION_FAILED;
686
687 return ret;
688}
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707int
708qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
709{
710 int return_status;
711 unsigned long wait_online;
712 struct qla_hw_data *ha = vha->hw;
713 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
714
715 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
716 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
717 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
718 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
719 ha->dpc_active) && time_before(jiffies, wait_online)) {
720
721 msleep(1000);
722 }
723 if (base_vha->flags.online)
724 return_status = QLA_SUCCESS;
725 else
726 return_status = QLA_FUNCTION_FAILED;
727
728 return (return_status);
729}
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749static int
750qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
751{
752 int return_status;
753 unsigned long wait_online;
754 struct qla_hw_data *ha = vha->hw;
755 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
756
757 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
758 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
759 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
760 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
761 ha->optrom_state != QLA_SWAITING ||
762 ha->dpc_active) && time_before(jiffies, wait_online))
763 msleep(1000);
764
765 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
766 return_status = QLA_SUCCESS;
767 else
768 return_status = QLA_FUNCTION_FAILED;
769
770 ql_dbg(ql_dbg_taskm, vha, 0x8019,
771 "%s return status=%d.\n", __func__, return_status);
772
773 return return_status;
774}
775
776int
777qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
778{
779 int return_status;
780 unsigned long wait_reset;
781 struct qla_hw_data *ha = vha->hw;
782 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
783
784 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
785 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
786 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
787 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
788 ha->dpc_active) && time_before(jiffies, wait_reset)) {
789
790 msleep(1000);
791
792 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
793 ha->flags.chip_reset_done)
794 break;
795 }
796 if (ha->flags.chip_reset_done)
797 return_status = QLA_SUCCESS;
798 else
799 return_status = QLA_FUNCTION_FAILED;
800
801 return return_status;
802}
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820static inline int
821qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
822{
823 int return_status = QLA_SUCCESS;
824 unsigned long loop_timeout ;
825 struct qla_hw_data *ha = vha->hw;
826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
827
828
829 loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
830
831 while ((!atomic_read(&base_vha->loop_down_timer) &&
832 atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
833 atomic_read(&base_vha->loop_state) != LOOP_READY) {
834 if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
835 return_status = QLA_FUNCTION_FAILED;
836 break;
837 }
838 msleep(1000);
839 if (time_after_eq(jiffies, loop_timeout)) {
840 return_status = QLA_FUNCTION_FAILED;
841 break;
842 }
843 }
844 return (return_status);
845}
846
847static void
848sp_get(struct srb *sp)
849{
850 atomic_inc(&sp->ref_count);
851}
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868static int
869qla2xxx_eh_abort(struct scsi_cmnd *cmd)
870{
871 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
872 srb_t *sp;
873 int ret;
874 unsigned int id, lun;
875 unsigned long flags;
876 int wait = 0;
877 struct qla_hw_data *ha = vha->hw;
878
879 ql_dbg(ql_dbg_taskm, vha, 0x8000,
880 "Entered %s for cmd=%p.\n", __func__, cmd);
881 if (!CMD_SP(cmd))
882 return SUCCESS;
883
884 ret = fc_block_scsi_eh(cmd);
885 ql_dbg(ql_dbg_taskm, vha, 0x8001,
886 "Return value of fc_block_scsi_eh=%d.\n", ret);
887 if (ret != 0)
888 return ret;
889 ret = SUCCESS;
890
891 id = cmd->device->id;
892 lun = cmd->device->lun;
893
894 spin_lock_irqsave(&ha->hardware_lock, flags);
895 sp = (srb_t *) CMD_SP(cmd);
896 if (!sp) {
897 spin_unlock_irqrestore(&ha->hardware_lock, flags);
898 return SUCCESS;
899 }
900
901 ql_dbg(ql_dbg_taskm, vha, 0x8002,
902 "Aborting sp=%p cmd=%p from RISC ", sp, cmd);
903
904
905 sp_get(sp);
906
907 spin_unlock_irqrestore(&ha->hardware_lock, flags);
908 if (ha->isp_ops->abort_command(sp)) {
909 ql_dbg(ql_dbg_taskm, vha, 0x8003,
910 "Abort command mbx failed for cmd=%p.\n", cmd);
911 } else {
912 ql_dbg(ql_dbg_taskm, vha, 0x8004,
913 "Abort command mbx success.\n");
914 wait = 1;
915 }
916
917 spin_lock_irqsave(&ha->hardware_lock, flags);
918 qla2x00_sp_compl(ha, sp);
919 spin_unlock_irqrestore(&ha->hardware_lock, flags);
920
921
922 if (ret == FAILED && !CMD_SP(cmd))
923 ret = SUCCESS;
924
925
926 if (wait) {
927 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
928 ql_log(ql_log_warn, vha, 0x8006,
929 "Abort handler timed out for cmd=%p.\n", cmd);
930 ret = FAILED;
931 }
932 }
933
934 ql_log(ql_log_info, vha, 0x801c,
935 "Abort command issued -- %d %x.\n", wait, ret);
936
937 return ret;
938}
939
940int
941qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
942 unsigned int l, enum nexus_wait_type type)
943{
944 int cnt, match, status;
945 unsigned long flags;
946 struct qla_hw_data *ha = vha->hw;
947 struct req_que *req;
948 srb_t *sp;
949
950 status = QLA_SUCCESS;
951
952 spin_lock_irqsave(&ha->hardware_lock, flags);
953 req = vha->req;
954 for (cnt = 1; status == QLA_SUCCESS &&
955 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
956 sp = req->outstanding_cmds[cnt];
957 if (!sp)
958 continue;
959 if ((sp->ctx) && !IS_PROT_IO(sp))
960 continue;
961 if (vha->vp_idx != sp->fcport->vha->vp_idx)
962 continue;
963 match = 0;
964 switch (type) {
965 case WAIT_HOST:
966 match = 1;
967 break;
968 case WAIT_TARGET:
969 match = sp->cmd->device->id == t;
970 break;
971 case WAIT_LUN:
972 match = (sp->cmd->device->id == t &&
973 sp->cmd->device->lun == l);
974 break;
975 }
976 if (!match)
977 continue;
978
979 spin_unlock_irqrestore(&ha->hardware_lock, flags);
980 status = qla2x00_eh_wait_on_command(sp->cmd);
981 spin_lock_irqsave(&ha->hardware_lock, flags);
982 }
983 spin_unlock_irqrestore(&ha->hardware_lock, flags);
984
985 return status;
986}
987
988static char *reset_errors[] = {
989 "HBA not online",
990 "HBA not ready",
991 "Task management failed",
992 "Waiting for command completions",
993};
994
995static int
996__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
997 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
998{
999 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1000 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1001 int err;
1002
1003 if (!fcport) {
1004 ql_log(ql_log_warn, vha, 0x8007,
1005 "fcport is NULL.\n");
1006 return FAILED;
1007 }
1008
1009 err = fc_block_scsi_eh(cmd);
1010 ql_dbg(ql_dbg_taskm, vha, 0x8008,
1011 "fc_block_scsi_eh ret=%d.\n", err);
1012 if (err != 0)
1013 return err;
1014
1015 ql_log(ql_log_info, vha, 0x8009,
1016 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name,
1017 cmd->device->id, cmd->device->lun, cmd);
1018
1019 err = 0;
1020 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1021 ql_log(ql_log_warn, vha, 0x800a,
1022 "Wait for hba online failed for cmd=%p.\n", cmd);
1023 goto eh_reset_failed;
1024 }
1025 err = 1;
1026 if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS) {
1027 ql_log(ql_log_warn, vha, 0x800b,
1028 "Wait for loop ready failed for cmd=%p.\n", cmd);
1029 goto eh_reset_failed;
1030 }
1031 err = 2;
1032 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1033 != QLA_SUCCESS) {
1034 ql_log(ql_log_warn, vha, 0x800c,
1035 "do_reset failed for cmd=%p.\n", cmd);
1036 goto eh_reset_failed;
1037 }
1038 err = 3;
1039 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1040 cmd->device->lun, type) != QLA_SUCCESS) {
1041 ql_log(ql_log_warn, vha, 0x800d,
1042 "wait for peding cmds failed for cmd=%p.\n", cmd);
1043 goto eh_reset_failed;
1044 }
1045
1046 ql_log(ql_log_info, vha, 0x800e,
1047 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name,
1048 cmd->device->id, cmd->device->lun, cmd);
1049
1050 return SUCCESS;
1051
1052eh_reset_failed:
1053 ql_log(ql_log_info, vha, 0x800f,
1054 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
1055 reset_errors[err], cmd->device->id, cmd->device->lun);
1056 return FAILED;
1057}
1058
1059static int
1060qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1061{
1062 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1063 struct qla_hw_data *ha = vha->hw;
1064
1065 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1066 ha->isp_ops->lun_reset);
1067}
1068
1069static int
1070qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1071{
1072 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1073 struct qla_hw_data *ha = vha->hw;
1074
1075 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1076 ha->isp_ops->target_reset);
1077}
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094static int
1095qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1096{
1097 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1098 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1099 int ret = FAILED;
1100 unsigned int id, lun;
1101
1102 id = cmd->device->id;
1103 lun = cmd->device->lun;
1104
1105 if (!fcport) {
1106 ql_log(ql_log_warn, vha, 0x8010,
1107 "fcport is NULL.\n");
1108 return ret;
1109 }
1110
1111 ret = fc_block_scsi_eh(cmd);
1112 ql_dbg(ql_dbg_taskm, vha, 0x8011,
1113 "fc_block_scsi_eh ret=%d.\n", ret);
1114 if (ret != 0)
1115 return ret;
1116 ret = FAILED;
1117
1118 ql_log(ql_log_info, vha, 0x8012,
1119 "BUS RESET ISSUED for id %d lun %d.\n", id, lun);
1120
1121 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1122 ql_log(ql_log_fatal, vha, 0x8013,
1123 "Wait for hba online failed board disabled.\n");
1124 goto eh_bus_reset_done;
1125 }
1126
1127 if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
1128 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1129 ret = SUCCESS;
1130 }
1131 if (ret == FAILED)
1132 goto eh_bus_reset_done;
1133
1134
1135 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1136 QLA_SUCCESS) {
1137 ql_log(ql_log_warn, vha, 0x8014,
1138 "Wait for pending commands failed.\n");
1139 ret = FAILED;
1140 }
1141
1142eh_bus_reset_done:
1143 ql_log(ql_log_warn, vha, 0x802b,
1144 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED");
1145
1146 return ret;
1147}
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164static int
1165qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1166{
1167 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1168 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1169 struct qla_hw_data *ha = vha->hw;
1170 int ret = FAILED;
1171 unsigned int id, lun;
1172 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1173
1174 id = cmd->device->id;
1175 lun = cmd->device->lun;
1176
1177 if (!fcport) {
1178 ql_log(ql_log_warn, vha, 0x8016,
1179 "fcport is NULL.\n");
1180 return ret;
1181 }
1182
1183 ret = fc_block_scsi_eh(cmd);
1184 ql_dbg(ql_dbg_taskm, vha, 0x8017,
1185 "fc_block_scsi_eh ret=%d.\n", ret);
1186 if (ret != 0)
1187 return ret;
1188 ret = FAILED;
1189
1190 ql_log(ql_log_info, vha, 0x8018,
1191 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun);
1192
1193 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
1194 goto eh_host_reset_lock;
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204 qla2x00_wait_for_loop_ready(vha);
1205 if (vha != base_vha) {
1206 if (qla2x00_vp_abort_isp(vha))
1207 goto eh_host_reset_lock;
1208 } else {
1209 if (IS_QLA82XX(vha->hw)) {
1210 if (!qla82xx_fcoe_ctx_reset(vha)) {
1211
1212 ret = SUCCESS;
1213 goto eh_host_reset_lock;
1214 }
1215
1216 }
1217 if (ha->wq)
1218 flush_workqueue(ha->wq);
1219
1220 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1221 if (ha->isp_ops->abort_isp(base_vha)) {
1222 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1223
1224 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1225
1226 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1227 ql_log(ql_log_warn, vha, 0x802a,
1228 "wait for hba online failed.\n");
1229 goto eh_host_reset_lock;
1230 }
1231 }
1232 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1233 }
1234
1235
1236 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1237 QLA_SUCCESS)
1238 ret = SUCCESS;
1239
1240eh_host_reset_lock:
1241 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__,
1242 (ret == FAILED) ? "failed" : "succeeded");
1243
1244 return ret;
1245}
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257int
1258qla2x00_loop_reset(scsi_qla_host_t *vha)
1259{
1260 int ret;
1261 struct fc_port *fcport;
1262 struct qla_hw_data *ha = vha->hw;
1263
1264 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1265 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1266 if (fcport->port_type != FCT_TARGET)
1267 continue;
1268
1269 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1270 if (ret != QLA_SUCCESS) {
1271 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1272 "Bus Reset failed: Target Reset=%d "
1273 "d_id=%x.\n", ret, fcport->d_id.b24);
1274 }
1275 }
1276 }
1277
1278 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
1279 ret = qla2x00_full_login_lip(vha);
1280 if (ret != QLA_SUCCESS) {
1281 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1282 "full_login_lip=%d.\n", ret);
1283 }
1284 atomic_set(&vha->loop_state, LOOP_DOWN);
1285 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1286 qla2x00_mark_all_devices_lost(vha, 0);
1287 qla2x00_wait_for_loop_ready(vha);
1288 }
1289
1290 if (ha->flags.enable_lip_reset) {
1291 ret = qla2x00_lip_reset(vha);
1292 if (ret != QLA_SUCCESS) {
1293 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1294 "lip_reset failed (%d).\n", ret);
1295 } else
1296 qla2x00_wait_for_loop_ready(vha);
1297 }
1298
1299
1300 vha->marker_needed = 1;
1301
1302 return QLA_SUCCESS;
1303}
1304
1305void
1306qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1307{
1308 int que, cnt;
1309 unsigned long flags;
1310 srb_t *sp;
1311 struct srb_ctx *ctx;
1312 struct qla_hw_data *ha = vha->hw;
1313 struct req_que *req;
1314
1315 spin_lock_irqsave(&ha->hardware_lock, flags);
1316 for (que = 0; que < ha->max_req_queues; que++) {
1317 req = ha->req_q_map[que];
1318 if (!req)
1319 continue;
1320 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1321 sp = req->outstanding_cmds[cnt];
1322 if (sp) {
1323 req->outstanding_cmds[cnt] = NULL;
1324 if (!sp->ctx ||
1325 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1326 IS_PROT_IO(sp)) {
1327 sp->cmd->result = res;
1328 qla2x00_sp_compl(ha, sp);
1329 } else {
1330 ctx = sp->ctx;
1331 if (ctx->type == SRB_ELS_CMD_RPT ||
1332 ctx->type == SRB_ELS_CMD_HST ||
1333 ctx->type == SRB_CT_CMD) {
1334 struct fc_bsg_job *bsg_job =
1335 ctx->u.bsg_job;
1336 if (bsg_job->request->msgcode
1337 == FC_BSG_HST_CT)
1338 kfree(sp->fcport);
1339 bsg_job->req->errors = 0;
1340 bsg_job->reply->result = res;
1341 bsg_job->job_done(bsg_job);
1342 kfree(sp->ctx);
1343 mempool_free(sp,
1344 ha->srb_mempool);
1345 } else {
1346 ctx->u.iocb_cmd->free(sp);
1347 }
1348 }
1349 }
1350 }
1351 }
1352 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1353}
1354
1355static int
1356qla2xxx_slave_alloc(struct scsi_device *sdev)
1357{
1358 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1359
1360 if (!rport || fc_remote_port_chkready(rport))
1361 return -ENXIO;
1362
1363 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1364
1365 return 0;
1366}
1367
1368static int
1369qla2xxx_slave_configure(struct scsi_device *sdev)
1370{
1371 scsi_qla_host_t *vha = shost_priv(sdev->host);
1372 struct req_que *req = vha->req;
1373
1374 if (sdev->tagged_supported)
1375 scsi_activate_tcq(sdev, req->max_q_depth);
1376 else
1377 scsi_deactivate_tcq(sdev, req->max_q_depth);
1378 return 0;
1379}
1380
1381static void
1382qla2xxx_slave_destroy(struct scsi_device *sdev)
1383{
1384 sdev->hostdata = NULL;
1385}
1386
1387static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1388{
1389 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1390
1391 if (!scsi_track_queue_full(sdev, qdepth))
1392 return;
1393
1394 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1395 "Queue depth adjusted-down "
1396 "to %d for scsi(%ld:%d:%d:%d).\n",
1397 sdev->queue_depth, fcport->vha->host_no,
1398 sdev->channel, sdev->id, sdev->lun);
1399}
1400
1401static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1402{
1403 fc_port_t *fcport = sdev->hostdata;
1404 struct scsi_qla_host *vha = fcport->vha;
1405 struct req_que *req = NULL;
1406
1407 req = vha->req;
1408 if (!req)
1409 return;
1410
1411 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1412 return;
1413
1414 if (sdev->ordered_tags)
1415 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1416 else
1417 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1418
1419 ql_dbg(ql_dbg_io, vha, 0x302a,
1420 "Queue depth adjusted-up to %d for "
1421 "scsi(%ld:%d:%d:%d).\n",
1422 sdev->queue_depth, fcport->vha->host_no,
1423 sdev->channel, sdev->id, sdev->lun);
1424}
1425
1426static int
1427qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1428{
1429 switch (reason) {
1430 case SCSI_QDEPTH_DEFAULT:
1431 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1432 break;
1433 case SCSI_QDEPTH_QFULL:
1434 qla2x00_handle_queue_full(sdev, qdepth);
1435 break;
1436 case SCSI_QDEPTH_RAMP_UP:
1437 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1438 break;
1439 default:
1440 return -EOPNOTSUPP;
1441 }
1442
1443 return sdev->queue_depth;
1444}
1445
1446static int
1447qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1448{
1449 if (sdev->tagged_supported) {
1450 scsi_set_tag_type(sdev, tag_type);
1451 if (tag_type)
1452 scsi_activate_tcq(sdev, sdev->queue_depth);
1453 else
1454 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1455 } else
1456 tag_type = 0;
1457
1458 return tag_type;
1459}
1460
1461
1462
1463
1464
1465
1466
1467
1468static void
1469qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1470{
1471
1472 ha->flags.enable_64bit_addressing = 0;
1473
1474 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1475
1476 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1477 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1478
1479 ha->flags.enable_64bit_addressing = 1;
1480 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1481 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1482 return;
1483 }
1484 }
1485
1486 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1487 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1488}
1489
1490static void
1491qla2x00_enable_intrs(struct qla_hw_data *ha)
1492{
1493 unsigned long flags = 0;
1494 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1495
1496 spin_lock_irqsave(&ha->hardware_lock, flags);
1497 ha->interrupts_on = 1;
1498
1499 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1500 RD_REG_WORD(®->ictrl);
1501 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1502
1503}
1504
1505static void
1506qla2x00_disable_intrs(struct qla_hw_data *ha)
1507{
1508 unsigned long flags = 0;
1509 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1510
1511 spin_lock_irqsave(&ha->hardware_lock, flags);
1512 ha->interrupts_on = 0;
1513
1514 WRT_REG_WORD(®->ictrl, 0);
1515 RD_REG_WORD(®->ictrl);
1516 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1517}
1518
1519static void
1520qla24xx_enable_intrs(struct qla_hw_data *ha)
1521{
1522 unsigned long flags = 0;
1523 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1524
1525 spin_lock_irqsave(&ha->hardware_lock, flags);
1526 ha->interrupts_on = 1;
1527 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT);
1528 RD_REG_DWORD(®->ictrl);
1529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1530}
1531
1532static void
1533qla24xx_disable_intrs(struct qla_hw_data *ha)
1534{
1535 unsigned long flags = 0;
1536 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1537
1538 if (IS_NOPOLLING_TYPE(ha))
1539 return;
1540 spin_lock_irqsave(&ha->hardware_lock, flags);
1541 ha->interrupts_on = 0;
1542 WRT_REG_DWORD(®->ictrl, 0);
1543 RD_REG_DWORD(®->ictrl);
1544 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1545}
1546
1547static struct isp_operations qla2100_isp_ops = {
1548 .pci_config = qla2100_pci_config,
1549 .reset_chip = qla2x00_reset_chip,
1550 .chip_diag = qla2x00_chip_diag,
1551 .config_rings = qla2x00_config_rings,
1552 .reset_adapter = qla2x00_reset_adapter,
1553 .nvram_config = qla2x00_nvram_config,
1554 .update_fw_options = qla2x00_update_fw_options,
1555 .load_risc = qla2x00_load_risc,
1556 .pci_info_str = qla2x00_pci_info_str,
1557 .fw_version_str = qla2x00_fw_version_str,
1558 .intr_handler = qla2100_intr_handler,
1559 .enable_intrs = qla2x00_enable_intrs,
1560 .disable_intrs = qla2x00_disable_intrs,
1561 .abort_command = qla2x00_abort_command,
1562 .target_reset = qla2x00_abort_target,
1563 .lun_reset = qla2x00_lun_reset,
1564 .fabric_login = qla2x00_login_fabric,
1565 .fabric_logout = qla2x00_fabric_logout,
1566 .calc_req_entries = qla2x00_calc_iocbs_32,
1567 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1568 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1569 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1570 .read_nvram = qla2x00_read_nvram_data,
1571 .write_nvram = qla2x00_write_nvram_data,
1572 .fw_dump = qla2100_fw_dump,
1573 .beacon_on = NULL,
1574 .beacon_off = NULL,
1575 .beacon_blink = NULL,
1576 .read_optrom = qla2x00_read_optrom_data,
1577 .write_optrom = qla2x00_write_optrom_data,
1578 .get_flash_version = qla2x00_get_flash_version,
1579 .start_scsi = qla2x00_start_scsi,
1580 .abort_isp = qla2x00_abort_isp,
1581};
1582
1583static struct isp_operations qla2300_isp_ops = {
1584 .pci_config = qla2300_pci_config,
1585 .reset_chip = qla2x00_reset_chip,
1586 .chip_diag = qla2x00_chip_diag,
1587 .config_rings = qla2x00_config_rings,
1588 .reset_adapter = qla2x00_reset_adapter,
1589 .nvram_config = qla2x00_nvram_config,
1590 .update_fw_options = qla2x00_update_fw_options,
1591 .load_risc = qla2x00_load_risc,
1592 .pci_info_str = qla2x00_pci_info_str,
1593 .fw_version_str = qla2x00_fw_version_str,
1594 .intr_handler = qla2300_intr_handler,
1595 .enable_intrs = qla2x00_enable_intrs,
1596 .disable_intrs = qla2x00_disable_intrs,
1597 .abort_command = qla2x00_abort_command,
1598 .target_reset = qla2x00_abort_target,
1599 .lun_reset = qla2x00_lun_reset,
1600 .fabric_login = qla2x00_login_fabric,
1601 .fabric_logout = qla2x00_fabric_logout,
1602 .calc_req_entries = qla2x00_calc_iocbs_32,
1603 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1604 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1605 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1606 .read_nvram = qla2x00_read_nvram_data,
1607 .write_nvram = qla2x00_write_nvram_data,
1608 .fw_dump = qla2300_fw_dump,
1609 .beacon_on = qla2x00_beacon_on,
1610 .beacon_off = qla2x00_beacon_off,
1611 .beacon_blink = qla2x00_beacon_blink,
1612 .read_optrom = qla2x00_read_optrom_data,
1613 .write_optrom = qla2x00_write_optrom_data,
1614 .get_flash_version = qla2x00_get_flash_version,
1615 .start_scsi = qla2x00_start_scsi,
1616 .abort_isp = qla2x00_abort_isp,
1617};
1618
1619static struct isp_operations qla24xx_isp_ops = {
1620 .pci_config = qla24xx_pci_config,
1621 .reset_chip = qla24xx_reset_chip,
1622 .chip_diag = qla24xx_chip_diag,
1623 .config_rings = qla24xx_config_rings,
1624 .reset_adapter = qla24xx_reset_adapter,
1625 .nvram_config = qla24xx_nvram_config,
1626 .update_fw_options = qla24xx_update_fw_options,
1627 .load_risc = qla24xx_load_risc,
1628 .pci_info_str = qla24xx_pci_info_str,
1629 .fw_version_str = qla24xx_fw_version_str,
1630 .intr_handler = qla24xx_intr_handler,
1631 .enable_intrs = qla24xx_enable_intrs,
1632 .disable_intrs = qla24xx_disable_intrs,
1633 .abort_command = qla24xx_abort_command,
1634 .target_reset = qla24xx_abort_target,
1635 .lun_reset = qla24xx_lun_reset,
1636 .fabric_login = qla24xx_login_fabric,
1637 .fabric_logout = qla24xx_fabric_logout,
1638 .calc_req_entries = NULL,
1639 .build_iocbs = NULL,
1640 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1641 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1642 .read_nvram = qla24xx_read_nvram_data,
1643 .write_nvram = qla24xx_write_nvram_data,
1644 .fw_dump = qla24xx_fw_dump,
1645 .beacon_on = qla24xx_beacon_on,
1646 .beacon_off = qla24xx_beacon_off,
1647 .beacon_blink = qla24xx_beacon_blink,
1648 .read_optrom = qla24xx_read_optrom_data,
1649 .write_optrom = qla24xx_write_optrom_data,
1650 .get_flash_version = qla24xx_get_flash_version,
1651 .start_scsi = qla24xx_start_scsi,
1652 .abort_isp = qla2x00_abort_isp,
1653};
1654
1655static struct isp_operations qla25xx_isp_ops = {
1656 .pci_config = qla25xx_pci_config,
1657 .reset_chip = qla24xx_reset_chip,
1658 .chip_diag = qla24xx_chip_diag,
1659 .config_rings = qla24xx_config_rings,
1660 .reset_adapter = qla24xx_reset_adapter,
1661 .nvram_config = qla24xx_nvram_config,
1662 .update_fw_options = qla24xx_update_fw_options,
1663 .load_risc = qla24xx_load_risc,
1664 .pci_info_str = qla24xx_pci_info_str,
1665 .fw_version_str = qla24xx_fw_version_str,
1666 .intr_handler = qla24xx_intr_handler,
1667 .enable_intrs = qla24xx_enable_intrs,
1668 .disable_intrs = qla24xx_disable_intrs,
1669 .abort_command = qla24xx_abort_command,
1670 .target_reset = qla24xx_abort_target,
1671 .lun_reset = qla24xx_lun_reset,
1672 .fabric_login = qla24xx_login_fabric,
1673 .fabric_logout = qla24xx_fabric_logout,
1674 .calc_req_entries = NULL,
1675 .build_iocbs = NULL,
1676 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1677 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1678 .read_nvram = qla25xx_read_nvram_data,
1679 .write_nvram = qla25xx_write_nvram_data,
1680 .fw_dump = qla25xx_fw_dump,
1681 .beacon_on = qla24xx_beacon_on,
1682 .beacon_off = qla24xx_beacon_off,
1683 .beacon_blink = qla24xx_beacon_blink,
1684 .read_optrom = qla25xx_read_optrom_data,
1685 .write_optrom = qla24xx_write_optrom_data,
1686 .get_flash_version = qla24xx_get_flash_version,
1687 .start_scsi = qla24xx_dif_start_scsi,
1688 .abort_isp = qla2x00_abort_isp,
1689};
1690
1691static struct isp_operations qla81xx_isp_ops = {
1692 .pci_config = qla25xx_pci_config,
1693 .reset_chip = qla24xx_reset_chip,
1694 .chip_diag = qla24xx_chip_diag,
1695 .config_rings = qla24xx_config_rings,
1696 .reset_adapter = qla24xx_reset_adapter,
1697 .nvram_config = qla81xx_nvram_config,
1698 .update_fw_options = qla81xx_update_fw_options,
1699 .load_risc = qla81xx_load_risc,
1700 .pci_info_str = qla24xx_pci_info_str,
1701 .fw_version_str = qla24xx_fw_version_str,
1702 .intr_handler = qla24xx_intr_handler,
1703 .enable_intrs = qla24xx_enable_intrs,
1704 .disable_intrs = qla24xx_disable_intrs,
1705 .abort_command = qla24xx_abort_command,
1706 .target_reset = qla24xx_abort_target,
1707 .lun_reset = qla24xx_lun_reset,
1708 .fabric_login = qla24xx_login_fabric,
1709 .fabric_logout = qla24xx_fabric_logout,
1710 .calc_req_entries = NULL,
1711 .build_iocbs = NULL,
1712 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1713 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1714 .read_nvram = NULL,
1715 .write_nvram = NULL,
1716 .fw_dump = qla81xx_fw_dump,
1717 .beacon_on = qla24xx_beacon_on,
1718 .beacon_off = qla24xx_beacon_off,
1719 .beacon_blink = qla24xx_beacon_blink,
1720 .read_optrom = qla25xx_read_optrom_data,
1721 .write_optrom = qla24xx_write_optrom_data,
1722 .get_flash_version = qla24xx_get_flash_version,
1723 .start_scsi = qla24xx_dif_start_scsi,
1724 .abort_isp = qla2x00_abort_isp,
1725};
1726
1727static struct isp_operations qla82xx_isp_ops = {
1728 .pci_config = qla82xx_pci_config,
1729 .reset_chip = qla82xx_reset_chip,
1730 .chip_diag = qla24xx_chip_diag,
1731 .config_rings = qla82xx_config_rings,
1732 .reset_adapter = qla24xx_reset_adapter,
1733 .nvram_config = qla81xx_nvram_config,
1734 .update_fw_options = qla24xx_update_fw_options,
1735 .load_risc = qla82xx_load_risc,
1736 .pci_info_str = qla82xx_pci_info_str,
1737 .fw_version_str = qla24xx_fw_version_str,
1738 .intr_handler = qla82xx_intr_handler,
1739 .enable_intrs = qla82xx_enable_intrs,
1740 .disable_intrs = qla82xx_disable_intrs,
1741 .abort_command = qla24xx_abort_command,
1742 .target_reset = qla24xx_abort_target,
1743 .lun_reset = qla24xx_lun_reset,
1744 .fabric_login = qla24xx_login_fabric,
1745 .fabric_logout = qla24xx_fabric_logout,
1746 .calc_req_entries = NULL,
1747 .build_iocbs = NULL,
1748 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1749 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1750 .read_nvram = qla24xx_read_nvram_data,
1751 .write_nvram = qla24xx_write_nvram_data,
1752 .fw_dump = qla24xx_fw_dump,
1753 .beacon_on = qla24xx_beacon_on,
1754 .beacon_off = qla24xx_beacon_off,
1755 .beacon_blink = qla24xx_beacon_blink,
1756 .read_optrom = qla82xx_read_optrom_data,
1757 .write_optrom = qla82xx_write_optrom_data,
1758 .get_flash_version = qla24xx_get_flash_version,
1759 .start_scsi = qla82xx_start_scsi,
1760 .abort_isp = qla82xx_abort_isp,
1761};
1762
1763static inline void
1764qla2x00_set_isp_flags(struct qla_hw_data *ha)
1765{
1766 ha->device_type = DT_EXTENDED_IDS;
1767 switch (ha->pdev->device) {
1768 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1769 ha->device_type |= DT_ISP2100;
1770 ha->device_type &= ~DT_EXTENDED_IDS;
1771 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
1772 break;
1773 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1774 ha->device_type |= DT_ISP2200;
1775 ha->device_type &= ~DT_EXTENDED_IDS;
1776 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
1777 break;
1778 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1779 ha->device_type |= DT_ISP2300;
1780 ha->device_type |= DT_ZIO_SUPPORTED;
1781 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1782 break;
1783 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1784 ha->device_type |= DT_ISP2312;
1785 ha->device_type |= DT_ZIO_SUPPORTED;
1786 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1787 break;
1788 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1789 ha->device_type |= DT_ISP2322;
1790 ha->device_type |= DT_ZIO_SUPPORTED;
1791 if (ha->pdev->subsystem_vendor == 0x1028 &&
1792 ha->pdev->subsystem_device == 0x0170)
1793 ha->device_type |= DT_OEM_001;
1794 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1795 break;
1796 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1797 ha->device_type |= DT_ISP6312;
1798 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1799 break;
1800 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1801 ha->device_type |= DT_ISP6322;
1802 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1803 break;
1804 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1805 ha->device_type |= DT_ISP2422;
1806 ha->device_type |= DT_ZIO_SUPPORTED;
1807 ha->device_type |= DT_FWI2;
1808 ha->device_type |= DT_IIDMA;
1809 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1810 break;
1811 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1812 ha->device_type |= DT_ISP2432;
1813 ha->device_type |= DT_ZIO_SUPPORTED;
1814 ha->device_type |= DT_FWI2;
1815 ha->device_type |= DT_IIDMA;
1816 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1817 break;
1818 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1819 ha->device_type |= DT_ISP8432;
1820 ha->device_type |= DT_ZIO_SUPPORTED;
1821 ha->device_type |= DT_FWI2;
1822 ha->device_type |= DT_IIDMA;
1823 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1824 break;
1825 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1826 ha->device_type |= DT_ISP5422;
1827 ha->device_type |= DT_FWI2;
1828 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1829 break;
1830 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1831 ha->device_type |= DT_ISP5432;
1832 ha->device_type |= DT_FWI2;
1833 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1834 break;
1835 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1836 ha->device_type |= DT_ISP2532;
1837 ha->device_type |= DT_ZIO_SUPPORTED;
1838 ha->device_type |= DT_FWI2;
1839 ha->device_type |= DT_IIDMA;
1840 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1841 break;
1842 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1843 ha->device_type |= DT_ISP8001;
1844 ha->device_type |= DT_ZIO_SUPPORTED;
1845 ha->device_type |= DT_FWI2;
1846 ha->device_type |= DT_IIDMA;
1847 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1848 break;
1849 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1850 ha->device_type |= DT_ISP8021;
1851 ha->device_type |= DT_ZIO_SUPPORTED;
1852 ha->device_type |= DT_FWI2;
1853 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1854
1855 qla82xx_init_flags(ha);
1856 break;
1857 }
1858
1859 if (IS_QLA82XX(ha))
1860 ha->port_no = !(ha->portnum & 1);
1861 else
1862
1863 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1864
1865 if (ha->port_no & 1)
1866 ha->flags.port0 = 1;
1867 else
1868 ha->flags.port0 = 0;
1869 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
1870 "device_type=0x%x port=%d fw_srisc_address=%p.\n",
1871 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
1872}
1873
1874static int
1875qla2x00_iospace_config(struct qla_hw_data *ha)
1876{
1877 resource_size_t pio;
1878 uint16_t msix;
1879 int cpus;
1880
1881 if (IS_QLA82XX(ha))
1882 return qla82xx_iospace_config(ha);
1883
1884 if (pci_request_selected_regions(ha->pdev, ha->bars,
1885 QLA2XXX_DRIVER_NAME)) {
1886 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1887 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1888 pci_name(ha->pdev));
1889 goto iospace_error_exit;
1890 }
1891 if (!(ha->bars & 1))
1892 goto skip_pio;
1893
1894
1895 pio = pci_resource_start(ha->pdev, 0);
1896 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1897 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1898 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1899 "Invalid pci I/O region size (%s).\n",
1900 pci_name(ha->pdev));
1901 pio = 0;
1902 }
1903 } else {
1904 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1905 "Region #0 no a PIO resource (%s).\n",
1906 pci_name(ha->pdev));
1907 pio = 0;
1908 }
1909 ha->pio_address = pio;
1910 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1911 "PIO address=%p.\n",
1912 ha->pio_address);
1913
1914skip_pio:
1915
1916 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1917 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1918 "Region #1 not an MMIO resource (%s), aborting.\n",
1919 pci_name(ha->pdev));
1920 goto iospace_error_exit;
1921 }
1922 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1923 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1924 "Invalid PCI mem region size (%s), aborting.\n",
1925 pci_name(ha->pdev));
1926 goto iospace_error_exit;
1927 }
1928
1929 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1930 if (!ha->iobase) {
1931 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1932 "Cannot remap MMIO (%s), aborting.\n",
1933 pci_name(ha->pdev));
1934 goto iospace_error_exit;
1935 }
1936
1937
1938 ha->max_req_queues = ha->max_rsp_queues = 1;
1939 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1940 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1941 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1942 goto mqiobase_exit;
1943
1944 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1945 pci_resource_len(ha->pdev, 3));
1946 if (ha->mqiobase) {
1947 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1948 "MQIO Base=%p.\n", ha->mqiobase);
1949
1950 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1951 ha->msix_count = msix;
1952
1953
1954 if (ql2xmultique_tag) {
1955 cpus = num_online_cpus();
1956 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1957 (cpus + 1) : (ha->msix_count - 1);
1958 ha->max_req_queues = 2;
1959 } else if (ql2xmaxqueues > 1) {
1960 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1961 QLA_MQ_SIZE : ql2xmaxqueues;
1962 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1963 "QoS mode set, max no of request queues:%d.\n",
1964 ha->max_req_queues);
1965 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1966 "QoS mode set, max no of request queues:%d.\n",
1967 ha->max_req_queues);
1968 }
1969 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1970 "MSI-X vector count: %d.\n", msix);
1971 } else
1972 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1973 "BAR 3 not enabled.\n");
1974
1975mqiobase_exit:
1976 ha->msix_count = ha->max_rsp_queues + 1;
1977 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1978 "MSIX Count:%d.\n", ha->msix_count);
1979 return (0);
1980
1981iospace_error_exit:
1982 return (-ENOMEM);
1983}
1984
1985static void
1986qla2xxx_scan_start(struct Scsi_Host *shost)
1987{
1988 scsi_qla_host_t *vha = shost_priv(shost);
1989
1990 if (vha->hw->flags.running_gold_fw)
1991 return;
1992
1993 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1994 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1995 set_bit(RSCN_UPDATE, &vha->dpc_flags);
1996 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1997}
1998
1999static int
2000qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2001{
2002 scsi_qla_host_t *vha = shost_priv(shost);
2003
2004 if (!vha->host)
2005 return 1;
2006 if (time > vha->hw->loop_reset_delay * HZ)
2007 return 1;
2008
2009 return atomic_read(&vha->loop_state) == LOOP_READY;
2010}
2011
2012
2013
2014
2015static int __devinit
2016qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2017{
2018 int ret = -ENODEV;
2019 struct Scsi_Host *host;
2020 scsi_qla_host_t *base_vha = NULL;
2021 struct qla_hw_data *ha;
2022 char pci_info[30];
2023 char fw_str[30];
2024 struct scsi_host_template *sht;
2025 int bars, max_id, mem_only = 0;
2026 uint16_t req_length = 0, rsp_length = 0;
2027 struct req_que *req = NULL;
2028 struct rsp_que *rsp = NULL;
2029
2030 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2031 sht = &qla2xxx_driver_template;
2032 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2033 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2034 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2035 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2036 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2037 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2038 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2039 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
2040 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2041 mem_only = 1;
2042 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2043 "Mem only adapter.\n");
2044 }
2045 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2046 "Bars=%d.\n", bars);
2047
2048 if (mem_only) {
2049 if (pci_enable_device_mem(pdev))
2050 goto probe_out;
2051 } else {
2052 if (pci_enable_device(pdev))
2053 goto probe_out;
2054 }
2055
2056
2057 pci_enable_pcie_error_reporting(pdev);
2058
2059 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2060 if (!ha) {
2061 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2062 "Unable to allocate memory for ha.\n");
2063 goto probe_out;
2064 }
2065 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2066 "Memory allocated for ha=%p.\n", ha);
2067 ha->pdev = pdev;
2068
2069
2070 ha->bars = bars;
2071 ha->mem_only = mem_only;
2072 spin_lock_init(&ha->hardware_lock);
2073 spin_lock_init(&ha->vport_slock);
2074
2075
2076 qla2x00_set_isp_flags(ha);
2077
2078
2079 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2080 pdev->needs_freset = 1;
2081 }
2082
2083
2084 ret = qla2x00_iospace_config(ha);
2085 if (ret)
2086 goto probe_hw_failed;
2087
2088 ql_log_pci(ql_log_info, pdev, 0x001d,
2089 "Found an ISP%04X irq %d iobase 0x%p.\n",
2090 pdev->device, pdev->irq, ha->iobase);
2091 ha->prev_topology = 0;
2092 ha->init_cb_size = sizeof(init_cb_t);
2093 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2094 ha->optrom_size = OPTROM_SIZE_2300;
2095
2096
2097 max_id = MAX_TARGETS_2200;
2098 if (IS_QLA2100(ha)) {
2099 max_id = MAX_TARGETS_2100;
2100 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2101 req_length = REQUEST_ENTRY_CNT_2100;
2102 rsp_length = RESPONSE_ENTRY_CNT_2100;
2103 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2104 ha->gid_list_info_size = 4;
2105 ha->flash_conf_off = ~0;
2106 ha->flash_data_off = ~0;
2107 ha->nvram_conf_off = ~0;
2108 ha->nvram_data_off = ~0;
2109 ha->isp_ops = &qla2100_isp_ops;
2110 } else if (IS_QLA2200(ha)) {
2111 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2112 req_length = REQUEST_ENTRY_CNT_2200;
2113 rsp_length = RESPONSE_ENTRY_CNT_2100;
2114 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2115 ha->gid_list_info_size = 4;
2116 ha->flash_conf_off = ~0;
2117 ha->flash_data_off = ~0;
2118 ha->nvram_conf_off = ~0;
2119 ha->nvram_data_off = ~0;
2120 ha->isp_ops = &qla2100_isp_ops;
2121 } else if (IS_QLA23XX(ha)) {
2122 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2123 req_length = REQUEST_ENTRY_CNT_2200;
2124 rsp_length = RESPONSE_ENTRY_CNT_2300;
2125 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2126 ha->gid_list_info_size = 6;
2127 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2128 ha->optrom_size = OPTROM_SIZE_2322;
2129 ha->flash_conf_off = ~0;
2130 ha->flash_data_off = ~0;
2131 ha->nvram_conf_off = ~0;
2132 ha->nvram_data_off = ~0;
2133 ha->isp_ops = &qla2300_isp_ops;
2134 } else if (IS_QLA24XX_TYPE(ha)) {
2135 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2136 req_length = REQUEST_ENTRY_CNT_24XX;
2137 rsp_length = RESPONSE_ENTRY_CNT_2300;
2138 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2139 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2140 ha->gid_list_info_size = 8;
2141 ha->optrom_size = OPTROM_SIZE_24XX;
2142 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2143 ha->isp_ops = &qla24xx_isp_ops;
2144 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2145 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2146 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2147 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2148 } else if (IS_QLA25XX(ha)) {
2149 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2150 req_length = REQUEST_ENTRY_CNT_24XX;
2151 rsp_length = RESPONSE_ENTRY_CNT_2300;
2152 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2153 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2154 ha->gid_list_info_size = 8;
2155 ha->optrom_size = OPTROM_SIZE_25XX;
2156 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2157 ha->isp_ops = &qla25xx_isp_ops;
2158 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2159 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2160 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2161 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2162 } else if (IS_QLA81XX(ha)) {
2163 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2164 req_length = REQUEST_ENTRY_CNT_24XX;
2165 rsp_length = RESPONSE_ENTRY_CNT_2300;
2166 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2167 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2168 ha->gid_list_info_size = 8;
2169 ha->optrom_size = OPTROM_SIZE_81XX;
2170 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2171 ha->isp_ops = &qla81xx_isp_ops;
2172 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2173 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2174 ha->nvram_conf_off = ~0;
2175 ha->nvram_data_off = ~0;
2176 } else if (IS_QLA82XX(ha)) {
2177 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2178 req_length = REQUEST_ENTRY_CNT_82XX;
2179 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2180 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2181 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2182 ha->gid_list_info_size = 8;
2183 ha->optrom_size = OPTROM_SIZE_82XX;
2184 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2185 ha->isp_ops = &qla82xx_isp_ops;
2186 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2187 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2188 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2189 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2190 }
2191 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2192 "mbx_count=%d, req_length=%d, "
2193 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2194 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2195 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2196 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2197 ha->nvram_npiv_size);
2198 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2199 "isp_ops=%p, flash_conf_off=%d, "
2200 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2201 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2202 ha->nvram_conf_off, ha->nvram_data_off);
2203 mutex_init(&ha->vport_lock);
2204 init_completion(&ha->mbx_cmd_comp);
2205 complete(&ha->mbx_cmd_comp);
2206 init_completion(&ha->mbx_intr_comp);
2207 init_completion(&ha->dcbx_comp);
2208
2209 set_bit(0, (unsigned long *) ha->vp_idx_map);
2210
2211 qla2x00_config_dma_addressing(ha);
2212 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2213 "64 Bit addressing is %s.\n",
2214 ha->flags.enable_64bit_addressing ? "enable" :
2215 "disable");
2216 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2217 if (!ret) {
2218 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2219 "Failed to allocate memory for adapter, aborting.\n");
2220
2221 goto probe_hw_failed;
2222 }
2223
2224 req->max_q_depth = MAX_Q_DEPTH;
2225 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2226 req->max_q_depth = ql2xmaxqdepth;
2227
2228
2229 base_vha = qla2x00_create_host(sht, ha);
2230 if (!base_vha) {
2231 ret = -ENOMEM;
2232 qla2x00_mem_free(ha);
2233 qla2x00_free_req_que(ha, req);
2234 qla2x00_free_rsp_que(ha, rsp);
2235 goto probe_hw_failed;
2236 }
2237
2238 pci_set_drvdata(pdev, base_vha);
2239
2240 host = base_vha->host;
2241 base_vha->req = req;
2242 host->can_queue = req->length + 128;
2243 if (IS_QLA2XXX_MIDTYPE(ha))
2244 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2245 else
2246 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2247 base_vha->vp_idx;
2248
2249
2250 if (!IS_FWI2_CAPABLE(ha)) {
2251 if (IS_QLA2100(ha))
2252 host->sg_tablesize = 32;
2253 } else {
2254 if (!IS_QLA82XX(ha))
2255 host->sg_tablesize = QLA_SG_ALL;
2256 }
2257 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2258 "can_queue=%d, req=%p, "
2259 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2260 host->can_queue, base_vha->req,
2261 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2262 host->max_id = max_id;
2263 host->this_id = 255;
2264 host->cmd_per_lun = 3;
2265 host->unique_id = host->host_no;
2266 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2267 host->max_cmd_len = 32;
2268 else
2269 host->max_cmd_len = MAX_CMDSZ;
2270 host->max_channel = MAX_BUSES - 1;
2271 host->max_lun = ql2xmaxlun;
2272 host->transportt = qla2xxx_transport_template;
2273 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2274
2275 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2276 "max_id=%d this_id=%d "
2277 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2278 "max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id,
2279 host->this_id, host->cmd_per_lun, host->unique_id,
2280 host->max_cmd_len, host->max_channel, host->max_lun,
2281 host->transportt, sht->vendor_id);
2282
2283
2284 ret = qla2x00_request_irqs(ha, rsp);
2285 if (ret)
2286 goto probe_init_failed;
2287
2288 pci_save_state(pdev);
2289
2290
2291que_init:
2292 if (!qla2x00_alloc_queues(ha)) {
2293 ql_log(ql_log_fatal, base_vha, 0x003d,
2294 "Failed to allocate memory for queue pointers.. aborting.\n");
2295 goto probe_init_failed;
2296 }
2297
2298 ha->rsp_q_map[0] = rsp;
2299 ha->req_q_map[0] = req;
2300 rsp->req = req;
2301 req->rsp = rsp;
2302 set_bit(0, ha->req_qid_map);
2303 set_bit(0, ha->rsp_qid_map);
2304
2305 req->req_q_in = &ha->iobase->isp24.req_q_in;
2306 req->req_q_out = &ha->iobase->isp24.req_q_out;
2307 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2308 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2309 if (ha->mqenable) {
2310 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2311 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2312 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2313 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2314 }
2315
2316 if (IS_QLA82XX(ha)) {
2317 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2318 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2319 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2320 }
2321
2322 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2323 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2324 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2325 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2326 "req->req_q_in=%p req->req_q_out=%p "
2327 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2328 req->req_q_in, req->req_q_out,
2329 rsp->rsp_q_in, rsp->rsp_q_out);
2330 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2331 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2332 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2333 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2334 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2335 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2336
2337 if (qla2x00_initialize_adapter(base_vha)) {
2338 ql_log(ql_log_fatal, base_vha, 0x00d6,
2339 "Failed to initialize adapter - Adapter flags %x.\n",
2340 base_vha->device_flags);
2341
2342 if (IS_QLA82XX(ha)) {
2343 qla82xx_idc_lock(ha);
2344 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2345 QLA82XX_DEV_FAILED);
2346 qla82xx_idc_unlock(ha);
2347 ql_log(ql_log_fatal, base_vha, 0x00d7,
2348 "HW State: FAILED.\n");
2349 }
2350
2351 ret = -ENODEV;
2352 goto probe_failed;
2353 }
2354
2355 if (ha->mqenable) {
2356 if (qla25xx_setup_mode(base_vha)) {
2357 ql_log(ql_log_warn, base_vha, 0x00ec,
2358 "Failed to create queues, falling back to single queue mode.\n");
2359 goto que_init;
2360 }
2361 }
2362
2363 if (ha->flags.running_gold_fw)
2364 goto skip_dpc;
2365
2366
2367
2368
2369 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2370 "%s_dpc", base_vha->host_str);
2371 if (IS_ERR(ha->dpc_thread)) {
2372 ql_log(ql_log_fatal, base_vha, 0x00ed,
2373 "Failed to start DPC thread.\n");
2374 ret = PTR_ERR(ha->dpc_thread);
2375 goto probe_failed;
2376 }
2377 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2378 "DPC thread started successfully.\n");
2379
2380skip_dpc:
2381 list_add_tail(&base_vha->list, &ha->vp_list);
2382 base_vha->host->irq = ha->pdev->irq;
2383
2384
2385 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2386 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2387 "Started qla2x00_timer with "
2388 "interval=%d.\n", WATCH_INTERVAL);
2389 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2390 "Detected hba at address=%p.\n",
2391 ha);
2392
2393 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2394 if (ha->fw_attributes & BIT_4) {
2395 int prot = 0;
2396 base_vha->flags.difdix_supported = 1;
2397 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2398 "Registering for DIF/DIX type 1 and 3 protection.\n");
2399 if (ql2xenabledif == 1)
2400 prot = SHOST_DIX_TYPE0_PROTECTION;
2401 scsi_host_set_prot(host,
2402 prot | SHOST_DIF_TYPE1_PROTECTION
2403 | SHOST_DIF_TYPE2_PROTECTION
2404 | SHOST_DIF_TYPE3_PROTECTION
2405 | SHOST_DIX_TYPE1_PROTECTION
2406 | SHOST_DIX_TYPE2_PROTECTION
2407 | SHOST_DIX_TYPE3_PROTECTION);
2408 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2409 } else
2410 base_vha->flags.difdix_supported = 0;
2411 }
2412
2413 ha->isp_ops->enable_intrs(ha);
2414
2415 ret = scsi_add_host(host, &pdev->dev);
2416 if (ret)
2417 goto probe_failed;
2418
2419 base_vha->flags.init_done = 1;
2420 base_vha->flags.online = 1;
2421
2422 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2423 "Init done and hba is online.\n");
2424
2425 scsi_scan_host(host);
2426
2427 qla2x00_alloc_sysfs_attr(base_vha);
2428
2429 qla2x00_init_host_attr(base_vha);
2430
2431 qla2x00_dfs_setup(base_vha);
2432
2433 ql_log(ql_log_info, base_vha, 0x00fa,
2434 "QLogic Fibre Channed HBA Driver: %s.\n",
2435 qla2x00_version_str);
2436 ql_log(ql_log_info, base_vha, 0x00fb,
2437 "QLogic %s - %s.\n",
2438 ha->model_number, ha->model_desc ? ha->model_desc : "");
2439 ql_log(ql_log_info, base_vha, 0x00fc,
2440 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2441 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2442 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2443 base_vha->host_no,
2444 ha->isp_ops->fw_version_str(base_vha, fw_str));
2445
2446 return 0;
2447
2448probe_init_failed:
2449 qla2x00_free_req_que(ha, req);
2450 qla2x00_free_rsp_que(ha, rsp);
2451 ha->max_req_queues = ha->max_rsp_queues = 0;
2452
2453probe_failed:
2454 if (base_vha->timer_active)
2455 qla2x00_stop_timer(base_vha);
2456 base_vha->flags.online = 0;
2457 if (ha->dpc_thread) {
2458 struct task_struct *t = ha->dpc_thread;
2459
2460 ha->dpc_thread = NULL;
2461 kthread_stop(t);
2462 }
2463
2464 qla2x00_free_device(base_vha);
2465
2466 scsi_host_put(base_vha->host);
2467
2468probe_hw_failed:
2469 if (IS_QLA82XX(ha)) {
2470 qla82xx_idc_lock(ha);
2471 qla82xx_clear_drv_active(ha);
2472 qla82xx_idc_unlock(ha);
2473 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2474 if (!ql2xdbwr)
2475 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2476 } else {
2477 if (ha->iobase)
2478 iounmap(ha->iobase);
2479 }
2480 pci_release_selected_regions(ha->pdev, ha->bars);
2481 kfree(ha);
2482 ha = NULL;
2483
2484probe_out:
2485 pci_disable_device(pdev);
2486 return ret;
2487}
2488
2489static void
2490qla2x00_shutdown(struct pci_dev *pdev)
2491{
2492 scsi_qla_host_t *vha;
2493 struct qla_hw_data *ha;
2494
2495 vha = pci_get_drvdata(pdev);
2496 ha = vha->hw;
2497
2498
2499 if (ha->flags.fce_enabled) {
2500 qla2x00_disable_fce_trace(vha, NULL, NULL);
2501 ha->flags.fce_enabled = 0;
2502 }
2503
2504
2505 if (ha->eft)
2506 qla2x00_disable_eft_trace(vha);
2507
2508
2509 qla2x00_try_to_stop_firmware(vha);
2510
2511
2512 vha->flags.online = 0;
2513
2514
2515 if (ha->interrupts_on) {
2516 vha->flags.init_done = 0;
2517 ha->isp_ops->disable_intrs(ha);
2518 }
2519
2520 qla2x00_free_irqs(vha);
2521
2522 qla2x00_free_fw_dump(ha);
2523}
2524
2525static void
2526qla2x00_remove_one(struct pci_dev *pdev)
2527{
2528 scsi_qla_host_t *base_vha, *vha;
2529 struct qla_hw_data *ha;
2530 unsigned long flags;
2531
2532 base_vha = pci_get_drvdata(pdev);
2533 ha = base_vha->hw;
2534
2535 mutex_lock(&ha->vport_lock);
2536 while (ha->cur_vport_count) {
2537 struct Scsi_Host *scsi_host;
2538
2539 spin_lock_irqsave(&ha->vport_slock, flags);
2540
2541 BUG_ON(base_vha->list.next == &ha->vp_list);
2542
2543 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2544 scsi_host = scsi_host_get(vha->host);
2545
2546 spin_unlock_irqrestore(&ha->vport_slock, flags);
2547 mutex_unlock(&ha->vport_lock);
2548
2549 fc_vport_terminate(vha->fc_vport);
2550 scsi_host_put(vha->host);
2551
2552 mutex_lock(&ha->vport_lock);
2553 }
2554 mutex_unlock(&ha->vport_lock);
2555
2556 set_bit(UNLOADING, &base_vha->dpc_flags);
2557
2558 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2559
2560 qla2x00_dfs_remove(base_vha);
2561
2562 qla84xx_put_chip(base_vha);
2563
2564
2565 if (base_vha->timer_active)
2566 qla2x00_stop_timer(base_vha);
2567
2568 base_vha->flags.online = 0;
2569
2570
2571 if (ha->wq) {
2572 flush_workqueue(ha->wq);
2573 destroy_workqueue(ha->wq);
2574 ha->wq = NULL;
2575 }
2576
2577
2578 if (ha->dpc_thread) {
2579 struct task_struct *t = ha->dpc_thread;
2580
2581
2582
2583
2584
2585 ha->dpc_thread = NULL;
2586 kthread_stop(t);
2587 }
2588
2589 qla2x00_free_sysfs_attr(base_vha);
2590
2591 fc_remove_host(base_vha->host);
2592
2593 scsi_remove_host(base_vha->host);
2594
2595 qla2x00_free_device(base_vha);
2596
2597 scsi_host_put(base_vha->host);
2598
2599 if (IS_QLA82XX(ha)) {
2600 qla82xx_idc_lock(ha);
2601 qla82xx_clear_drv_active(ha);
2602 qla82xx_idc_unlock(ha);
2603
2604 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2605 if (!ql2xdbwr)
2606 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2607 } else {
2608 if (ha->iobase)
2609 iounmap(ha->iobase);
2610
2611 if (ha->mqiobase)
2612 iounmap(ha->mqiobase);
2613 }
2614
2615 pci_release_selected_regions(ha->pdev, ha->bars);
2616 kfree(ha);
2617 ha = NULL;
2618
2619 pci_disable_pcie_error_reporting(pdev);
2620
2621 pci_disable_device(pdev);
2622 pci_set_drvdata(pdev, NULL);
2623}
2624
2625static void
2626qla2x00_free_device(scsi_qla_host_t *vha)
2627{
2628 struct qla_hw_data *ha = vha->hw;
2629
2630 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2631
2632
2633 if (vha->timer_active)
2634 qla2x00_stop_timer(vha);
2635
2636
2637 if (ha->dpc_thread) {
2638 struct task_struct *t = ha->dpc_thread;
2639
2640
2641
2642
2643
2644 ha->dpc_thread = NULL;
2645 kthread_stop(t);
2646 }
2647
2648 qla25xx_delete_queues(vha);
2649
2650 if (ha->flags.fce_enabled)
2651 qla2x00_disable_fce_trace(vha, NULL, NULL);
2652
2653 if (ha->eft)
2654 qla2x00_disable_eft_trace(vha);
2655
2656
2657 qla2x00_try_to_stop_firmware(vha);
2658
2659 vha->flags.online = 0;
2660
2661
2662 if (ha->interrupts_on) {
2663 vha->flags.init_done = 0;
2664 ha->isp_ops->disable_intrs(ha);
2665 }
2666
2667 qla2x00_free_irqs(vha);
2668
2669 qla2x00_free_fcports(vha);
2670
2671 qla2x00_mem_free(ha);
2672
2673 qla2x00_free_queues(ha);
2674}
2675
2676void qla2x00_free_fcports(struct scsi_qla_host *vha)
2677{
2678 fc_port_t *fcport, *tfcport;
2679
2680 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2681 list_del(&fcport->list);
2682 kfree(fcport);
2683 fcport = NULL;
2684 }
2685}
2686
2687static inline void
2688qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
2689 int defer)
2690{
2691 struct fc_rport *rport;
2692 scsi_qla_host_t *base_vha;
2693 unsigned long flags;
2694
2695 if (!fcport->rport)
2696 return;
2697
2698 rport = fcport->rport;
2699 if (defer) {
2700 base_vha = pci_get_drvdata(vha->hw->pdev);
2701 spin_lock_irqsave(vha->host->host_lock, flags);
2702 fcport->drport = rport;
2703 spin_unlock_irqrestore(vha->host->host_lock, flags);
2704 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2705 qla2xxx_wake_dpc(base_vha);
2706 } else
2707 fc_remote_port_delete(rport);
2708}
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
2720 int do_login, int defer)
2721{
2722 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2723 vha->vp_idx == fcport->vp_idx) {
2724 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2725 qla2x00_schedule_rport_del(vha, fcport, defer);
2726 }
2727
2728
2729
2730
2731 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
2732 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2733
2734 if (!do_login)
2735 return;
2736
2737 if (fcport->login_retry == 0) {
2738 fcport->login_retry = vha->hw->login_retry_count;
2739 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2740
2741 ql_dbg(ql_dbg_disc, vha, 0x2067,
2742 "Port login retry "
2743 "%02x%02x%02x%02x%02x%02x%02x%02x, "
2744 "id = 0x%04x retry cnt=%d.\n",
2745 fcport->port_name[0], fcport->port_name[1],
2746 fcport->port_name[2], fcport->port_name[3],
2747 fcport->port_name[4], fcport->port_name[5],
2748 fcport->port_name[6], fcport->port_name[7],
2749 fcport->loop_id, fcport->login_retry);
2750 }
2751}
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766void
2767qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
2768{
2769 fc_port_t *fcport;
2770
2771 list_for_each_entry(fcport, &vha->vp_fcports, list) {
2772 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
2773 continue;
2774
2775
2776
2777
2778
2779 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2780 continue;
2781 if (atomic_read(&fcport->state) == FCS_ONLINE) {
2782 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2783 if (defer)
2784 qla2x00_schedule_rport_del(vha, fcport, defer);
2785 else if (vha->vp_idx == fcport->vp_idx)
2786 qla2x00_schedule_rport_del(vha, fcport, defer);
2787 }
2788 }
2789}
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799static int
2800qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2801 struct req_que **req, struct rsp_que **rsp)
2802{
2803 char name[16];
2804
2805 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
2806 &ha->init_cb_dma, GFP_KERNEL);
2807 if (!ha->init_cb)
2808 goto fail;
2809
2810 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2811 &ha->gid_list_dma, GFP_KERNEL);
2812 if (!ha->gid_list)
2813 goto fail_free_init_cb;
2814
2815 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2816 if (!ha->srb_mempool)
2817 goto fail_free_gid_list;
2818
2819 if (IS_QLA82XX(ha)) {
2820
2821 if (!ctx_cachep) {
2822 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2823 sizeof(struct ct6_dsd), 0,
2824 SLAB_HWCACHE_ALIGN, NULL);
2825 if (!ctx_cachep)
2826 goto fail_free_gid_list;
2827 }
2828 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2829 ctx_cachep);
2830 if (!ha->ctx_mempool)
2831 goto fail_free_srb_mempool;
2832 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2833 "ctx_cachep=%p ctx_mempool=%p.\n",
2834 ctx_cachep, ha->ctx_mempool);
2835 }
2836
2837
2838 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2839 if (!ha->nvram)
2840 goto fail_free_ctx_mempool;
2841
2842 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2843 ha->pdev->device);
2844 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2845 DMA_POOL_SIZE, 8, 0);
2846 if (!ha->s_dma_pool)
2847 goto fail_free_nvram;
2848
2849 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2850 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2851 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2852
2853 if (IS_QLA82XX(ha) || ql2xenabledif) {
2854 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2855 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2856 if (!ha->dl_dma_pool) {
2857 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2858 "Failed to allocate memory for dl_dma_pool.\n");
2859 goto fail_s_dma_pool;
2860 }
2861
2862 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2863 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2864 if (!ha->fcp_cmnd_dma_pool) {
2865 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2866 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
2867 goto fail_dl_dma_pool;
2868 }
2869 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2870 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2871 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
2872 }
2873
2874
2875 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2876
2877 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
2878 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
2879 if (!ha->sns_cmd)
2880 goto fail_dma_pool;
2881 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
2882 "sns_cmd.\n", ha->sns_cmd);
2883 } else {
2884
2885 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2886 &ha->ms_iocb_dma);
2887 if (!ha->ms_iocb)
2888 goto fail_dma_pool;
2889
2890 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
2891 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
2892 if (!ha->ct_sns)
2893 goto fail_free_ms_iocb;
2894 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2895 "ms_iocb=%p ct_sns=%p.\n",
2896 ha->ms_iocb, ha->ct_sns);
2897 }
2898
2899
2900 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2901 if (!*req) {
2902 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2903 "Failed to allocate memory for req.\n");
2904 goto fail_req;
2905 }
2906 (*req)->length = req_len;
2907 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2908 ((*req)->length + 1) * sizeof(request_t),
2909 &(*req)->dma, GFP_KERNEL);
2910 if (!(*req)->ring) {
2911 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2912 "Failed to allocate memory for req_ring.\n");
2913 goto fail_req_ring;
2914 }
2915
2916 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2917 if (!*rsp) {
2918 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2919 "Failed to allocate memory for rsp.\n");
2920 goto fail_rsp;
2921 }
2922 (*rsp)->hw = ha;
2923 (*rsp)->length = rsp_len;
2924 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2925 ((*rsp)->length + 1) * sizeof(response_t),
2926 &(*rsp)->dma, GFP_KERNEL);
2927 if (!(*rsp)->ring) {
2928 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2929 "Failed to allocate memory for rsp_ring.\n");
2930 goto fail_rsp_ring;
2931 }
2932 (*req)->rsp = *rsp;
2933 (*rsp)->req = *req;
2934 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2935 "req=%p req->length=%d req->ring=%p rsp=%p "
2936 "rsp->length=%d rsp->ring=%p.\n",
2937 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2938 (*rsp)->ring);
2939
2940 if (ha->nvram_npiv_size) {
2941 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
2942 ha->nvram_npiv_size, GFP_KERNEL);
2943 if (!ha->npiv_info) {
2944 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2945 "Failed to allocate memory for npiv_info.\n");
2946 goto fail_npiv_info;
2947 }
2948 } else
2949 ha->npiv_info = NULL;
2950
2951
2952 if (IS_QLA8XXX_TYPE(ha)) {
2953 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2954 &ha->ex_init_cb_dma);
2955 if (!ha->ex_init_cb)
2956 goto fail_ex_init_cb;
2957 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2958 "ex_init_cb=%p.\n", ha->ex_init_cb);
2959 }
2960
2961 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2962
2963
2964 if (!IS_FWI2_CAPABLE(ha)) {
2965 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2966 &ha->async_pd_dma);
2967 if (!ha->async_pd)
2968 goto fail_async_pd;
2969 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2970 "async_pd=%p.\n", ha->async_pd);
2971 }
2972
2973 INIT_LIST_HEAD(&ha->vp_list);
2974 return 1;
2975
2976fail_async_pd:
2977 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
2978fail_ex_init_cb:
2979 kfree(ha->npiv_info);
2980fail_npiv_info:
2981 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2982 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2983 (*rsp)->ring = NULL;
2984 (*rsp)->dma = 0;
2985fail_rsp_ring:
2986 kfree(*rsp);
2987fail_rsp:
2988 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
2989 sizeof(request_t), (*req)->ring, (*req)->dma);
2990 (*req)->ring = NULL;
2991 (*req)->dma = 0;
2992fail_req_ring:
2993 kfree(*req);
2994fail_req:
2995 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
2996 ha->ct_sns, ha->ct_sns_dma);
2997 ha->ct_sns = NULL;
2998 ha->ct_sns_dma = 0;
2999fail_free_ms_iocb:
3000 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3001 ha->ms_iocb = NULL;
3002 ha->ms_iocb_dma = 0;
3003fail_dma_pool:
3004 if (IS_QLA82XX(ha) || ql2xenabledif) {
3005 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3006 ha->fcp_cmnd_dma_pool = NULL;
3007 }
3008fail_dl_dma_pool:
3009 if (IS_QLA82XX(ha) || ql2xenabledif) {
3010 dma_pool_destroy(ha->dl_dma_pool);
3011 ha->dl_dma_pool = NULL;
3012 }
3013fail_s_dma_pool:
3014 dma_pool_destroy(ha->s_dma_pool);
3015 ha->s_dma_pool = NULL;
3016fail_free_nvram:
3017 kfree(ha->nvram);
3018 ha->nvram = NULL;
3019fail_free_ctx_mempool:
3020 mempool_destroy(ha->ctx_mempool);
3021 ha->ctx_mempool = NULL;
3022fail_free_srb_mempool:
3023 mempool_destroy(ha->srb_mempool);
3024 ha->srb_mempool = NULL;
3025fail_free_gid_list:
3026 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
3027 ha->gid_list_dma);
3028 ha->gid_list = NULL;
3029 ha->gid_list_dma = 0;
3030fail_free_init_cb:
3031 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3032 ha->init_cb_dma);
3033 ha->init_cb = NULL;
3034 ha->init_cb_dma = 0;
3035fail:
3036 ql_log(ql_log_fatal, NULL, 0x0030,
3037 "Memory allocation failure.\n");
3038 return -ENOMEM;
3039}
3040
3041
3042
3043
3044
3045
3046
3047
3048static void
3049qla2x00_free_fw_dump(struct qla_hw_data *ha)
3050{
3051 if (ha->fce)
3052 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
3053 ha->fce_dma);
3054
3055 if (ha->fw_dump) {
3056 if (ha->eft)
3057 dma_free_coherent(&ha->pdev->dev,
3058 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
3059 vfree(ha->fw_dump);
3060 }
3061 ha->fce = NULL;
3062 ha->fce_dma = 0;
3063 ha->eft = NULL;
3064 ha->eft_dma = 0;
3065 ha->fw_dump = NULL;
3066 ha->fw_dumped = 0;
3067 ha->fw_dump_reading = 0;
3068}
3069
3070
3071
3072
3073
3074
3075
3076
3077static void
3078qla2x00_mem_free(struct qla_hw_data *ha)
3079{
3080 qla2x00_free_fw_dump(ha);
3081
3082 if (ha->srb_mempool)
3083 mempool_destroy(ha->srb_mempool);
3084
3085 if (ha->dcbx_tlv)
3086 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3087 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3088
3089 if (ha->xgmac_data)
3090 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3091 ha->xgmac_data, ha->xgmac_data_dma);
3092
3093 if (ha->sns_cmd)
3094 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3095 ha->sns_cmd, ha->sns_cmd_dma);
3096
3097 if (ha->ct_sns)
3098 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3099 ha->ct_sns, ha->ct_sns_dma);
3100
3101 if (ha->sfp_data)
3102 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3103
3104 if (ha->edc_data)
3105 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3106
3107 if (ha->ms_iocb)
3108 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3109
3110 if (ha->ex_init_cb)
3111 dma_pool_free(ha->s_dma_pool,
3112 ha->ex_init_cb, ha->ex_init_cb_dma);
3113
3114 if (ha->async_pd)
3115 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3116
3117 if (ha->s_dma_pool)
3118 dma_pool_destroy(ha->s_dma_pool);
3119
3120 if (ha->gid_list)
3121 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
3122 ha->gid_list_dma);
3123
3124 if (IS_QLA82XX(ha)) {
3125 if (!list_empty(&ha->gbl_dsd_list)) {
3126 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3127
3128
3129 list_for_each_entry_safe(dsd_ptr,
3130 tdsd_ptr, &ha->gbl_dsd_list, list) {
3131 dma_pool_free(ha->dl_dma_pool,
3132 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3133 list_del(&dsd_ptr->list);
3134 kfree(dsd_ptr);
3135 }
3136 }
3137 }
3138
3139 if (ha->dl_dma_pool)
3140 dma_pool_destroy(ha->dl_dma_pool);
3141
3142 if (ha->fcp_cmnd_dma_pool)
3143 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3144
3145 if (ha->ctx_mempool)
3146 mempool_destroy(ha->ctx_mempool);
3147
3148 if (ha->init_cb)
3149 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3150 ha->init_cb, ha->init_cb_dma);
3151 vfree(ha->optrom_buffer);
3152 kfree(ha->nvram);
3153 kfree(ha->npiv_info);
3154
3155 ha->srb_mempool = NULL;
3156 ha->ctx_mempool = NULL;
3157 ha->sns_cmd = NULL;
3158 ha->sns_cmd_dma = 0;
3159 ha->ct_sns = NULL;
3160 ha->ct_sns_dma = 0;
3161 ha->ms_iocb = NULL;
3162 ha->ms_iocb_dma = 0;
3163 ha->init_cb = NULL;
3164 ha->init_cb_dma = 0;
3165 ha->ex_init_cb = NULL;
3166 ha->ex_init_cb_dma = 0;
3167 ha->async_pd = NULL;
3168 ha->async_pd_dma = 0;
3169
3170 ha->s_dma_pool = NULL;
3171 ha->dl_dma_pool = NULL;
3172 ha->fcp_cmnd_dma_pool = NULL;
3173
3174 ha->gid_list = NULL;
3175 ha->gid_list_dma = 0;
3176}
3177
3178struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3179 struct qla_hw_data *ha)
3180{
3181 struct Scsi_Host *host;
3182 struct scsi_qla_host *vha = NULL;
3183
3184 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3185 if (host == NULL) {
3186 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3187 "Failed to allocate host from the scsi layer, aborting.\n");
3188 goto fail;
3189 }
3190
3191
3192 vha = shost_priv(host);
3193 memset(vha, 0, sizeof(scsi_qla_host_t));
3194
3195 vha->host = host;
3196 vha->host_no = host->host_no;
3197 vha->hw = ha;
3198
3199 INIT_LIST_HEAD(&vha->vp_fcports);
3200 INIT_LIST_HEAD(&vha->work_list);
3201 INIT_LIST_HEAD(&vha->list);
3202
3203 spin_lock_init(&vha->work_lock);
3204
3205 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3206 ql_dbg(ql_dbg_init, vha, 0x0041,
3207 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3208 vha->host, vha->hw, vha,
3209 dev_name(&(ha->pdev->dev)));
3210
3211 return vha;
3212
3213fail:
3214 return vha;
3215}
3216
3217static struct qla_work_evt *
3218qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3219{
3220 struct qla_work_evt *e;
3221 uint8_t bail;
3222
3223 QLA_VHA_MARK_BUSY(vha, bail);
3224 if (bail)
3225 return NULL;
3226
3227 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3228 if (!e) {
3229 QLA_VHA_MARK_NOT_BUSY(vha);
3230 return NULL;
3231 }
3232
3233 INIT_LIST_HEAD(&e->list);
3234 e->type = type;
3235 e->flags = QLA_EVT_FLAG_FREE;
3236 return e;
3237}
3238
3239static int
3240qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3241{
3242 unsigned long flags;
3243
3244 spin_lock_irqsave(&vha->work_lock, flags);
3245 list_add_tail(&e->list, &vha->work_list);
3246 spin_unlock_irqrestore(&vha->work_lock, flags);
3247 qla2xxx_wake_dpc(vha);
3248
3249 return QLA_SUCCESS;
3250}
3251
3252int
3253qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3254 u32 data)
3255{
3256 struct qla_work_evt *e;
3257
3258 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3259 if (!e)
3260 return QLA_FUNCTION_FAILED;
3261
3262 e->u.aen.code = code;
3263 e->u.aen.data = data;
3264 return qla2x00_post_work(vha, e);
3265}
3266
3267int
3268qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3269{
3270 struct qla_work_evt *e;
3271
3272 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3273 if (!e)
3274 return QLA_FUNCTION_FAILED;
3275
3276 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3277 return qla2x00_post_work(vha, e);
3278}
3279
3280#define qla2x00_post_async_work(name, type) \
3281int qla2x00_post_async_##name##_work( \
3282 struct scsi_qla_host *vha, \
3283 fc_port_t *fcport, uint16_t *data) \
3284{ \
3285 struct qla_work_evt *e; \
3286 \
3287 e = qla2x00_alloc_work(vha, type); \
3288 if (!e) \
3289 return QLA_FUNCTION_FAILED; \
3290 \
3291 e->u.logio.fcport = fcport; \
3292 if (data) { \
3293 e->u.logio.data[0] = data[0]; \
3294 e->u.logio.data[1] = data[1]; \
3295 } \
3296 return qla2x00_post_work(vha, e); \
3297}
3298
3299qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3300qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3301qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3302qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3303qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3304qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3305
3306int
3307qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3308{
3309 struct qla_work_evt *e;
3310
3311 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3312 if (!e)
3313 return QLA_FUNCTION_FAILED;
3314
3315 e->u.uevent.code = code;
3316 return qla2x00_post_work(vha, e);
3317}
3318
3319static void
3320qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3321{
3322 char event_string[40];
3323 char *envp[] = { event_string, NULL };
3324
3325 switch (code) {
3326 case QLA_UEVENT_CODE_FW_DUMP:
3327 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3328 vha->host_no);
3329 break;
3330 default:
3331
3332 break;
3333 }
3334 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3335}
3336
3337void
3338qla2x00_do_work(struct scsi_qla_host *vha)
3339{
3340 struct qla_work_evt *e, *tmp;
3341 unsigned long flags;
3342 LIST_HEAD(work);
3343
3344 spin_lock_irqsave(&vha->work_lock, flags);
3345 list_splice_init(&vha->work_list, &work);
3346 spin_unlock_irqrestore(&vha->work_lock, flags);
3347
3348 list_for_each_entry_safe(e, tmp, &work, list) {
3349 list_del_init(&e->list);
3350
3351 switch (e->type) {
3352 case QLA_EVT_AEN:
3353 fc_host_post_event(vha->host, fc_get_event_number(),
3354 e->u.aen.code, e->u.aen.data);
3355 break;
3356 case QLA_EVT_IDC_ACK:
3357 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3358 break;
3359 case QLA_EVT_ASYNC_LOGIN:
3360 qla2x00_async_login(vha, e->u.logio.fcport,
3361 e->u.logio.data);
3362 break;
3363 case QLA_EVT_ASYNC_LOGIN_DONE:
3364 qla2x00_async_login_done(vha, e->u.logio.fcport,
3365 e->u.logio.data);
3366 break;
3367 case QLA_EVT_ASYNC_LOGOUT:
3368 qla2x00_async_logout(vha, e->u.logio.fcport);
3369 break;
3370 case QLA_EVT_ASYNC_LOGOUT_DONE:
3371 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3372 e->u.logio.data);
3373 break;
3374 case QLA_EVT_ASYNC_ADISC:
3375 qla2x00_async_adisc(vha, e->u.logio.fcport,
3376 e->u.logio.data);
3377 break;
3378 case QLA_EVT_ASYNC_ADISC_DONE:
3379 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3380 e->u.logio.data);
3381 break;
3382 case QLA_EVT_UEVENT:
3383 qla2x00_uevent_emit(vha, e->u.uevent.code);
3384 break;
3385 }
3386 if (e->flags & QLA_EVT_FLAG_FREE)
3387 kfree(e);
3388
3389
3390 QLA_VHA_MARK_NOT_BUSY(vha);
3391 }
3392}
3393
3394
3395
3396
3397void qla2x00_relogin(struct scsi_qla_host *vha)
3398{
3399 fc_port_t *fcport;
3400 int status;
3401 uint16_t next_loopid = 0;
3402 struct qla_hw_data *ha = vha->hw;
3403 uint16_t data[2];
3404
3405 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3406
3407
3408
3409
3410 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3411 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
3412 fcport->login_retry--;
3413 if (fcport->flags & FCF_FABRIC_DEVICE) {
3414 if (fcport->flags & FCF_FCP2_DEVICE)
3415 ha->isp_ops->fabric_logout(vha,
3416 fcport->loop_id,
3417 fcport->d_id.b.domain,
3418 fcport->d_id.b.area,
3419 fcport->d_id.b.al_pa);
3420
3421 if (fcport->loop_id == FC_NO_LOOP_ID) {
3422 fcport->loop_id = next_loopid =
3423 ha->min_external_loopid;
3424 status = qla2x00_find_new_loop_id(
3425 vha, fcport);
3426 if (status != QLA_SUCCESS) {
3427
3428 break;
3429 }
3430 }
3431
3432 if (IS_ALOGIO_CAPABLE(ha)) {
3433 fcport->flags |= FCF_ASYNC_SENT;
3434 data[0] = 0;
3435 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3436 status = qla2x00_post_async_login_work(
3437 vha, fcport, data);
3438 if (status == QLA_SUCCESS)
3439 continue;
3440
3441 status = 1;
3442 } else
3443 status = qla2x00_fabric_login(vha,
3444 fcport, &next_loopid);
3445 } else
3446 status = qla2x00_local_device_login(vha,
3447 fcport);
3448
3449 if (status == QLA_SUCCESS) {
3450 fcport->old_loop_id = fcport->loop_id;
3451
3452 ql_dbg(ql_dbg_disc, vha, 0x2003,
3453 "Port login OK: logged in ID 0x%x.\n",
3454 fcport->loop_id);
3455
3456 qla2x00_update_fcport(vha, fcport);
3457
3458 } else if (status == 1) {
3459 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3460
3461 ql_dbg(ql_dbg_disc, vha, 0x2007,
3462 "Retrying %d login again loop_id 0x%x.\n",
3463 fcport->login_retry, fcport->loop_id);
3464 } else {
3465 fcport->login_retry = 0;
3466 }
3467
3468 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3469 fcport->loop_id = FC_NO_LOOP_ID;
3470 }
3471 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3472 break;
3473 }
3474}
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489static int
3490qla2x00_do_dpc(void *data)
3491{
3492 int rval;
3493 scsi_qla_host_t *base_vha;
3494 struct qla_hw_data *ha;
3495
3496 ha = (struct qla_hw_data *)data;
3497 base_vha = pci_get_drvdata(ha->pdev);
3498
3499 set_user_nice(current, -20);
3500
3501 set_current_state(TASK_INTERRUPTIBLE);
3502 while (!kthread_should_stop()) {
3503 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3504 "DPC handler sleeping.\n");
3505
3506 schedule();
3507 __set_current_state(TASK_RUNNING);
3508
3509 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3510 "DPC handler waking up.\n");
3511 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3512 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
3513
3514
3515 if (!base_vha->flags.init_done)
3516 continue;
3517
3518 if (ha->flags.eeh_busy) {
3519 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3520 "eeh_busy=%d.\n", ha->flags.eeh_busy);
3521 continue;
3522 }
3523
3524 ha->dpc_active = 1;
3525
3526 if (ha->flags.mbox_busy) {
3527 ha->dpc_active = 0;
3528 continue;
3529 }
3530
3531 qla2x00_do_work(base_vha);
3532
3533 if (IS_QLA82XX(ha)) {
3534 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3535 &base_vha->dpc_flags)) {
3536 qla82xx_idc_lock(ha);
3537 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3538 QLA82XX_DEV_FAILED);
3539 qla82xx_idc_unlock(ha);
3540 ql_log(ql_log_info, base_vha, 0x4004,
3541 "HW State: FAILED.\n");
3542 qla82xx_device_state_handler(base_vha);
3543 continue;
3544 }
3545
3546 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3547 &base_vha->dpc_flags)) {
3548
3549 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3550 "FCoE context reset scheduled.\n");
3551 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3552 &base_vha->dpc_flags))) {
3553 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3554
3555
3556
3557 set_bit(ISP_ABORT_NEEDED,
3558 &base_vha->dpc_flags);
3559 }
3560 clear_bit(ABORT_ISP_ACTIVE,
3561 &base_vha->dpc_flags);
3562 }
3563
3564 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3565 "FCoE context reset end.\n");
3566 }
3567 }
3568
3569 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3570 &base_vha->dpc_flags)) {
3571
3572 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3573 "ISP abort scheduled.\n");
3574 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3575 &base_vha->dpc_flags))) {
3576
3577 if (ha->isp_ops->abort_isp(base_vha)) {
3578
3579 set_bit(ISP_ABORT_NEEDED,
3580 &base_vha->dpc_flags);
3581 }
3582 clear_bit(ABORT_ISP_ACTIVE,
3583 &base_vha->dpc_flags);
3584 }
3585
3586 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3587 "ISP abort end.\n");
3588 }
3589
3590 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3591 qla2x00_update_fcports(base_vha);
3592 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3593 }
3594
3595 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
3596 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3597 "Quiescence mode scheduled.\n");
3598 qla82xx_device_state_handler(base_vha);
3599 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3600 if (!ha->flags.quiesce_owner) {
3601 qla2x00_perform_loop_resync(base_vha);
3602
3603 qla82xx_idc_lock(ha);
3604 qla82xx_clear_qsnt_ready(base_vha);
3605 qla82xx_idc_unlock(ha);
3606 }
3607 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3608 "Quiescence mode end.\n");
3609 }
3610
3611 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3612 &base_vha->dpc_flags) &&
3613 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
3614
3615 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3616 "Reset marker scheduled.\n");
3617 qla2x00_rst_aen(base_vha);
3618 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
3619 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3620 "Reset marker end.\n");
3621 }
3622
3623
3624 if ((test_and_clear_bit(RELOGIN_NEEDED,
3625 &base_vha->dpc_flags)) &&
3626 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3627 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
3628
3629 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3630 "Relogin scheduled.\n");
3631 qla2x00_relogin(base_vha);
3632 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3633 "Relogin end.\n");
3634 }
3635
3636 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3637 &base_vha->dpc_flags)) {
3638
3639 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3640 "Loop resync scheduled.\n");
3641
3642 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
3643 &base_vha->dpc_flags))) {
3644
3645 rval = qla2x00_loop_resync(base_vha);
3646
3647 clear_bit(LOOP_RESYNC_ACTIVE,
3648 &base_vha->dpc_flags);
3649 }
3650
3651 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3652 "Loop resync end.\n");
3653 }
3654
3655 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3656 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3657 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3658 qla2xxx_flash_npiv_conf(base_vha);
3659 }
3660
3661 if (!ha->interrupts_on)
3662 ha->isp_ops->enable_intrs(ha);
3663
3664 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3665 &base_vha->dpc_flags))
3666 ha->isp_ops->beacon_blink(base_vha);
3667
3668 qla2x00_do_dpc_all_vps(base_vha);
3669
3670 ha->dpc_active = 0;
3671 set_current_state(TASK_INTERRUPTIBLE);
3672 }
3673 __set_current_state(TASK_RUNNING);
3674
3675 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3676 "DPC handler exiting.\n");
3677
3678
3679
3680
3681 ha->dpc_active = 0;
3682
3683
3684 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3685
3686 return 0;
3687}
3688
3689void
3690qla2xxx_wake_dpc(struct scsi_qla_host *vha)
3691{
3692 struct qla_hw_data *ha = vha->hw;
3693 struct task_struct *t = ha->dpc_thread;
3694
3695 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
3696 wake_up_process(t);
3697}
3698
3699
3700
3701
3702
3703
3704
3705
3706static void
3707qla2x00_rst_aen(scsi_qla_host_t *vha)
3708{
3709 if (vha->flags.online && !vha->flags.reset_active &&
3710 !atomic_read(&vha->loop_down_timer) &&
3711 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
3712 do {
3713 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
3714
3715
3716
3717
3718
3719 vha->marker_needed = 1;
3720 } while (!atomic_read(&vha->loop_down_timer) &&
3721 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
3722 }
3723}
3724
3725static void
3726qla2x00_sp_free_dma(srb_t *sp)
3727{
3728 struct scsi_cmnd *cmd = sp->cmd;
3729 struct qla_hw_data *ha = sp->fcport->vha->hw;
3730
3731 if (sp->flags & SRB_DMA_VALID) {
3732 scsi_dma_unmap(cmd);
3733 sp->flags &= ~SRB_DMA_VALID;
3734 }
3735
3736 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3737 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3738 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3739 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3740 }
3741
3742 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3743
3744 qla2x00_clean_dsd_pool(ha, sp);
3745 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3746 }
3747
3748 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3749 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3750 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3751 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3752 }
3753
3754 CMD_SP(cmd) = NULL;
3755}
3756
3757static void
3758qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
3759{
3760 struct scsi_cmnd *cmd = sp->cmd;
3761
3762 qla2x00_sp_free_dma(sp);
3763
3764 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3765 struct ct6_dsd *ctx = sp->ctx;
3766 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3767 ctx->fcp_cmnd_dma);
3768 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3769 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3770 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3771 mempool_free(sp->ctx, ha->ctx_mempool);
3772 sp->ctx = NULL;
3773 }
3774
3775 mempool_free(sp, ha->srb_mempool);
3776 cmd->scsi_done(cmd);
3777}
3778
3779void
3780qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3781{
3782 if (atomic_read(&sp->ref_count) == 0) {
3783 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3784 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3785 sp, sp->cmd);
3786 if (ql2xextended_error_logging & ql_dbg_io)
3787 BUG();
3788 return;
3789 }
3790 if (!atomic_dec_and_test(&sp->ref_count))
3791 return;
3792 qla2x00_sp_final_compl(ha, sp);
3793}
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803void
3804qla2x00_timer(scsi_qla_host_t *vha)
3805{
3806 unsigned long cpu_flags = 0;
3807 int start_dpc = 0;
3808 int index;
3809 srb_t *sp;
3810 uint16_t w;
3811 struct qla_hw_data *ha = vha->hw;
3812 struct req_que *req;
3813
3814 if (ha->flags.eeh_busy) {
3815 ql_dbg(ql_dbg_timer, vha, 0x6000,
3816 "EEH = %d, restarting timer.\n",
3817 ha->flags.eeh_busy);
3818 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3819 return;
3820 }
3821
3822
3823 if (!pci_channel_offline(ha->pdev))
3824 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
3825
3826
3827 if (!vha->vp_idx && IS_QLA82XX(ha)) {
3828 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3829 start_dpc++;
3830 qla82xx_watchdog(vha);
3831 }
3832
3833
3834 if (atomic_read(&vha->loop_down_timer) > 0 &&
3835 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3836 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
3837 && vha->flags.online) {
3838
3839 if (atomic_read(&vha->loop_down_timer) ==
3840 vha->loop_down_abort_time) {
3841
3842 ql_log(ql_log_info, vha, 0x6008,
3843 "Loop down - aborting the queues before time expires.\n");
3844
3845 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3846 atomic_set(&vha->loop_state, LOOP_DEAD);
3847
3848
3849
3850
3851
3852
3853 if (!vha->vp_idx) {
3854 spin_lock_irqsave(&ha->hardware_lock,
3855 cpu_flags);
3856 req = ha->req_q_map[0];
3857 for (index = 1;
3858 index < MAX_OUTSTANDING_COMMANDS;
3859 index++) {
3860 fc_port_t *sfcp;
3861
3862 sp = req->outstanding_cmds[index];
3863 if (!sp)
3864 continue;
3865 if (sp->ctx && !IS_PROT_IO(sp))
3866 continue;
3867 sfcp = sp->fcport;
3868 if (!(sfcp->flags & FCF_FCP2_DEVICE))
3869 continue;
3870
3871 if (IS_QLA82XX(ha))
3872 set_bit(FCOE_CTX_RESET_NEEDED,
3873 &vha->dpc_flags);
3874 else
3875 set_bit(ISP_ABORT_NEEDED,
3876 &vha->dpc_flags);
3877 break;
3878 }
3879 spin_unlock_irqrestore(&ha->hardware_lock,
3880 cpu_flags);
3881 }
3882 start_dpc++;
3883 }
3884
3885
3886 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
3887 if (!(vha->device_flags & DFLG_NO_CABLE)) {
3888 ql_log(ql_log_warn, vha, 0x6009,
3889 "Loop down - aborting ISP.\n");
3890
3891 if (IS_QLA82XX(ha))
3892 set_bit(FCOE_CTX_RESET_NEEDED,
3893 &vha->dpc_flags);
3894 else
3895 set_bit(ISP_ABORT_NEEDED,
3896 &vha->dpc_flags);
3897 }
3898 }
3899 ql_dbg(ql_dbg_timer, vha, 0x600a,
3900 "Loop down - seconds remaining %d.\n",
3901 atomic_read(&vha->loop_down_timer));
3902 }
3903
3904
3905 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
3906 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
3907 start_dpc++;
3908 }
3909
3910
3911 if (!list_empty(&vha->work_list))
3912 start_dpc++;
3913
3914
3915 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3916 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3917 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
3918 start_dpc ||
3919 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3920 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
3921 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3922 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3923 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
3924 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3925 ql_dbg(ql_dbg_timer, vha, 0x600b,
3926 "isp_abort_needed=%d loop_resync_needed=%d "
3927 "fcport_update_needed=%d start_dpc=%d "
3928 "reset_marker_needed=%d",
3929 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3930 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3931 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3932 start_dpc,
3933 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3934 ql_dbg(ql_dbg_timer, vha, 0x600c,
3935 "beacon_blink_needed=%d isp_unrecoverable=%d "
3936 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3937 "relogin_needed=%d.\n",
3938 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3939 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3940 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3941 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3942 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
3943 qla2xxx_wake_dpc(vha);
3944 }
3945
3946 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3947}
3948
3949
3950
3951#define FW_BLOBS 8
3952#define FW_ISP21XX 0
3953#define FW_ISP22XX 1
3954#define FW_ISP2300 2
3955#define FW_ISP2322 3
3956#define FW_ISP24XX 4
3957#define FW_ISP25XX 5
3958#define FW_ISP81XX 6
3959#define FW_ISP82XX 7
3960
3961#define FW_FILE_ISP21XX "ql2100_fw.bin"
3962#define FW_FILE_ISP22XX "ql2200_fw.bin"
3963#define FW_FILE_ISP2300 "ql2300_fw.bin"
3964#define FW_FILE_ISP2322 "ql2322_fw.bin"
3965#define FW_FILE_ISP24XX "ql2400_fw.bin"
3966#define FW_FILE_ISP25XX "ql2500_fw.bin"
3967#define FW_FILE_ISP81XX "ql8100_fw.bin"
3968#define FW_FILE_ISP82XX "ql8200_fw.bin"
3969
3970static DEFINE_MUTEX(qla_fw_lock);
3971
3972static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
3973 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3974 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3975 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3976 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3977 { .name = FW_FILE_ISP24XX, },
3978 { .name = FW_FILE_ISP25XX, },
3979 { .name = FW_FILE_ISP81XX, },
3980 { .name = FW_FILE_ISP82XX, },
3981};
3982
3983struct fw_blob *
3984qla2x00_request_firmware(scsi_qla_host_t *vha)
3985{
3986 struct qla_hw_data *ha = vha->hw;
3987 struct fw_blob *blob;
3988
3989 blob = NULL;
3990 if (IS_QLA2100(ha)) {
3991 blob = &qla_fw_blobs[FW_ISP21XX];
3992 } else if (IS_QLA2200(ha)) {
3993 blob = &qla_fw_blobs[FW_ISP22XX];
3994 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3995 blob = &qla_fw_blobs[FW_ISP2300];
3996 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
3997 blob = &qla_fw_blobs[FW_ISP2322];
3998 } else if (IS_QLA24XX_TYPE(ha)) {
3999 blob = &qla_fw_blobs[FW_ISP24XX];
4000 } else if (IS_QLA25XX(ha)) {
4001 blob = &qla_fw_blobs[FW_ISP25XX];
4002 } else if (IS_QLA81XX(ha)) {
4003 blob = &qla_fw_blobs[FW_ISP81XX];
4004 } else if (IS_QLA82XX(ha)) {
4005 blob = &qla_fw_blobs[FW_ISP82XX];
4006 }
4007
4008 mutex_lock(&qla_fw_lock);
4009 if (blob->fw)
4010 goto out;
4011
4012 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
4013 ql_log(ql_log_warn, vha, 0x0063,
4014 "Failed to load firmware image (%s).\n", blob->name);
4015 blob->fw = NULL;
4016 blob = NULL;
4017 goto out;
4018 }
4019
4020out:
4021 mutex_unlock(&qla_fw_lock);
4022 return blob;
4023}
4024
4025static void
4026qla2x00_release_firmware(void)
4027{
4028 int idx;
4029
4030 mutex_lock(&qla_fw_lock);
4031 for (idx = 0; idx < FW_BLOBS; idx++)
4032 if (qla_fw_blobs[idx].fw)
4033 release_firmware(qla_fw_blobs[idx].fw);
4034 mutex_unlock(&qla_fw_lock);
4035}
4036
4037static pci_ers_result_t
4038qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4039{
4040 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4041 struct qla_hw_data *ha = vha->hw;
4042
4043 ql_dbg(ql_dbg_aer, vha, 0x9000,
4044 "PCI error detected, state %x.\n", state);
4045
4046 switch (state) {
4047 case pci_channel_io_normal:
4048 ha->flags.eeh_busy = 0;
4049 return PCI_ERS_RESULT_CAN_RECOVER;
4050 case pci_channel_io_frozen:
4051 ha->flags.eeh_busy = 1;
4052
4053 if (IS_QLA82XX(ha)) {
4054 ha->flags.isp82xx_fw_hung = 1;
4055 if (ha->flags.mbox_busy) {
4056 ha->flags.mbox_int = 1;
4057 ql_dbg(ql_dbg_aer, vha, 0x9001,
4058 "Due to pci channel io frozen, doing premature "
4059 "completion of mbx command.\n");
4060 complete(&ha->mbx_intr_comp);
4061 }
4062 }
4063 qla2x00_free_irqs(vha);
4064 pci_disable_device(pdev);
4065
4066 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4067 return PCI_ERS_RESULT_NEED_RESET;
4068 case pci_channel_io_perm_failure:
4069 ha->flags.pci_channel_io_perm_failure = 1;
4070 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
4071 return PCI_ERS_RESULT_DISCONNECT;
4072 }
4073 return PCI_ERS_RESULT_NEED_RESET;
4074}
4075
4076static pci_ers_result_t
4077qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4078{
4079 int risc_paused = 0;
4080 uint32_t stat;
4081 unsigned long flags;
4082 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4083 struct qla_hw_data *ha = base_vha->hw;
4084 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4085 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4086
4087 if (IS_QLA82XX(ha))
4088 return PCI_ERS_RESULT_RECOVERED;
4089
4090 spin_lock_irqsave(&ha->hardware_lock, flags);
4091 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4092 stat = RD_REG_DWORD(®->hccr);
4093 if (stat & HCCR_RISC_PAUSE)
4094 risc_paused = 1;
4095 } else if (IS_QLA23XX(ha)) {
4096 stat = RD_REG_DWORD(®->u.isp2300.host_status);
4097 if (stat & HSR_RISC_PAUSED)
4098 risc_paused = 1;
4099 } else if (IS_FWI2_CAPABLE(ha)) {
4100 stat = RD_REG_DWORD(®24->host_status);
4101 if (stat & HSRX_RISC_PAUSED)
4102 risc_paused = 1;
4103 }
4104 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4105
4106 if (risc_paused) {
4107 ql_log(ql_log_info, base_vha, 0x9003,
4108 "RISC paused -- mmio_enabled, Dumping firmware.\n");
4109 ha->isp_ops->fw_dump(base_vha, 0);
4110
4111 return PCI_ERS_RESULT_NEED_RESET;
4112 } else
4113 return PCI_ERS_RESULT_RECOVERED;
4114}
4115
4116uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4117{
4118 uint32_t rval = QLA_FUNCTION_FAILED;
4119 uint32_t drv_active = 0;
4120 struct qla_hw_data *ha = base_vha->hw;
4121 int fn;
4122 struct pci_dev *other_pdev = NULL;
4123
4124 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4125 "Entered %s.\n", __func__);
4126
4127 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4128
4129 if (base_vha->flags.online) {
4130
4131
4132 qla2x00_abort_isp_cleanup(base_vha);
4133 }
4134
4135
4136 fn = PCI_FUNC(ha->pdev->devfn);
4137 while (fn > 0) {
4138 fn--;
4139 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4140 "Finding pci device at function = 0x%x.\n", fn);
4141 other_pdev =
4142 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4143 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4144 fn));
4145
4146 if (!other_pdev)
4147 continue;
4148 if (atomic_read(&other_pdev->enable_cnt)) {
4149 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4150 "Found PCI func available and enable at 0x%x.\n",
4151 fn);
4152 pci_dev_put(other_pdev);
4153 break;
4154 }
4155 pci_dev_put(other_pdev);
4156 }
4157
4158 if (!fn) {
4159
4160 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4161 "This devfn is reset owner = 0x%x.\n",
4162 ha->pdev->devfn);
4163 qla82xx_idc_lock(ha);
4164
4165 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4166 QLA82XX_DEV_INITIALIZING);
4167
4168 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4169 QLA82XX_IDC_VERSION);
4170
4171 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
4172 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4173 "drv_active = 0x%x.\n", drv_active);
4174
4175 qla82xx_idc_unlock(ha);
4176
4177
4178
4179 if (drv_active)
4180 rval = qla82xx_start_firmware(base_vha);
4181 else
4182 rval = QLA_SUCCESS;
4183 qla82xx_idc_lock(ha);
4184
4185 if (rval != QLA_SUCCESS) {
4186 ql_log(ql_log_info, base_vha, 0x900b,
4187 "HW State: FAILED.\n");
4188 qla82xx_clear_drv_active(ha);
4189 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4190 QLA82XX_DEV_FAILED);
4191 } else {
4192 ql_log(ql_log_info, base_vha, 0x900c,
4193 "HW State: READY.\n");
4194 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4195 QLA82XX_DEV_READY);
4196 qla82xx_idc_unlock(ha);
4197 ha->flags.isp82xx_fw_hung = 0;
4198 rval = qla82xx_restart_isp(base_vha);
4199 qla82xx_idc_lock(ha);
4200
4201 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4202 qla82xx_set_drv_active(base_vha);
4203 }
4204 qla82xx_idc_unlock(ha);
4205 } else {
4206 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4207 "This devfn is not reset owner = 0x%x.\n",
4208 ha->pdev->devfn);
4209 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4210 QLA82XX_DEV_READY)) {
4211 ha->flags.isp82xx_fw_hung = 0;
4212 rval = qla82xx_restart_isp(base_vha);
4213 qla82xx_idc_lock(ha);
4214 qla82xx_set_drv_active(base_vha);
4215 qla82xx_idc_unlock(ha);
4216 }
4217 }
4218 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4219
4220 return rval;
4221}
4222
4223static pci_ers_result_t
4224qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4225{
4226 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
4227 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4228 struct qla_hw_data *ha = base_vha->hw;
4229 struct rsp_que *rsp;
4230 int rc, retries = 10;
4231
4232 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4233 "Slot Reset.\n");
4234
4235
4236
4237
4238
4239 pdev->error_state = pci_channel_io_normal;
4240
4241 pci_restore_state(pdev);
4242
4243
4244
4245
4246 pci_save_state(pdev);
4247
4248 if (ha->mem_only)
4249 rc = pci_enable_device_mem(pdev);
4250 else
4251 rc = pci_enable_device(pdev);
4252
4253 if (rc) {
4254 ql_log(ql_log_warn, base_vha, 0x9005,
4255 "Can't re-enable PCI device after reset.\n");
4256 goto exit_slot_reset;
4257 }
4258
4259 rsp = ha->rsp_q_map[0];
4260 if (qla2x00_request_irqs(ha, rsp))
4261 goto exit_slot_reset;
4262
4263 if (ha->isp_ops->pci_config(base_vha))
4264 goto exit_slot_reset;
4265
4266 if (IS_QLA82XX(ha)) {
4267 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4268 ret = PCI_ERS_RESULT_RECOVERED;
4269 goto exit_slot_reset;
4270 } else
4271 goto exit_slot_reset;
4272 }
4273
4274 while (ha->flags.mbox_busy && retries--)
4275 msleep(1000);
4276
4277 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4278 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
4279 ret = PCI_ERS_RESULT_RECOVERED;
4280 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4281
4282
4283exit_slot_reset:
4284 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4285 "slot_reset return %x.\n", ret);
4286
4287 return ret;
4288}
4289
4290static void
4291qla2xxx_pci_resume(struct pci_dev *pdev)
4292{
4293 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4294 struct qla_hw_data *ha = base_vha->hw;
4295 int ret;
4296
4297 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4298 "pci_resume.\n");
4299
4300 ret = qla2x00_wait_for_hba_online(base_vha);
4301 if (ret != QLA_SUCCESS) {
4302 ql_log(ql_log_fatal, base_vha, 0x9002,
4303 "The device failed to resume I/O from slot/link_reset.\n");
4304 }
4305
4306 pci_cleanup_aer_uncorrect_error_status(pdev);
4307
4308 ha->flags.eeh_busy = 0;
4309}
4310
4311static struct pci_error_handlers qla2xxx_err_handler = {
4312 .error_detected = qla2xxx_pci_error_detected,
4313 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4314 .slot_reset = qla2xxx_pci_slot_reset,
4315 .resume = qla2xxx_pci_resume,
4316};
4317
4318static struct pci_device_id qla2xxx_pci_tbl[] = {
4319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
4329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
4331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
4332 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
4333 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
4334 { 0 },
4335};
4336MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4337
4338static struct pci_driver qla2xxx_pci_driver = {
4339 .name = QLA2XXX_DRIVER_NAME,
4340 .driver = {
4341 .owner = THIS_MODULE,
4342 },
4343 .id_table = qla2xxx_pci_tbl,
4344 .probe = qla2x00_probe_one,
4345 .remove = qla2x00_remove_one,
4346 .shutdown = qla2x00_shutdown,
4347 .err_handler = &qla2xxx_err_handler,
4348};
4349
4350static struct file_operations apidev_fops = {
4351 .owner = THIS_MODULE,
4352 .llseek = noop_llseek,
4353};
4354
4355
4356
4357
4358static int __init
4359qla2x00_module_init(void)
4360{
4361 int ret = 0;
4362
4363
4364 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
4365 SLAB_HWCACHE_ALIGN, NULL);
4366 if (srb_cachep == NULL) {
4367 ql_log(ql_log_fatal, NULL, 0x0001,
4368 "Unable to allocate SRB cache...Failing load!.\n");
4369 return -ENOMEM;
4370 }
4371
4372
4373 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
4374 if (ql2xextended_error_logging)
4375 strcat(qla2x00_version_str, "-debug");
4376
4377 qla2xxx_transport_template =
4378 fc_attach_transport(&qla2xxx_transport_functions);
4379 if (!qla2xxx_transport_template) {
4380 kmem_cache_destroy(srb_cachep);
4381 ql_log(ql_log_fatal, NULL, 0x0002,
4382 "fc_attach_transport failed...Failing load!.\n");
4383 return -ENODEV;
4384 }
4385
4386 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4387 if (apidev_major < 0) {
4388 ql_log(ql_log_fatal, NULL, 0x0003,
4389 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
4390 }
4391
4392 qla2xxx_transport_vport_template =
4393 fc_attach_transport(&qla2xxx_transport_vport_functions);
4394 if (!qla2xxx_transport_vport_template) {
4395 kmem_cache_destroy(srb_cachep);
4396 fc_release_transport(qla2xxx_transport_template);
4397 ql_log(ql_log_fatal, NULL, 0x0004,
4398 "fc_attach_transport vport failed...Failing load!.\n");
4399 return -ENODEV;
4400 }
4401 ql_log(ql_log_info, NULL, 0x0005,
4402 "QLogic Fibre Channel HBA Driver: %s.\n",
4403 qla2x00_version_str);
4404 ret = pci_register_driver(&qla2xxx_pci_driver);
4405 if (ret) {
4406 kmem_cache_destroy(srb_cachep);
4407 fc_release_transport(qla2xxx_transport_template);
4408 fc_release_transport(qla2xxx_transport_vport_template);
4409 ql_log(ql_log_fatal, NULL, 0x0006,
4410 "pci_register_driver failed...ret=%d Failing load!.\n",
4411 ret);
4412 }
4413 return ret;
4414}
4415
4416
4417
4418
4419static void __exit
4420qla2x00_module_exit(void)
4421{
4422 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
4423 pci_unregister_driver(&qla2xxx_pci_driver);
4424 qla2x00_release_firmware();
4425 kmem_cache_destroy(srb_cachep);
4426 if (ctx_cachep)
4427 kmem_cache_destroy(ctx_cachep);
4428 fc_release_transport(qla2xxx_transport_template);
4429 fc_release_transport(qla2xxx_transport_vport_template);
4430}
4431
4432module_init(qla2x00_module_init);
4433module_exit(qla2x00_module_exit);
4434
4435MODULE_AUTHOR("QLogic Corporation");
4436MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4437MODULE_LICENSE("GPL");
4438MODULE_VERSION(QLA2XXX_VERSION);
4439MODULE_FIRMWARE(FW_FILE_ISP21XX);
4440MODULE_FIRMWARE(FW_FILE_ISP22XX);
4441MODULE_FIRMWARE(FW_FILE_ISP2300);
4442MODULE_FIRMWARE(FW_FILE_ISP2322);
4443MODULE_FIRMWARE(FW_FILE_ISP24XX);
4444MODULE_FIRMWARE(FW_FILE_ISP25XX);
4445
