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8#ifndef IIO_DAC_AD5446_H_
9#define IIO_DAC_AD5446_H_
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13#define AD5446_LOAD (0x0 << 14)
14#define AD5446_SDO_DIS (0x1 << 14)
15#define AD5446_NOP (0x2 << 14)
16#define AD5446_CLK_RISING (0x3 << 14)
17
18#define AD5620_LOAD (0x0 << 14)
19#define AD5620_PWRDWN_1k (0x1 << 14)
20#define AD5620_PWRDWN_100k (0x2 << 14)
21#define AD5620_PWRDWN_TRISTATE (0x3 << 14)
22
23#define AD5660_LOAD (0x0 << 16)
24#define AD5660_PWRDWN_1k (0x1 << 16)
25#define AD5660_PWRDWN_100k (0x2 << 16)
26#define AD5660_PWRDWN_TRISTATE (0x3 << 16)
27
28#define RES_MASK(bits) ((1 << (bits)) - 1)
29
30#define MODE_PWRDWN_1k 0x1
31#define MODE_PWRDWN_100k 0x2
32#define MODE_PWRDWN_TRISTATE 0x3
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46struct ad5446_state {
47 struct spi_device *spi;
48 const struct ad5446_chip_info *chip_info;
49 struct regulator *reg;
50 struct work_struct poll_work;
51 unsigned short vref_mv;
52 unsigned cached_val;
53 unsigned pwr_down_mode;
54 unsigned pwr_down;
55 struct spi_transfer xfer;
56 struct spi_message msg;
57 union {
58 unsigned short d16;
59 unsigned char d24[3];
60 } data;
61};
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73struct ad5446_chip_info {
74 u8 bits;
75 u8 storagebits;
76 u8 left_shift;
77 u16 int_vref_mv;
78 void (*store_sample) (struct ad5446_state *st, unsigned val);
79 void (*store_pwr_down) (struct ad5446_state *st, unsigned mode);
80};
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90enum ad5446_supported_device_ids {
91 ID_AD5444,
92 ID_AD5446,
93 ID_AD5541A,
94 ID_AD5542A,
95 ID_AD5543,
96 ID_AD5512A,
97 ID_AD5553,
98 ID_AD5601,
99 ID_AD5611,
100 ID_AD5621,
101 ID_AD5620_2500,
102 ID_AD5620_1250,
103 ID_AD5640_2500,
104 ID_AD5640_1250,
105 ID_AD5660_2500,
106 ID_AD5660_1250,
107};
108
109#endif
110