LXR linux/drivers/staging/rtl8192e/r819xE

   1#ifndef _R819XU_PHY_H
   2#define _R819XU_PHY_H
   3
   4/* Channel switch: the size of command tables for switch channel */
   5#define MAX_PRECMD_CNT 16
   6#define MAX_RFDEPENDCMD_CNT 16
   7#define MAX_POSTCMD_CNT 16
   8
   9#define MACPHY_Array_PGLength 30
  10#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
  11#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
  12#define RadioC_ArrayLength 1
  13#define RadioD_ArrayLength 1
  14#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
  15#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
  16#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
  17#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
  18#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
  19#define PHY_REGArrayLength 1
  20#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
  21#define PHY_REG_1T2RArrayLength 296
  22#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
  23
  24#define AGCTAB_ArrayLength 384
  25#define MACPHY_ArrayLength 18
  26
  27#define RadioA_ArrayLength 246
  28#define RadioB_ArrayLength 78
  29
  30
  31typedef enum _SwChnlCmdID {
  32        CmdID_End,
  33        CmdID_SetTxPowerLevel,
  34        CmdID_BBRegWrite10,
  35        CmdID_WritePortUlong,
  36        CmdID_WritePortUshort,
  37        CmdID_WritePortUchar,
  38        CmdID_RF_WriteReg,
  39} SwChnlCmdID;
  40
  41/* switch channel data structure */
  42typedef struct _SwChnlCmd {
  43        SwChnlCmdID CmdID;
  44        u32 Para1;
  45        u32 Para2;
  46        u32 msDelay;
  47} __attribute__ ((packed)) SwChnlCmd;
  48
  49extern u32 rtl819XMACPHY_Array_PG[];
  50extern u32 rtl819XPHY_REG_1T2RArray[];
  51extern u32 rtl819XAGCTAB_Array[];
  52extern u32 rtl819XRadioA_Array[];
  53extern u32 rtl819XRadioB_Array[];
  54extern u32 rtl819XRadioC_Array[];
  55extern u32 rtl819XRadioD_Array[];
  56
  57typedef enum _HW90_BLOCK {
  58        HW90_BLOCK_MAC = 0,
  59        HW90_BLOCK_PHY0 = 1,
  60        HW90_BLOCK_PHY1 = 2,
  61        HW90_BLOCK_RF = 3,
  62        /* Don't ever use this. */
  63        HW90_BLOCK_MAXIMUM = 4,
  64} HW90_BLOCK_E, *PHW90_BLOCK_E;
  65
  66typedef enum _RF90_RADIO_PATH {
  67        /* Radio paths */
  68        RF90_PATH_A = 0,
  69        RF90_PATH_B = 1,
  70        RF90_PATH_C = 2,
  71        RF90_PATH_D = 3,
  72
  73        /* Max RF number 92 support */
  74        RF90_PATH_MAX
  75} RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
  76
  77#define bMaskByte0 0xff
  78#define bMaskByte1 0xff00
  79#define bMaskByte2 0xff0000
  80#define bMaskByte3 0xff000000
  81#define bMaskHWord 0xffff0000
  82#define bMaskLWord 0x0000ffff
  83#define bMaskDWord 0xffffffff
  84
  85u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath);
  86
  87void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr,
  88                             u32 dwBitMask, u32 dwData);
  89
  90u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr,
  91                             u32 dwBitMask);
  92
  93void rtl8192_phy_SetRFReg(struct r8192_priv *priv,
  94                RF90_RADIO_PATH_E eRFPath, u32 RegAddr,
  95                u32 BitMask, u32 Data);
  96
  97u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv,
  98                RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
  99
 100void rtl8192_phy_configmac(struct r8192_priv *priv);
 101
 102void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType);
 103
 104RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv,
 105                HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
 106
 107RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv);
 108
 109void rtl8192_phy_getTxPower(struct r8192_priv *priv);
 110
 111void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel);
 112
 113RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv);
 114
 115void rtl8192_phy_updateInitGain(struct r8192_priv *priv);
 116
 117u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv,
 118                                        RF90_RADIO_PATH_E eRFPath);
 119
 120u8 rtl8192_phy_SwChnl(struct ieee80211_device *ieee80211, u8 channel);
 121
 122void rtl8192_SetBWMode(struct ieee80211_device *ieee80211,
 123                HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
 124
 125void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv);
 126
 127void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv);
 128
 129void InitialGain819xPci(struct ieee80211_device *ieee, u8 Operation);
 130
 131#endif /* _R819XU_PHY_H */
 132