1#ifndef _ISP1760_HCD_H_ 2#define _ISP1760_HCD_H_ 3 4/* exports for if */ 5struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, 6 int irq, unsigned long irqflags, 7 struct device *dev, const char *busname, 8 unsigned int devflags); 9int init_kmem_once(void); 10void deinit_kmem_cache(void); 11 12/* EHCI capability registers */ 13#define HC_CAPLENGTH 0x00 14#define HC_HCSPARAMS 0x04 15#define HC_HCCPARAMS 0x08 16 17/* EHCI operational registers */ 18#define HC_USBCMD 0x20 19#define HC_USBSTS 0x24 20#define HC_FRINDEX 0x2c 21#define HC_CONFIGFLAG 0x60 22#define HC_PORTSC1 0x64 23#define HC_ISO_PTD_DONEMAP_REG 0x130 24#define HC_ISO_PTD_SKIPMAP_REG 0x134 25#define HC_ISO_PTD_LASTPTD_REG 0x138 26#define HC_INT_PTD_DONEMAP_REG 0x140 27#define HC_INT_PTD_SKIPMAP_REG 0x144 28#define HC_INT_PTD_LASTPTD_REG 0x148 29#define HC_ATL_PTD_DONEMAP_REG 0x150 30#define HC_ATL_PTD_SKIPMAP_REG 0x154 31#define HC_ATL_PTD_LASTPTD_REG 0x158 32 33/* Configuration Register */ 34#define HC_HW_MODE_CTRL 0x300 35#define ALL_ATX_RESET (1 << 31) 36#define HW_ANA_DIGI_OC (1 << 15) 37#define HW_DATA_BUS_32BIT (1 << 8) 38#define HW_DACK_POL_HIGH (1 << 6) 39#define HW_DREQ_POL_HIGH (1 << 5) 40#define HW_INTR_HIGH_ACT (1 << 2) 41#define HW_INTR_EDGE_TRIG (1 << 1) 42#define HW_GLOBAL_INTR_EN (1 << 0) 43 44#define HC_CHIP_ID_REG 0x304 45#define HC_SCRATCH_REG 0x308 46 47#define HC_RESET_REG 0x30c 48#define SW_RESET_RESET_HC (1 << 1) 49#define SW_RESET_RESET_ALL (1 << 0) 50 51#define HC_BUFFER_STATUS_REG 0x334 52#define ISO_BUF_FILL (1 << 2) 53#define INT_BUF_FILL (1 << 1) 54#define ATL_BUF_FILL (1 << 0) 55 56#define HC_MEMORY_REG 0x33c 57#define ISP_BANK(x) ((x) << 16) 58 59#define HC_PORT1_CTRL 0x374 60#define PORT1_POWER (3 << 3) 61#define PORT1_INIT1 (1 << 7) 62#define PORT1_INIT2 (1 << 23) 63#define HW_OTG_CTRL_SET 0x374 64#define HW_OTG_CTRL_CLR 0x376 65 66/* Interrupt Register */ 67#define HC_INTERRUPT_REG 0x310 68 69#define HC_INTERRUPT_ENABLE 0x314 70#define HC_ISO_INT (1 << 9) 71#define HC_ATL_INT (1 << 8) 72#define HC_INTL_INT (1 << 7) 73#define HC_EOT_INT (1 << 3) 74#define HC_SOT_INT (1 << 1) 75#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT) 76#define INTERRUPT_ENABLE_SOT_MASK (HC_SOT_INT) 77 78#define HC_ISO_IRQ_MASK_OR_REG 0x318 79#define HC_INT_IRQ_MASK_OR_REG 0x31C 80#define HC_ATL_IRQ_MASK_OR_REG 0x320 81#define HC_ISO_IRQ_MASK_AND_REG 0x324 82#define HC_INT_IRQ_MASK_AND_REG 0x328 83#define HC_ATL_IRQ_MASK_AND_REG 0x32C 84 85/* urb state*/ 86#define DELETE_URB (0x0008) 87#define NO_TRANSFER_ACTIVE (0xffffffff) 88 89/* Philips Proprietary Transfer Descriptor (PTD) */ 90typedef __u32 __bitwise __dw; 91struct ptd { 92 __dw dw0; 93 __dw dw1; 94 __dw dw2; 95 __dw dw3; 96 __dw dw4; 97 __dw dw5; 98 __dw dw6; 99 __dw dw7; 100}; 101#define PTD_OFFSET 0x0400 102#define ISO_PTD_OFFSET 0x0400 103#define INT_PTD_OFFSET 0x0800 104#define ATL_PTD_OFFSET 0x0c00 105#define PAYLOAD_OFFSET 0x1000 106 107struct slotinfo { 108 struct isp1760_qh *qh; 109 struct isp1760_qtd *qtd; 110}; 111 112 113typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 114 struct isp1760_qtd *qtd); 115 116/* 117 * Device flags that can vary from board to board. All of these 118 * indicate the most "atypical" case, so that a devflags of 0 is 119 * a sane default configuration. 120 */ 121#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */ 122#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */ 123#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */ 124#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */ 125#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */ 126#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */ 127#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */ 128#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */ 129 130/* chip memory management */ 131struct memory_chunk { 132 unsigned int start; 133 unsigned int size; 134 unsigned int free; 135}; 136 137/* 138 * 60kb divided in: 139 * - 32 blocks @ 256 bytes 140 * - 20 blocks @ 1024 bytes 141 * - 4 blocks @ 8192 bytes 142 */ 143 144#define BLOCK_1_NUM 32 145#define BLOCK_2_NUM 20 146#define BLOCK_3_NUM 4 147 148#define BLOCK_1_SIZE 256 149#define BLOCK_2_SIZE 1024 150#define BLOCK_3_SIZE 8192 151#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) 152#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE 153#define PAYLOAD_AREA_SIZE 0xf000 154 155/* ATL */ 156/* DW0 */ 157#define DW0_VALID_BIT 1 158#define FROM_DW0_VALID(x) ((x) & 0x01) 159#define TO_DW0_LENGTH(x) (((u32) x) << 3) 160#define TO_DW0_MAXPACKET(x) (((u32) x) << 18) 161#define TO_DW0_MULTI(x) (((u32) x) << 29) 162#define TO_DW0_ENDPOINT(x) (((u32) x) << 31) 163/* DW1 */ 164#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3) 165#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10) 166#define DW1_TRANS_BULK ((u32) 2 << 12) 167#define DW1_TRANS_INT ((u32) 3 << 12) 168#define DW1_TRANS_SPLIT ((u32) 1 << 14) 169#define DW1_SE_USB_LOSPEED ((u32) 2 << 16) 170#define TO_DW1_PORT_NUM(x) (((u32) x) << 18) 171#define TO_DW1_HUB_NUM(x) (((u32) x) << 25) 172/* DW2 */ 173#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8) 174#define TO_DW2_RL(x) ((x) << 25) 175#define FROM_DW2_RL(x) (((x) >> 25) & 0xf) 176/* DW3 */ 177#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff) 178#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff) 179#define TO_DW3_NAKCOUNT(x) ((x) << 19) 180#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf) 181#define TO_DW3_CERR(x) ((x) << 23) 182#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3) 183#define TO_DW3_DATA_TOGGLE(x) ((x) << 25) 184#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1) 185#define TO_DW3_PING(x) ((x) << 26) 186#define FROM_DW3_PING(x) (((x) >> 26) & 0x1) 187#define DW3_ERROR_BIT (1 << 28) 188#define DW3_BABBLE_BIT (1 << 29) 189#define DW3_HALT_BIT (1 << 30) 190#define DW3_ACTIVE_BIT (1 << 31) 191 192#define INT_UNDERRUN (1 << 2) 193#define INT_BABBLE (1 << 1) 194#define INT_EXACT (1 << 0) 195 196#define SETUP_PID (2) 197#define IN_PID (1) 198#define OUT_PID (0) 199 200/* Errata 1 */ 201#define RL_COUNTER (0) 202#define NAK_COUNTER (0) 203#define ERR_COUNTER (2) 204 205#endif /* _ISP1760_HCD_H_ */ 206