LXR linux/include/linux/bcma/bcma_driver

   1#ifndef LINUX_BCMA_DRIVER_CC_H_
   2#define LINUX_BCMA_DRIVER_CC_H_
   3
   4/** ChipCommon core registers. **/
   5#define BCMA_CC_ID                      0x0000
   6#define  BCMA_CC_ID_ID                  0x0000FFFF
   7#define  BCMA_CC_ID_ID_SHIFT            0
   8#define  BCMA_CC_ID_REV                 0x000F0000
   9#define  BCMA_CC_ID_REV_SHIFT           16
  10#define  BCMA_CC_ID_PKG                 0x00F00000
  11#define  BCMA_CC_ID_PKG_SHIFT           20
  12#define  BCMA_CC_ID_NRCORES             0x0F000000
  13#define  BCMA_CC_ID_NRCORES_SHIFT       24
  14#define  BCMA_CC_ID_TYPE                0xF0000000
  15#define  BCMA_CC_ID_TYPE_SHIFT          28
  16#define BCMA_CC_CAP                     0x0004          /* Capabilities */
  17#define  BCMA_CC_CAP_NRUART             0x00000003      /* # of UARTs */
  18#define  BCMA_CC_CAP_MIPSEB             0x00000004      /* MIPS in BigEndian Mode */
  19#define  BCMA_CC_CAP_UARTCLK            0x00000018      /* UART clock select */
  20#define   BCMA_CC_CAP_UARTCLK_INT       0x00000008      /* UARTs are driven by internal divided clock */
  21#define  BCMA_CC_CAP_UARTGPIO           0x00000020      /* UARTs on GPIO 15-12 */
  22#define  BCMA_CC_CAP_EXTBUS             0x000000C0      /* External buses present */
  23#define  BCMA_CC_CAP_FLASHT             0x00000700      /* Flash Type */
  24#define   BCMA_CC_FLASHT_NONE           0x00000000      /* No flash */
  25#define   BCMA_CC_FLASHT_STSER          0x00000100      /* ST serial flash */
  26#define   BCMA_CC_FLASHT_ATSER          0x00000200      /* Atmel serial flash */
  27#define   BCMA_CC_FLASHT_PARA           0x00000700      /* Parallel flash */
  28#define  BCMA_CC_CAP_PLLT               0x00038000      /* PLL Type */
  29#define   BCMA_PLLTYPE_NONE             0x00000000
  30#define   BCMA_PLLTYPE_1                0x00010000      /* 48Mhz base, 3 dividers */
  31#define   BCMA_PLLTYPE_2                0x00020000      /* 48Mhz, 4 dividers */
  32#define   BCMA_PLLTYPE_3                0x00030000      /* 25Mhz, 2 dividers */
  33#define   BCMA_PLLTYPE_4                0x00008000      /* 48Mhz, 4 dividers */
  34#define   BCMA_PLLTYPE_5                0x00018000      /* 25Mhz, 4 dividers */
  35#define   BCMA_PLLTYPE_6                0x00028000      /* 100/200 or 120/240 only */
  36#define   BCMA_PLLTYPE_7                0x00038000      /* 25Mhz, 4 dividers */
  37#define  BCMA_CC_CAP_PCTL               0x00040000      /* Power Control */
  38#define  BCMA_CC_CAP_OTPS               0x00380000      /* OTP size */
  39#define  BCMA_CC_CAP_OTPS_SHIFT         19
  40#define  BCMA_CC_CAP_OTPS_BASE          5
  41#define  BCMA_CC_CAP_JTAGM              0x00400000      /* JTAG master present */
  42#define  BCMA_CC_CAP_BROM               0x00800000      /* Internal boot ROM active */
  43#define  BCMA_CC_CAP_64BIT              0x08000000      /* 64-bit Backplane */
  44#define  BCMA_CC_CAP_PMU                0x10000000      /* PMU available (rev >= 20) */
  45#define  BCMA_CC_CAP_ECI                0x20000000      /* ECI available (rev >= 20) */
  46#define  BCMA_CC_CAP_SPROM              0x40000000      /* SPROM present */
  47#define BCMA_CC_CORECTL                 0x0008
  48#define  BCMA_CC_CORECTL_UARTCLK0       0x00000001      /* Drive UART with internal clock */
  49#define  BCMA_CC_CORECTL_SE             0x00000002      /* sync clk out enable (corerev >= 3) */
  50#define  BCMA_CC_CORECTL_UARTCLKEN      0x00000008      /* UART clock enable (rev >= 21) */
  51#define BCMA_CC_BIST                    0x000C
  52#define BCMA_CC_OTPS                    0x0010          /* OTP status */
  53#define  BCMA_CC_OTPS_PROGFAIL          0x80000000
  54#define  BCMA_CC_OTPS_PROTECT           0x00000007
  55#define  BCMA_CC_OTPS_HW_PROTECT        0x00000001
  56#define  BCMA_CC_OTPS_SW_PROTECT        0x00000002
  57#define  BCMA_CC_OTPS_CID_PROTECT       0x00000004
  58#define BCMA_CC_OTPC                    0x0014          /* OTP control */
  59#define  BCMA_CC_OTPC_RECWAIT           0xFF000000
  60#define  BCMA_CC_OTPC_PROGWAIT          0x00FFFF00
  61#define  BCMA_CC_OTPC_PRW_SHIFT         8
  62#define  BCMA_CC_OTPC_MAXFAIL           0x00000038
  63#define  BCMA_CC_OTPC_VSEL              0x00000006
  64#define  BCMA_CC_OTPC_SELVL             0x00000001
  65#define BCMA_CC_OTPP                    0x0018          /* OTP prog */
  66#define  BCMA_CC_OTPP_COL               0x000000FF
  67#define  BCMA_CC_OTPP_ROW               0x0000FF00
  68#define  BCMA_CC_OTPP_ROW_SHIFT         8
  69#define  BCMA_CC_OTPP_READERR           0x10000000
  70#define  BCMA_CC_OTPP_VALUE             0x20000000
  71#define  BCMA_CC_OTPP_READ              0x40000000
  72#define  BCMA_CC_OTPP_START             0x80000000
  73#define  BCMA_CC_OTPP_BUSY              0x80000000
  74#define BCMA_CC_IRQSTAT                 0x0020
  75#define BCMA_CC_IRQMASK                 0x0024
  76#define  BCMA_CC_IRQ_GPIO               0x00000001      /* gpio intr */
  77#define  BCMA_CC_IRQ_EXT                0x00000002      /* ro: ext intr pin (corerev >= 3) */
  78#define  BCMA_CC_IRQ_WDRESET            0x80000000      /* watchdog reset occurred */
  79#define BCMA_CC_CHIPCTL                 0x0028          /* Rev >= 11 only */
  80#define BCMA_CC_CHIPSTAT                0x002C          /* Rev >= 11 only */
  81#define BCMA_CC_JCMD                    0x0030          /* Rev >= 10 only */
  82#define  BCMA_CC_JCMD_START             0x80000000
  83#define  BCMA_CC_JCMD_BUSY              0x80000000
  84#define  BCMA_CC_JCMD_PAUSE             0x40000000
  85#define  BCMA_CC_JCMD0_ACC_MASK         0x0000F000
  86#define  BCMA_CC_JCMD0_ACC_IRDR         0x00000000
  87#define  BCMA_CC_JCMD0_ACC_DR           0x00001000
  88#define  BCMA_CC_JCMD0_ACC_IR           0x00002000
  89#define  BCMA_CC_JCMD0_ACC_RESET        0x00003000
  90#define  BCMA_CC_JCMD0_ACC_IRPDR        0x00004000
  91#define  BCMA_CC_JCMD0_ACC_PDR          0x00005000
  92#define  BCMA_CC_JCMD0_IRW_MASK         0x00000F00
  93#define  BCMA_CC_JCMD_ACC_MASK          0x000F0000      /* Changes for corerev 11 */
  94#define  BCMA_CC_JCMD_ACC_IRDR          0x00000000
  95#define  BCMA_CC_JCMD_ACC_DR            0x00010000
  96#define  BCMA_CC_JCMD_ACC_IR            0x00020000
  97#define  BCMA_CC_JCMD_ACC_RESET         0x00030000
  98#define  BCMA_CC_JCMD_ACC_IRPDR         0x00040000
  99#define  BCMA_CC_JCMD_ACC_PDR           0x00050000
 100#define  BCMA_CC_JCMD_IRW_MASK          0x00001F00
 101#define  BCMA_CC_JCMD_IRW_SHIFT         8
 102#define  BCMA_CC_JCMD_DRW_MASK          0x0000003F
 103#define BCMA_CC_JIR                     0x0034          /* Rev >= 10 only */
 104#define BCMA_CC_JDR                     0x0038          /* Rev >= 10 only */
 105#define BCMA_CC_JCTL                    0x003C          /* Rev >= 10 only */
 106#define  BCMA_CC_JCTL_FORCE_CLK         4               /* Force clock */
 107#define  BCMA_CC_JCTL_EXT_EN            2               /* Enable external targets */
 108#define  BCMA_CC_JCTL_EN                1               /* Enable Jtag master */
 109#define BCMA_CC_FLASHCTL                0x0040
 110#define  BCMA_CC_FLASHCTL_START         0x80000000
 111#define  BCMA_CC_FLASHCTL_BUSY          BCMA_CC_FLASHCTL_START
 112#define BCMA_CC_FLASHADDR               0x0044
 113#define BCMA_CC_FLASHDATA               0x0048
 114#define BCMA_CC_BCAST_ADDR              0x0050
 115#define BCMA_CC_BCAST_DATA              0x0054
 116#define BCMA_CC_GPIOPULLUP              0x0058          /* Rev >= 20 only */
 117#define BCMA_CC_GPIOPULLDOWN            0x005C          /* Rev >= 20 only */
 118#define BCMA_CC_GPIOIN                  0x0060
 119#define BCMA_CC_GPIOOUT                 0x0064
 120#define BCMA_CC_GPIOOUTEN               0x0068
 121#define BCMA_CC_GPIOCTL                 0x006C
 122#define BCMA_CC_GPIOPOL                 0x0070
 123#define BCMA_CC_GPIOIRQ                 0x0074
 124#define BCMA_CC_WATCHDOG                0x0080
 125#define BCMA_CC_GPIOTIMER               0x0088          /* LED powersave (corerev >= 16) */
 126#define  BCMA_CC_GPIOTIMER_OFFTIME      0x0000FFFF
 127#define  BCMA_CC_GPIOTIMER_OFFTIME_SHIFT        0
 128#define  BCMA_CC_GPIOTIMER_ONTIME       0xFFFF0000
 129#define  BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
 130#define BCMA_CC_GPIOTOUTM               0x008C          /* LED powersave (corerev >= 16) */
 131#define BCMA_CC_CLOCK_N                 0x0090
 132#define BCMA_CC_CLOCK_SB                0x0094
 133#define BCMA_CC_CLOCK_PCI               0x0098
 134#define BCMA_CC_CLOCK_M2                0x009C
 135#define BCMA_CC_CLOCK_MIPS              0x00A0
 136#define BCMA_CC_CLKDIV                  0x00A4          /* Rev >= 3 only */
 137#define  BCMA_CC_CLKDIV_SFLASH          0x0F000000
 138#define  BCMA_CC_CLKDIV_SFLASH_SHIFT    24
 139#define  BCMA_CC_CLKDIV_OTP             0x000F0000
 140#define  BCMA_CC_CLKDIV_OTP_SHIFT       16
 141#define  BCMA_CC_CLKDIV_JTAG            0x00000F00
 142#define  BCMA_CC_CLKDIV_JTAG_SHIFT      8
 143#define  BCMA_CC_CLKDIV_UART            0x000000FF
 144#define BCMA_CC_CAP_EXT                 0x00AC          /* Capabilities */
 145#define BCMA_CC_PLLONDELAY              0x00B0          /* Rev >= 4 only */
 146#define BCMA_CC_FREFSELDELAY            0x00B4          /* Rev >= 4 only */
 147#define BCMA_CC_SLOWCLKCTL              0x00B8          /* 6 <= Rev <= 9 only */
 148#define  BCMA_CC_SLOWCLKCTL_SRC         0x00000007      /* slow clock source mask */
 149#define   BCMA_CC_SLOWCLKCTL_SRC_LPO    0x00000000      /* source of slow clock is LPO */
 150#define   BCMA_CC_SLOWCLKCTL_SRC_XTAL   0x00000001      /* source of slow clock is crystal */
 151#define   BCMA_CC_SLOECLKCTL_SRC_PCI    0x00000002      /* source of slow clock is PCI */
 152#define  BCMA_CC_SLOWCLKCTL_LPOFREQ     0x00000200      /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
 153#define  BCMA_CC_SLOWCLKCTL_LPOPD       0x00000400      /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
 154#define  BCMA_CC_SLOWCLKCTL_FSLOW       0x00000800      /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
 155#define  BCMA_CC_SLOWCLKCTL_IPLL        0x00001000      /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
 156#define  BCMA_CC_SLOWCLKCTL_ENXTAL      0x00002000      /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
 157#define  BCMA_CC_SLOWCLKCTL_XTALPU      0x00004000      /* XtalPU (RO), 1/0: crystal running/disabled */
 158#define  BCMA_CC_SLOWCLKCTL_CLKDIV      0xFFFF0000      /* ClockDivider (SlowClk = 1/(4+divisor)) */
 159#define  BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT        16
 160#define BCMA_CC_SYSCLKCTL               0x00C0          /* Rev >= 3 only */
 161#define  BCMA_CC_SYSCLKCTL_IDLPEN       0x00000001      /* ILPen: Enable Idle Low Power */
 162#define  BCMA_CC_SYSCLKCTL_ALPEN        0x00000002      /* ALPen: Enable Active Low Power */
 163#define  BCMA_CC_SYSCLKCTL_PLLEN        0x00000004      /* ForcePLLOn */
 164#define  BCMA_CC_SYSCLKCTL_FORCEALP     0x00000008      /* Force ALP (or HT if ALPen is not set */
 165#define  BCMA_CC_SYSCLKCTL_FORCEHT      0x00000010      /* Force HT */
 166#define  BCMA_CC_SYSCLKCTL_CLKDIV       0xFFFF0000      /* ClkDiv  (ILP = 1/(4+divisor)) */
 167#define  BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
 168#define BCMA_CC_CLKSTSTR                0x00C4          /* Rev >= 3 only */
 169#define BCMA_CC_EROM                    0x00FC
 170#define BCMA_CC_PCMCIA_CFG              0x0100
 171#define BCMA_CC_PCMCIA_MEMWAIT          0x0104
 172#define BCMA_CC_PCMCIA_ATTRWAIT         0x0108
 173#define BCMA_CC_PCMCIA_IOWAIT           0x010C
 174#define BCMA_CC_IDE_CFG                 0x0110
 175#define BCMA_CC_IDE_MEMWAIT             0x0114
 176#define BCMA_CC_IDE_ATTRWAIT            0x0118
 177#define BCMA_CC_IDE_IOWAIT              0x011C
 178#define BCMA_CC_PROG_CFG                0x0120
 179#define BCMA_CC_PROG_WAITCNT            0x0124
 180#define BCMA_CC_FLASH_CFG               0x0128
 181#define BCMA_CC_FLASH_WAITCNT           0x012C
 182/* 0x1E0 is defined as shared BCMA_CLKCTLST */
 183#define BCMA_CC_HW_WORKAROUND           0x01E4 /* Hardware workaround (rev >= 20) */
 184#define BCMA_CC_UART0_DATA              0x0300
 185#define BCMA_CC_UART0_IMR               0x0304
 186#define BCMA_CC_UART0_FCR               0x0308
 187#define BCMA_CC_UART0_LCR               0x030C
 188#define BCMA_CC_UART0_MCR               0x0310
 189#define BCMA_CC_UART0_LSR               0x0314
 190#define BCMA_CC_UART0_MSR               0x0318
 191#define BCMA_CC_UART0_SCRATCH           0x031C
 192#define BCMA_CC_UART1_DATA              0x0400
 193#define BCMA_CC_UART1_IMR               0x0404
 194#define BCMA_CC_UART1_FCR               0x0408
 195#define BCMA_CC_UART1_LCR               0x040C
 196#define BCMA_CC_UART1_MCR               0x0410
 197#define BCMA_CC_UART1_LSR               0x0414
 198#define BCMA_CC_UART1_MSR               0x0418
 199#define BCMA_CC_UART1_SCRATCH           0x041C
 200/* PMU registers (rev >= 20) */
 201#define BCMA_CC_PMU_CTL                 0x0600 /* PMU control */
 202#define  BCMA_CC_PMU_CTL_ILP_DIV        0xFFFF0000 /* ILP div mask */
 203#define  BCMA_CC_PMU_CTL_ILP_DIV_SHIFT  16
 204#define  BCMA_CC_PMU_CTL_NOILPONW       0x00000200 /* No ILP on wait */
 205#define  BCMA_CC_PMU_CTL_HTREQEN        0x00000100 /* HT req enable */
 206#define  BCMA_CC_PMU_CTL_ALPREQEN       0x00000080 /* ALP req enable */
 207#define  BCMA_CC_PMU_CTL_XTALFREQ       0x0000007C /* Crystal freq */
 208#define  BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
 209#define  BCMA_CC_PMU_CTL_ILPDIVEN       0x00000002 /* ILP div enable */
 210#define  BCMA_CC_PMU_CTL_LPOSEL         0x00000001 /* LPO sel */
 211#define BCMA_CC_PMU_CAP                 0x0604 /* PMU capabilities */
 212#define  BCMA_CC_PMU_CAP_REVISION       0x000000FF /* Revision mask */
 213#define BCMA_CC_PMU_STAT                0x0608 /* PMU status */
 214#define  BCMA_CC_PMU_STAT_INTPEND       0x00000040 /* Interrupt pending */
 215#define  BCMA_CC_PMU_STAT_SBCLKST       0x00000030 /* Backplane clock status? */
 216#define  BCMA_CC_PMU_STAT_HAVEALP       0x00000008 /* ALP available */
 217#define  BCMA_CC_PMU_STAT_HAVEHT        0x00000004 /* HT available */
 218#define  BCMA_CC_PMU_STAT_RESINIT       0x00000003 /* Res init */
 219#define BCMA_CC_PMU_RES_STAT            0x060C /* PMU res status */
 220#define BCMA_CC_PMU_RES_PEND            0x0610 /* PMU res pending */
 221#define BCMA_CC_PMU_TIMER               0x0614 /* PMU timer */
 222#define BCMA_CC_PMU_MINRES_MSK          0x0618 /* PMU min res mask */
 223#define BCMA_CC_PMU_MAXRES_MSK          0x061C /* PMU max res mask */
 224#define BCMA_CC_PMU_RES_TABSEL          0x0620 /* PMU res table sel */
 225#define BCMA_CC_PMU_RES_DEPMSK          0x0624 /* PMU res dep mask */
 226#define BCMA_CC_PMU_RES_UPDNTM          0x0628 /* PMU res updown timer */
 227#define BCMA_CC_PMU_RES_TIMER           0x062C /* PMU res timer */
 228#define BCMA_CC_PMU_CLKSTRETCH          0x0630 /* PMU clockstretch */
 229#define BCMA_CC_PMU_WATCHDOG            0x0634 /* PMU watchdog */
 230#define BCMA_CC_PMU_RES_REQTS           0x0640 /* PMU res req timer sel */
 231#define BCMA_CC_PMU_RES_REQT            0x0644 /* PMU res req timer */
 232#define BCMA_CC_PMU_RES_REQM            0x0648 /* PMU res req mask */
 233#define BCMA_CC_CHIPCTL_ADDR            0x0650
 234#define BCMA_CC_CHIPCTL_DATA            0x0654
 235#define BCMA_CC_REGCTL_ADDR             0x0658
 236#define BCMA_CC_REGCTL_DATA             0x065C
 237#define BCMA_CC_PLLCTL_ADDR             0x0660
 238#define BCMA_CC_PLLCTL_DATA             0x0664
 239#define BCMA_CC_SPROM                   0x0800 /* SPROM beginning */
 240#define BCMA_CC_SPROM_PCIE6             0x0830 /* SPROM beginning on PCIe rev >= 6 */
 241
 242/* Data for the PMU, if available.
 243 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
 244 */
 245struct bcma_chipcommon_pmu {
 246        u8 rev;                 /* PMU revision */
 247        u32 crystalfreq;        /* The active crystal frequency (in kHz) */
 248};
 249
 250struct bcma_drv_cc {
 251        struct bcma_device *core;
 252        u32 status;
 253        u32 capabilities;
 254        u32 capabilities_ext;
 255        /* Fast Powerup Delay constant */
 256        u16 fast_pwrup_delay;
 257        struct bcma_chipcommon_pmu pmu;
 258};
 259
 260/* Register access */
 261#define bcma_cc_read32(cc, offset) \
 262        bcma_read32((cc)->core, offset)
 263#define bcma_cc_write32(cc, offset, val) \
 264        bcma_write32((cc)->core, offset, val)
 265
 266#define bcma_cc_mask32(cc, offset, mask) \
 267        bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
 268#define bcma_cc_set32(cc, offset, set) \
 269        bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
 270#define bcma_cc_maskset32(cc, offset, mask, set) \
 271        bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
 272
 273extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
 274
 275extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
 276extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
 277
 278extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
 279                                          u32 ticks);
 280
 281void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
 282
 283u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
 284
 285/* Chipcommon GPIO pin access. */
 286u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
 287u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
 288u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
 289u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
 290u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
 291u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
 292
 293/* PMU support */
 294extern void bcma_pmu_init(struct bcma_drv_cc *cc);
 295
 296#endif /* LINUX_BCMA_DRIVER_CC_H_ */
 297