LXR linux/include/linux/mtd/nand.h

   1/*
   2 *  linux/include/linux/mtd/nand.h
   3 *
   4 *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5 *                        Steven J. Hill <sjhill@realitydiluted.com>
   6 *                        Thomas Gleixner <tglx@linutronix.de>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * Info:
  13 *      Contains standard defines and IDs for NAND flash devices
  14 *
  15 * Changelog:
  16 *      See git changelog.
  17 */
  18#ifndef __LINUX_MTD_NAND_H
  19#define __LINUX_MTD_NAND_H
  20
  21#include <linux/wait.h>
  22#include <linux/spinlock.h>
  23#include <linux/mtd/mtd.h>
  24#include <linux/mtd/flashchip.h>
  25#include <linux/mtd/bbm.h>
  26
  27struct mtd_info;
  28struct nand_flash_dev;
  29/* Scan and identify a NAND device */
  30extern int nand_scan(struct mtd_info *mtd, int max_chips);
  31/*
  32 * Separate phases of nand_scan(), allowing board driver to intervene
  33 * and override command or ECC setup according to flash type.
  34 */
  35extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  36                           struct nand_flash_dev *table);
  37extern int nand_scan_tail(struct mtd_info *mtd);
  38
  39/* Free resources held by the NAND device */
  40extern void nand_release(struct mtd_info *mtd);
  41
  42/* Internal helper for board drivers which need to override command function */
  43extern void nand_wait_ready(struct mtd_info *mtd);
  44
  45/* locks all blockes present in the device */
  46extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  47
  48/* unlocks specified locked blockes */
  49extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  50
  51/* The maximum number of NAND chips in an array */
  52#define NAND_MAX_CHIPS          8
  53
  54/*
  55 * This constant declares the max. oobsize / page, which
  56 * is supported now. If you add a chip with bigger oobsize/page
  57 * adjust this accordingly.
  58 */
  59#define NAND_MAX_OOBSIZE        576
  60#define NAND_MAX_PAGESIZE       8192
  61
  62/*
  63 * Constants for hardware specific CLE/ALE/NCE function
  64 *
  65 * These are bits which can be or'ed to set/clear multiple
  66 * bits in one go.
  67 */
  68/* Select the chip by setting nCE to low */
  69#define NAND_NCE                0x01
  70/* Select the command latch by setting CLE to high */
  71#define NAND_CLE                0x02
  72/* Select the address latch by setting ALE to high */
  73#define NAND_ALE                0x04
  74
  75#define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  76#define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  77#define NAND_CTRL_CHANGE        0x80
  78
  79/*
  80 * Standard NAND flash commands
  81 */
  82#define NAND_CMD_READ0          0
  83#define NAND_CMD_READ1          1
  84#define NAND_CMD_RNDOUT         5
  85#define NAND_CMD_PAGEPROG       0x10
  86#define NAND_CMD_READOOB        0x50
  87#define NAND_CMD_ERASE1         0x60
  88#define NAND_CMD_STATUS         0x70
  89#define NAND_CMD_STATUS_MULTI   0x71
  90#define NAND_CMD_SEQIN          0x80
  91#define NAND_CMD_RNDIN          0x85
  92#define NAND_CMD_READID         0x90
  93#define NAND_CMD_ERASE2         0xd0
  94#define NAND_CMD_PARAM          0xec
  95#define NAND_CMD_RESET          0xff
  96
  97#define NAND_CMD_LOCK           0x2a
  98#define NAND_CMD_UNLOCK1        0x23
  99#define NAND_CMD_UNLOCK2        0x24
 100
 101/* Extended commands for large page devices */
 102#define NAND_CMD_READSTART      0x30
 103#define NAND_CMD_RNDOUTSTART    0xE0
 104#define NAND_CMD_CACHEDPROG     0x15
 105
 106/* Extended commands for AG-AND device */
 107/*
 108 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 109 *       there is no way to distinguish that from NAND_CMD_READ0
 110 *       until the remaining sequence of commands has been completed
 111 *       so add a high order bit and mask it off in the command.
 112 */
 113#define NAND_CMD_DEPLETE1       0x100
 114#define NAND_CMD_DEPLETE2       0x38
 115#define NAND_CMD_STATUS_MULTI   0x71
 116#define NAND_CMD_STATUS_ERROR   0x72
 117/* multi-bank error status (banks 0-3) */
 118#define NAND_CMD_STATUS_ERROR0  0x73
 119#define NAND_CMD_STATUS_ERROR1  0x74
 120#define NAND_CMD_STATUS_ERROR2  0x75
 121#define NAND_CMD_STATUS_ERROR3  0x76
 122#define NAND_CMD_STATUS_RESET   0x7f
 123#define NAND_CMD_STATUS_CLEAR   0xff
 124
 125#define NAND_CMD_NONE           -1
 126
 127/* Status bits */
 128#define NAND_STATUS_FAIL        0x01
 129#define NAND_STATUS_FAIL_N1     0x02
 130#define NAND_STATUS_TRUE_READY  0x20
 131#define NAND_STATUS_READY       0x40
 132#define NAND_STATUS_WP          0x80
 133
 134/*
 135 * Constants for ECC_MODES
 136 */
 137typedef enum {
 138        NAND_ECC_NONE,
 139        NAND_ECC_SOFT,
 140        NAND_ECC_HW,
 141        NAND_ECC_HW_SYNDROME,
 142        NAND_ECC_HW_OOB_FIRST,
 143        NAND_ECC_SOFT_BCH,
 144} nand_ecc_modes_t;
 145
 146/*
 147 * Constants for Hardware ECC
 148 */
 149/* Reset Hardware ECC for read */
 150#define NAND_ECC_READ           0
 151/* Reset Hardware ECC for write */
 152#define NAND_ECC_WRITE          1
 153/* Enable Hardware ECC before syndrom is read back from flash */
 154#define NAND_ECC_READSYN        2
 155
 156/* Bit mask for flags passed to do_nand_read_ecc */
 157#define NAND_GET_DEVICE         0x80
 158
 159
 160/*
 161 * Option constants for bizarre disfunctionality and real
 162 * features.
 163 */
 164/* Chip can not auto increment pages */
 165#define NAND_NO_AUTOINCR        0x00000001
 166/* Buswitdh is 16 bit */
 167#define NAND_BUSWIDTH_16        0x00000002
 168/* Device supports partial programming without padding */
 169#define NAND_NO_PADDING         0x00000004
 170/* Chip has cache program function */
 171#define NAND_CACHEPRG           0x00000008
 172/* Chip has copy back function */
 173#define NAND_COPYBACK           0x00000010
 174/*
 175 * AND Chip which has 4 banks and a confusing page / block
 176 * assignment. See Renesas datasheet for further information.
 177 */
 178#define NAND_IS_AND             0x00000020
 179/*
 180 * Chip has a array of 4 pages which can be read without
 181 * additional ready /busy waits.
 182 */
 183#define NAND_4PAGE_ARRAY        0x00000040
 184/*
 185 * Chip requires that BBT is periodically rewritten to prevent
 186 * bits from adjacent blocks from 'leaking' in altering data.
 187 * This happens with the Renesas AG-AND chips, possibly others.
 188 */
 189#define BBT_AUTO_REFRESH        0x00000080
 190/*
 191 * Chip does not require ready check on read. True
 192 * for all large page devices, as they do not support
 193 * autoincrement.
 194 */
 195#define NAND_NO_READRDY         0x00000100
 196/* Chip does not allow subpage writes */
 197#define NAND_NO_SUBPAGE_WRITE   0x00000200
 198
 199/* Device is one of 'new' xD cards that expose fake nand command set */
 200#define NAND_BROKEN_XD          0x00000400
 201
 202/* Device behaves just like nand, but is readonly */
 203#define NAND_ROM                0x00000800
 204
 205/* Options valid for Samsung large page devices */
 206#define NAND_SAMSUNG_LP_OPTIONS \
 207        (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 208
 209/* Macros to identify the above */
 210#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 211#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 212#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 213#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 214/* Large page NAND with SOFT_ECC should support subpage reads */
 215#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
 216                                        && (chip->page_shift > 9))
 217
 218/* Mask to zero out the chip options, which come from the id table */
 219#define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 220
 221/* Non chip related options */
 222/*
 223 * Use a flash based bad block table. OOB identifier is saved in OOB area.
 224 * This option is passed to the default bad block table function.
 225 */
 226#define NAND_USE_FLASH_BBT      0x00010000
 227/* This option skips the bbt scan during initialization. */
 228#define NAND_SKIP_BBTSCAN       0x00020000
 229/*
 230 * This option is defined if the board driver allocates its own buffers
 231 * (e.g. because it needs them DMA-coherent).
 232 */
 233#define NAND_OWN_BUFFERS        0x00040000
 234/* Chip may not exist, so silence any errors in scan */
 235#define NAND_SCAN_SILENT_NODEV  0x00080000
 236/*
 237 * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
 238 * the OOB area.
 239 */
 240#define NAND_USE_FLASH_BBT_NO_OOB       0x00800000
 241/* Create an empty BBT with no vendor information if the BBT is available */
 242#define NAND_CREATE_EMPTY_BBT           0x01000000
 243
 244/* Options set by nand scan */
 245/* Nand scan has allocated controller struct */
 246#define NAND_CONTROLLER_ALLOC   0x80000000
 247
 248/* Cell info constants */
 249#define NAND_CI_CHIPNR_MSK      0x03
 250#define NAND_CI_CELLTYPE_MSK    0x0C
 251
 252/* Keep gcc happy */
 253struct nand_chip;
 254
 255struct nand_onfi_params {
 256        /* rev info and features block */
 257        /* 'O' 'N' 'F' 'I'  */
 258        u8 sig[4];
 259        __le16 revision;
 260        __le16 features;
 261        __le16 opt_cmd;
 262        u8 reserved[22];
 263
 264        /* manufacturer information block */
 265        char manufacturer[12];
 266        char model[20];
 267        u8 jedec_id;
 268        __le16 date_code;
 269        u8 reserved2[13];
 270
 271        /* memory organization block */
 272        __le32 byte_per_page;
 273        __le16 spare_bytes_per_page;
 274        __le32 data_bytes_per_ppage;
 275        __le16 spare_bytes_per_ppage;
 276        __le32 pages_per_block;
 277        __le32 blocks_per_lun;
 278        u8 lun_count;
 279        u8 addr_cycles;
 280        u8 bits_per_cell;
 281        __le16 bb_per_lun;
 282        __le16 block_endurance;
 283        u8 guaranteed_good_blocks;
 284        __le16 guaranteed_block_endurance;
 285        u8 programs_per_page;
 286        u8 ppage_attr;
 287        u8 ecc_bits;
 288        u8 interleaved_bits;
 289        u8 interleaved_ops;
 290        u8 reserved3[13];
 291
 292        /* electrical parameter block */
 293        u8 io_pin_capacitance_max;
 294        __le16 async_timing_mode;
 295        __le16 program_cache_timing_mode;
 296        __le16 t_prog;
 297        __le16 t_bers;
 298        __le16 t_r;
 299        __le16 t_ccs;
 300        __le16 src_sync_timing_mode;
 301        __le16 src_ssync_features;
 302        __le16 clk_pin_capacitance_typ;
 303        __le16 io_pin_capacitance_typ;
 304        __le16 input_pin_capacitance_typ;
 305        u8 input_pin_capacitance_max;
 306        u8 driver_strenght_support;
 307        __le16 t_int_r;
 308        __le16 t_ald;
 309        u8 reserved4[7];
 310
 311        /* vendor */
 312        u8 reserved5[90];
 313
 314        __le16 crc;
 315} __attribute__((packed));
 316
 317#define ONFI_CRC_BASE   0x4F4E
 318
 319/**
 320 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 321 * @lock:               protection lock
 322 * @active:             the mtd device which holds the controller currently
 323 * @wq:                 wait queue to sleep on if a NAND operation is in
 324 *                      progress used instead of the per chip wait queue
 325 *                      when a hw controller is available.
 326 */
 327struct nand_hw_control {
 328        spinlock_t lock;
 329        struct nand_chip *active;
 330        wait_queue_head_t wq;
 331};
 332
 333/**
 334 * struct nand_ecc_ctrl - Control structure for ecc
 335 * @mode:       ecc mode
 336 * @steps:      number of ecc steps per page
 337 * @size:       data bytes per ecc step
 338 * @bytes:      ecc bytes per step
 339 * @total:      total number of ecc bytes per page
 340 * @prepad:     padding information for syndrome based ecc generators
 341 * @postpad:    padding information for syndrome based ecc generators
 342 * @layout:     ECC layout control struct pointer
 343 * @priv:       pointer to private ecc control data
 344 * @hwctl:      function to control hardware ecc generator. Must only
 345 *              be provided if an hardware ECC is available
 346 * @calculate:  function for ecc calculation or readback from ecc hardware
 347 * @correct:    function for ecc correction, matching to ecc generator (sw/hw)
 348 * @read_page_raw:      function to read a raw page without ECC
 349 * @write_page_raw:     function to write a raw page without ECC
 350 * @read_page:  function to read a page according to the ecc generator
 351 *              requirements.
 352 * @read_subpage:       function to read parts of the page covered by ECC.
 353 * @write_page: function to write a page according to the ecc generator
 354 *              requirements.
 355 * @read_oob:   function to read chip OOB data
 356 * @write_oob:  function to write chip OOB data
 357 */
 358struct nand_ecc_ctrl {
 359        nand_ecc_modes_t mode;
 360        int steps;
 361        int size;
 362        int bytes;
 363        int total;
 364        int prepad;
 365        int postpad;
 366        struct nand_ecclayout   *layout;
 367        void *priv;
 368        void (*hwctl)(struct mtd_info *mtd, int mode);
 369        int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 370                        uint8_t *ecc_code);
 371        int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 372                        uint8_t *calc_ecc);
 373        int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 374                        uint8_t *buf, int page);
 375        void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 376                        const uint8_t *buf);
 377        int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 378                        uint8_t *buf, int page);
 379        int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 380                        uint32_t offs, uint32_t len, uint8_t *buf);
 381        void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 382                        const uint8_t *buf);
 383        int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
 384                        int sndcmd);
 385        int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 386                        int page);
 387};
 388
 389/**
 390 * struct nand_buffers - buffer structure for read/write
 391 * @ecccalc:    buffer for calculated ecc
 392 * @ecccode:    buffer for ecc read from flash
 393 * @databuf:    buffer for data - dynamically sized
 394 *
 395 * Do not change the order of buffers. databuf and oobrbuf must be in
 396 * consecutive order.
 397 */
 398struct nand_buffers {
 399        uint8_t ecccalc[NAND_MAX_OOBSIZE];
 400        uint8_t ecccode[NAND_MAX_OOBSIZE];
 401        uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 402};
 403
 404/**
 405 * struct nand_chip - NAND Private Flash Chip Data
 406 * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 407 *                      flash device
 408 * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 409 *                      flash device.
 410 * @read_byte:          [REPLACEABLE] read one byte from the chip
 411 * @read_word:          [REPLACEABLE] read one word from the chip
 412 * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 413 * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 414 * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip
 415 *                      data.
 416 * @select_chip:        [REPLACEABLE] select chip nr
 417 * @block_bad:          [REPLACEABLE] check, if the block is bad
 418 * @block_markbad:      [REPLACEABLE] mark the block bad
 419 * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 420 *                      ALE/CLE/nCE. Also used to write command and address
 421 * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 422 *                      mtd->oobsize, mtd->writesize and so on.
 423 *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 424 *                      Return with the bus width.
 425 * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing
 426 *                      device ready/busy line. If set to NULL no access to
 427 *                      ready/busy is available and the ready/busy information
 428 *                      is read from the chip status register.
 429 * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 430 *                      commands to the chip.
 431 * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 432 *                      ready.
 433 * @ecc:                [BOARDSPECIFIC] ecc control ctructure
 434 * @buffers:            buffer structure for read/write
 435 * @hwcontrol:          platform-specific hardware control structure
 436 * @ops:                oob operation operands
 437 * @erase_cmd:          [INTERN] erase command write function, selectable due
 438 *                      to AND support.
 439 * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 440 * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 441 *                      data from array to read regs (tR).
 442 * @state:              [INTERN] the current state of the NAND device
 443 * @oob_poi:            poison value buffer
 444 * @page_shift:         [INTERN] number of address bits in a page (column
 445 *                      address bits).
 446 * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 447 * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 448 * @chip_shift:         [INTERN] number of address bits in one chip
 449 * @options:            [BOARDSPECIFIC] various chip options. They can partly
 450 *                      be set to inform nand_scan about special functionality.
 451 *                      See the defines for further explanation.
 452 * @badblockpos:        [INTERN] position of the bad block marker in the oob
 453 *                      area.
 454 * @badblockbits:       [INTERN] number of bits to left-shift the bad block
 455 *                      number
 456 * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 457 * @numchips:           [INTERN] number of physical chips
 458 * @chipsize:           [INTERN] the size of one chip for multichip arrays
 459 * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 460 * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 461 *                      data_buf.
 462 * @subpagesize:        [INTERN] holds the subpagesize
 463 * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 464 *                      non 0 if ONFI supported.
 465 * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 466 *                      supported, 0 otherwise.
 467 * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
 468 * @bbt:                [INTERN] bad block table pointer
 469 * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 470 *                      lookup.
 471 * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 472 * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 473 *                      bad block scan.
 474 * @controller:         [REPLACEABLE] a pointer to a hardware controller
 475 *                      structure which is shared among multiple independend
 476 *                      devices.
 477 * @priv:               [OPTIONAL] pointer to private chip date
 478 * @errstat:            [OPTIONAL] hardware specific function to perform
 479 *                      additional error status checks (determine if errors are
 480 *                      correctable).
 481 * @write_page:         [REPLACEABLE] High-level page write function
 482 */
 483
 484struct nand_chip {
 485        void __iomem *IO_ADDR_R;
 486        void __iomem *IO_ADDR_W;
 487
 488        uint8_t (*read_byte)(struct mtd_info *mtd);
 489        u16 (*read_word)(struct mtd_info *mtd);
 490        void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 491        void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 492        int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 493        void (*select_chip)(struct mtd_info *mtd, int chip);
 494        int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 495        int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 496        void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 497        int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 498                        u8 *id_data);
 499        int (*dev_ready)(struct mtd_info *mtd);
 500        void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 501                        int page_addr);
 502        int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 503        void (*erase_cmd)(struct mtd_info *mtd, int page);
 504        int (*scan_bbt)(struct mtd_info *mtd);
 505        int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 506                        int status, int page);
 507        int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 508                        const uint8_t *buf, int page, int cached, int raw);
 509
 510        int chip_delay;
 511        unsigned int options;
 512
 513        int page_shift;
 514        int phys_erase_shift;
 515        int bbt_erase_shift;
 516        int chip_shift;
 517        int numchips;
 518        uint64_t chipsize;
 519        int pagemask;
 520        int pagebuf;
 521        int subpagesize;
 522        uint8_t cellinfo;
 523        int badblockpos;
 524        int badblockbits;
 525
 526        int onfi_version;
 527        struct nand_onfi_params onfi_params;
 528
 529        flstate_t state;
 530
 531        uint8_t *oob_poi;
 532        struct nand_hw_control *controller;
 533        struct nand_ecclayout *ecclayout;
 534
 535        struct nand_ecc_ctrl ecc;
 536        struct nand_buffers *buffers;
 537        struct nand_hw_control hwcontrol;
 538
 539        struct mtd_oob_ops ops;
 540
 541        uint8_t *bbt;
 542        struct nand_bbt_descr *bbt_td;
 543        struct nand_bbt_descr *bbt_md;
 544
 545        struct nand_bbt_descr *badblock_pattern;
 546
 547        void *priv;
 548};
 549
 550/*
 551 * NAND Flash Manufacturer ID Codes
 552 */
 553#define NAND_MFR_TOSHIBA        0x98
 554#define NAND_MFR_SAMSUNG        0xec
 555#define NAND_MFR_FUJITSU        0x04
 556#define NAND_MFR_NATIONAL       0x8f
 557#define NAND_MFR_RENESAS        0x07
 558#define NAND_MFR_STMICRO        0x20
 559#define NAND_MFR_HYNIX          0xad
 560#define NAND_MFR_MICRON         0x2c
 561#define NAND_MFR_AMD            0x01
 562
 563/**
 564 * struct nand_flash_dev - NAND Flash Device ID Structure
 565 * @name:       Identify the device type
 566 * @id:         device ID code
 567 * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 568 *              If the pagesize is 0, then the real pagesize
 569 *              and the eraseize are determined from the
 570 *              extended id bytes in the chip
 571 * @erasesize:  Size of an erase block in the flash device.
 572 * @chipsize:   Total chipsize in Mega Bytes
 573 * @options:    Bitfield to store chip relevant options
 574 */
 575struct nand_flash_dev {
 576        char *name;
 577        int id;
 578        unsigned long pagesize;
 579        unsigned long chipsize;
 580        unsigned long erasesize;
 581        unsigned long options;
 582};
 583
 584/**
 585 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 586 * @name:       Manufacturer name
 587 * @id:         manufacturer ID code of device.
 588*/
 589struct nand_manufacturers {
 590        int id;
 591        char *name;
 592};
 593
 594extern struct nand_flash_dev nand_flash_ids[];
 595extern struct nand_manufacturers nand_manuf_ids[];
 596
 597extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 598extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 599extern int nand_default_bbt(struct mtd_info *mtd);
 600extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 601extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 602                           int allowbbt);
 603extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 604                        size_t *retlen, uint8_t *buf);
 605
 606/**
 607 * struct platform_nand_chip - chip level device structure
 608 * @nr_chips:           max. number of chips to scan for
 609 * @chip_offset:        chip number offset
 610 * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 611 * @partitions:         mtd partition list
 612 * @chip_delay:         R/B delay value in us
 613 * @options:            Option flags, e.g. 16bit buswidth
 614 * @ecclayout:          ecc layout info structure
 615 * @part_probe_types:   NULL-terminated array of probe types
 616 * @set_parts:          platform specific function to set partitions
 617 * @priv:               hardware controller specific settings
 618 */
 619struct platform_nand_chip {
 620        int nr_chips;
 621        int chip_offset;
 622        int nr_partitions;
 623        struct mtd_partition *partitions;
 624        struct nand_ecclayout *ecclayout;
 625        int chip_delay;
 626        unsigned int options;
 627        const char **part_probe_types;
 628        void (*set_parts)(uint64_t size, struct platform_nand_chip *chip);
 629        void *priv;
 630};
 631
 632/* Keep gcc happy */
 633struct platform_device;
 634
 635/**
 636 * struct platform_nand_ctrl - controller level device structure
 637 * @probe:              platform specific function to probe/setup hardware
 638 * @remove:             platform specific function to remove/teardown hardware
 639 * @hwcontrol:          platform specific hardware control structure
 640 * @dev_ready:          platform specific function to read ready/busy pin
 641 * @select_chip:        platform specific chip select function
 642 * @cmd_ctrl:           platform specific function for controlling
 643 *                      ALE/CLE/nCE. Also used to write command and address
 644 * @write_buf:          platform specific function for write buffer
 645 * @read_buf:           platform specific function for read buffer
 646 * @priv:               private data to transport driver specific settings
 647 *
 648 * All fields are optional and depend on the hardware driver requirements
 649 */
 650struct platform_nand_ctrl {
 651        int (*probe)(struct platform_device *pdev);
 652        void (*remove)(struct platform_device *pdev);
 653        void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 654        int (*dev_ready)(struct mtd_info *mtd);
 655        void (*select_chip)(struct mtd_info *mtd, int chip);
 656        void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 657        void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 658        void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 659        void *priv;
 660};
 661
 662/**
 663 * struct platform_nand_data - container structure for platform-specific data
 664 * @chip:               chip level chip structure
 665 * @ctrl:               controller level device structure
 666 */
 667struct platform_nand_data {
 668        struct platform_nand_chip chip;
 669        struct platform_nand_ctrl ctrl;
 670};
 671
 672/* Some helpers to access the data structures */
 673static inline
 674struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 675{
 676        struct nand_chip *chip = mtd->priv;
 677
 678        return chip->priv;
 679}
 680
 681#endif /* __LINUX_MTD_NAND_H */
 682