LXR linux/include/linux/mtd/sh

   1/*
   2 * SuperH FLCTL nand controller
   3 *
   4 * Copyright © 2008 Renesas Solutions Corp.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18 */
  19
  20#ifndef __SH_FLCTL_H__
  21#define __SH_FLCTL_H__
  22
  23#include <linux/mtd/mtd.h>
  24#include <linux/mtd/nand.h>
  25#include <linux/mtd/partitions.h>
  26
  27/* FLCTL registers */
  28#define FLCMNCR(f)              (f->reg + 0x0)
  29#define FLCMDCR(f)              (f->reg + 0x4)
  30#define FLCMCDR(f)              (f->reg + 0x8)
  31#define FLADR(f)                (f->reg + 0xC)
  32#define FLADR2(f)               (f->reg + 0x3C)
  33#define FLDATAR(f)              (f->reg + 0x10)
  34#define FLDTCNTR(f)             (f->reg + 0x14)
  35#define FLINTDMACR(f)           (f->reg + 0x18)
  36#define FLBSYTMR(f)             (f->reg + 0x1C)
  37#define FLBSYCNT(f)             (f->reg + 0x20)
  38#define FLDTFIFO(f)             (f->reg + 0x24)
  39#define FLECFIFO(f)             (f->reg + 0x28)
  40#define FLTRCR(f)               (f->reg + 0x2C)
  41#define FL4ECCRESULT0(f)        (f->reg + 0x80)
  42#define FL4ECCRESULT1(f)        (f->reg + 0x84)
  43#define FL4ECCRESULT2(f)        (f->reg + 0x88)
  44#define FL4ECCRESULT3(f)        (f->reg + 0x8C)
  45#define FL4ECCCR(f)             (f->reg + 0x90)
  46#define FL4ECCCNT(f)            (f->reg + 0x94)
  47#define FLERRADR(f)             (f->reg + 0x98)
  48
  49/* FLCMNCR control bits */
  50#define ECCPOS2         (0x1 << 25)
  51#define _4ECCCNTEN      (0x1 << 24)
  52#define _4ECCEN         (0x1 << 23)
  53#define _4ECCCORRECT    (0x1 << 22)
  54#define SHBUSSEL        (0x1 << 20)
  55#define SEL_16BIT       (0x1 << 19)
  56#define SNAND_E         (0x1 << 18)     /* SNAND (0=512 1=2048)*/
  57#define QTSEL_E         (0x1 << 17)
  58#define ENDIAN          (0x1 << 16)     /* 1 = little endian */
  59#define FCKSEL_E        (0x1 << 15)
  60#define ECCPOS_00       (0x00 << 12)
  61#define ECCPOS_01       (0x01 << 12)
  62#define ECCPOS_02       (0x02 << 12)
  63#define ACM_SACCES_MODE (0x01 << 10)
  64#define NANWF_E         (0x1 << 9)
  65#define SE_D            (0x1 << 8)      /* Spare area disable */
  66#define CE1_ENABLE      (0x1 << 4)      /* Chip Enable 1 */
  67#define CE0_ENABLE      (0x1 << 3)      /* Chip Enable 0 */
  68#define TYPESEL_SET     (0x1 << 0)
  69
  70/* FLCMDCR control bits */
  71#define ADRCNT2_E       (0x1 << 31)     /* 5byte address enable */
  72#define ADRMD_E         (0x1 << 26)     /* Sector address access */
  73#define CDSRC_E         (0x1 << 25)     /* Data buffer selection */
  74#define DOSR_E          (0x1 << 24)     /* Status read check */
  75#define SELRW           (0x1 << 21)     /*  0:read 1:write */
  76#define DOADR_E         (0x1 << 20)     /* Address stage execute */
  77#define ADRCNT_1        (0x00 << 18)    /* Address data bytes: 1byte */
  78#define ADRCNT_2        (0x01 << 18)    /* Address data bytes: 2byte */
  79#define ADRCNT_3        (0x02 << 18)    /* Address data bytes: 3byte */
  80#define ADRCNT_4        (0x03 << 18)    /* Address data bytes: 4byte */
  81#define DOCMD2_E        (0x1 << 17)     /* 2nd cmd stage execute */
  82#define DOCMD1_E        (0x1 << 16)     /* 1st cmd stage execute */
  83
  84/* FLTRCR control bits */
  85#define TRSTRT          (0x1 << 0)      /* translation start */
  86#define TREND           (0x1 << 1)      /* translation end */
  87
  88/* FL4ECCCR control bits */
  89#define _4ECCFA         (0x1 << 2)      /* 4 symbols correct fault */
  90#define _4ECCEND        (0x1 << 1)      /* 4 symbols end */
  91#define _4ECCEXST       (0x1 << 0)      /* 4 symbols exist */
  92
  93#define INIT_FL4ECCRESULT_VAL   0x03FF03FF
  94#define LOOP_TIMEOUT_MAX        0x00010000
  95
  96struct sh_flctl {
  97        struct mtd_info         mtd;
  98        struct nand_chip        chip;
  99        struct platform_device  *pdev;
 100        void __iomem            *reg;
 101
 102        uint8_t done_buff[2048 + 64];   /* max size 2048 + 64 */
 103        int     read_bytes;
 104        int     index;
 105        int     seqin_column;           /* column in SEQIN cmd */
 106        int     seqin_page_addr;        /* page_addr in SEQIN cmd */
 107        uint32_t seqin_read_cmd;                /* read cmd in SEQIN cmd */
 108        int     erase1_page_addr;       /* page_addr in ERASE1 cmd */
 109        uint32_t erase_ADRCNT;          /* bits of FLCMDCR in ERASE1 cmd */
 110        uint32_t rw_ADRCNT;     /* bits of FLCMDCR in READ WRITE cmd */
 111
 112        int     hwecc_cant_correct[4];
 113
 114        unsigned page_size:1;   /* NAND page size (0 = 512, 1 = 2048) */
 115        unsigned hwecc:1;       /* Hardware ECC (0 = disabled, 1 = enabled) */
 116};
 117
 118struct sh_flctl_platform_data {
 119        struct mtd_partition    *parts;
 120        int                     nr_parts;
 121        unsigned long           flcmncr_val;
 122
 123        unsigned has_hwecc:1;
 124};
 125
 126static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
 127{
 128        return container_of(mtdinfo, struct sh_flctl, mtd);
 129}
 130
 131#endif  /* __SH_FLCTL_H__ */
 132