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28#ifndef _PCI_HOTPLUG_H
29#define _PCI_HOTPLUG_H
30
31
32enum pcie_link_width {
33 PCIE_LNK_WIDTH_RESRV = 0x00,
34 PCIE_LNK_X1 = 0x01,
35 PCIE_LNK_X2 = 0x02,
36 PCIE_LNK_X4 = 0x04,
37 PCIE_LNK_X8 = 0x08,
38 PCIE_LNK_X12 = 0x0C,
39 PCIE_LNK_X16 = 0x10,
40 PCIE_LNK_X32 = 0x20,
41 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
42};
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72struct hotplug_slot_ops {
73 struct module *owner;
74 const char *mod_name;
75 int (*enable_slot) (struct hotplug_slot *slot);
76 int (*disable_slot) (struct hotplug_slot *slot);
77 int (*set_attention_status) (struct hotplug_slot *slot, u8 value);
78 int (*hardware_test) (struct hotplug_slot *slot, u32 value);
79 int (*get_power_status) (struct hotplug_slot *slot, u8 *value);
80 int (*get_attention_status) (struct hotplug_slot *slot, u8 *value);
81 int (*get_latch_status) (struct hotplug_slot *slot, u8 *value);
82 int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value);
83};
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93
94struct hotplug_slot_info {
95 u8 power_status;
96 u8 attention_status;
97 u8 latch_status;
98 u8 adapter_status;
99};
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110
111struct hotplug_slot {
112 struct hotplug_slot_ops *ops;
113 struct hotplug_slot_info *info;
114 void (*release) (struct hotplug_slot *slot);
115 void *private;
116
117
118 struct list_head slot_list;
119 struct pci_slot *pci_slot;
120};
121#define to_hotplug_slot(n) container_of(n, struct hotplug_slot, kobj)
122
123static inline const char *hotplug_slot_name(const struct hotplug_slot *slot)
124{
125 return pci_slot_name(slot->pci_slot);
126}
127
128extern int __pci_hp_register(struct hotplug_slot *slot, struct pci_bus *pbus,
129 int nr, const char *name,
130 struct module *owner, const char *mod_name);
131extern int pci_hp_deregister(struct hotplug_slot *slot);
132extern int __must_check pci_hp_change_slot_info (struct hotplug_slot *slot,
133 struct hotplug_slot_info *info);
134
135static inline int pci_hp_register(struct hotplug_slot *slot,
136 struct pci_bus *pbus,
137 int devnr, const char *name)
138{
139 return __pci_hp_register(slot, pbus, devnr, name,
140 THIS_MODULE, KBUILD_MODNAME);
141}
142
143
144struct hpp_type0 {
145 u32 revision;
146 u8 cache_line_size;
147 u8 latency_timer;
148 u8 enable_serr;
149 u8 enable_perr;
150};
151
152
153struct hpp_type1 {
154 u32 revision;
155 u8 max_mem_read;
156 u8 avg_max_split;
157 u16 tot_max_split;
158};
159
160
161struct hpp_type2 {
162 u32 revision;
163 u32 unc_err_mask_and;
164 u32 unc_err_mask_or;
165 u32 unc_err_sever_and;
166 u32 unc_err_sever_or;
167 u32 cor_err_mask_and;
168 u32 cor_err_mask_or;
169 u32 adv_err_cap_and;
170 u32 adv_err_cap_or;
171 u16 pci_exp_devctl_and;
172 u16 pci_exp_devctl_or;
173 u16 pci_exp_lnkctl_and;
174 u16 pci_exp_lnkctl_or;
175 u32 sec_unc_err_sever_and;
176 u32 sec_unc_err_sever_or;
177 u32 sec_unc_err_mask_and;
178 u32 sec_unc_err_mask_or;
179};
180
181struct hotplug_params {
182 struct hpp_type0 *t0;
183 struct hpp_type1 *t1;
184 struct hpp_type2 *t2;
185 struct hpp_type0 type0_data;
186 struct hpp_type1 type1_data;
187 struct hpp_type2 type2_data;
188};
189
190#ifdef CONFIG_ACPI
191#include <acpi/acpi.h>
192#include <acpi/acpi_bus.h>
193int pci_get_hp_params(struct pci_dev *dev, struct hotplug_params *hpp);
194int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags);
195int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle);
196int acpi_pci_detect_ejectable(acpi_handle handle);
197#else
198static inline int pci_get_hp_params(struct pci_dev *dev,
199 struct hotplug_params *hpp)
200{
201 return -ENODEV;
202}
203#endif
204
205void pci_configure_slot(struct pci_dev *dev);
206#endif
207
208