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35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
41#include <linux/gpio.h>
42#include <linux/regulator/consumer.h>
43#include <linux/platform_device.h>
44#include <linux/slab.h>
45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
49#include <sound/initval.h>
50#include <sound/tlv.h>
51#include <sound/tlv320aic3x.h>
52
53#include "tlv320aic3x.h"
54
55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD",
58 "DVDD",
59 "AVDD",
60 "DRVDD",
61};
62
63static LIST_HEAD(reset_list);
64
65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
72
73struct aic3x_priv {
74 struct snd_soc_codec *codec;
75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
79 void *control_data;
80 unsigned int sysclk;
81 struct list_head list;
82 int master;
83 int gpio_reset;
84 int power;
85#define AIC3X_MODEL_3X 0
86#define AIC3X_MODEL_33 1
87#define AIC3X_MODEL_3007 2
88 u16 model;
89};
90
91
92
93
94
95
96
97static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
98 0x00, 0x00, 0x00, 0x10,
99 0x04, 0x00, 0x00, 0x00,
100 0x00, 0x00, 0x00, 0x01,
101 0x00, 0x00, 0x00, 0x80,
102 0x80, 0xff, 0xff, 0x78,
103 0x78, 0x78, 0x78, 0x78,
104 0x78, 0x00, 0x00, 0xfe,
105 0x00, 0x00, 0xfe, 0x00,
106 0x18, 0x18, 0x00, 0x00,
107 0x00, 0x00, 0x00, 0x00,
108 0x00, 0x00, 0x00, 0x80,
109 0x80, 0x00, 0x00, 0x00,
110 0x00, 0x00, 0x00, 0x04,
111 0x00, 0x00, 0x00, 0x00,
112 0x00, 0x00, 0x04, 0x00,
113 0x00, 0x00, 0x00, 0x00,
114 0x00, 0x04, 0x00, 0x00,
115 0x00, 0x00, 0x00, 0x00,
116 0x04, 0x00, 0x00, 0x00,
117 0x00, 0x00, 0x00, 0x00,
118 0x00, 0x00, 0x00, 0x00,
119 0x00, 0x00, 0x00, 0x00,
120 0x00, 0x00, 0x00, 0x00,
121 0x00, 0x00, 0x00, 0x00,
122 0x00, 0x00, 0x00, 0x00,
123 0x00, 0x00, 0x02,
124};
125
126
127
128
129
130
131static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
132 u8 *value)
133{
134 u8 *cache = codec->reg_cache;
135
136 if (codec->cache_only)
137 return -EINVAL;
138 if (reg >= AIC3X_CACHEREGNUM)
139 return -1;
140
141 *value = codec->hw_read(codec, reg);
142 cache[reg] = *value;
143
144 return 0;
145}
146
147#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
148{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
149 .info = snd_soc_info_volsw, \
150 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
151 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
152
153
154
155
156
157static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
158 struct snd_ctl_elem_value *ucontrol)
159{
160 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
161 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
162 struct soc_mixer_control *mc =
163 (struct soc_mixer_control *)kcontrol->private_value;
164 unsigned int reg = mc->reg;
165 unsigned int shift = mc->shift;
166 int max = mc->max;
167 unsigned int mask = (1 << fls(max)) - 1;
168 unsigned int invert = mc->invert;
169 unsigned short val, val_mask;
170 int ret;
171 struct snd_soc_dapm_path *path;
172 int found = 0;
173
174 val = (ucontrol->value.integer.value[0] & mask);
175
176 mask = 0xf;
177 if (val)
178 val = mask;
179
180 if (invert)
181 val = mask - val;
182 val_mask = mask << shift;
183 val = val << shift;
184
185 mutex_lock(&widget->codec->mutex);
186
187 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
188
189 list_for_each_entry(path, &widget->dapm->card->paths, list) {
190 if (path->kcontrol != kcontrol)
191 continue;
192
193
194 found = 1;
195 if (val)
196
197 path->connect = invert ? 0 : 1;
198 else
199
200 path->connect = invert ? 1 : 0;
201 break;
202 }
203
204 if (found)
205 snd_soc_dapm_sync(widget->dapm);
206 }
207
208 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
209
210 mutex_unlock(&widget->codec->mutex);
211 return ret;
212}
213
214static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
215static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
216static const char *aic3x_left_hpcom_mux[] =
217 { "differential of HPLOUT", "constant VCM", "single-ended" };
218static const char *aic3x_right_hpcom_mux[] =
219 { "differential of HPROUT", "constant VCM", "single-ended",
220 "differential of HPLCOM", "external feedback" };
221static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
222static const char *aic3x_adc_hpf[] =
223 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
224
225#define LDAC_ENUM 0
226#define RDAC_ENUM 1
227#define LHPCOM_ENUM 2
228#define RHPCOM_ENUM 3
229#define LINE1L_2_L_ENUM 4
230#define LINE1L_2_R_ENUM 5
231#define LINE1R_2_L_ENUM 6
232#define LINE1R_2_R_ENUM 7
233#define LINE2L_ENUM 8
234#define LINE2R_ENUM 9
235#define ADC_HPF_ENUM 10
236
237static const struct soc_enum aic3x_enum[] = {
238 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
239 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
240 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
241 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
242 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
243 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
244 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
245 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
246 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
248 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
249};
250
251
252
253
254static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
255
256static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
257
258
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260
261
262
263
264
265
266static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
267
268static const struct snd_kcontrol_new aic3x_snd_controls[] = {
269
270 SOC_DOUBLE_R_TLV("PCM Playback Volume",
271 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
272
273
274
275
276
277
278 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
279 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
280 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
281 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
283 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
284
285 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
286 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
287 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
288 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
290 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
291
292 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
293 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
294 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
295 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
297 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
298
299 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
300 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
301 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
302 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
304 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
305
306 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
307 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
308 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
309 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
310 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
311 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
312
313 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
314 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
315 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
316 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
318 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
319
320
321 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
322 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
323 0, 118, 1, output_stage_tlv),
324 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
325 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
326 0, 118, 1, output_stage_tlv),
327 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
328 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
329 0, 118, 1, output_stage_tlv),
330
331 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
332 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
333 0, 118, 1, output_stage_tlv),
334 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
335 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
336 0, 118, 1, output_stage_tlv),
337 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
338 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
339 0, 118, 1, output_stage_tlv),
340
341 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
342 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
343 0, 118, 1, output_stage_tlv),
344 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
345 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
346 0, 118, 1, output_stage_tlv),
347 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
348 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
349 0, 118, 1, output_stage_tlv),
350
351 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
352 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
353 0, 118, 1, output_stage_tlv),
354 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
355 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
356 0, 118, 1, output_stage_tlv),
357 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
358 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
359 0, 118, 1, output_stage_tlv),
360
361
362 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
363 0x01, 0),
364 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
365 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
366 0x01, 0),
367 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
368 0x01, 0),
369
370
371
372
373
374 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
375
376
377 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
378 0, 119, 0, adc_tlv),
379 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
380
381 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
382};
383
384
385
386
387static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
388
389static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
390 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
391
392
393static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
394SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
395
396
397static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
398SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
399
400
401static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
402SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
403
404
405static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
406SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
407
408
409static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
410 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
411 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
412 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
416};
417
418
419static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
420 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
426};
427
428
429static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
430 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
436};
437
438
439static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
440 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
441 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
446};
447
448
449static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
450 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
456};
457
458
459static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
460 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
466};
467
468
469static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
470 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
472 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
473 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
474 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
476};
477
478
479static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
480 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
481 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
482 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
483 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
484 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
485};
486
487
488static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
489 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
490 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
491 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
492 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
493 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
494};
495
496
497static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
498SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
499static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
500SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
501
502
503static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
504SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
505static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
506SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
507
508
509static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
510SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
511
512
513static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
514SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
515
516static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
517
518 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
519 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
520 &aic3x_left_dac_mux_controls),
521 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
522 &aic3x_left_hpcom_mux_controls),
523 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
524 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
525 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
526
527
528 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
529 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
530 &aic3x_right_dac_mux_controls),
531 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
532 &aic3x_right_hpcom_mux_controls),
533 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
534 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
535 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
536
537
538 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
539
540
541 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
542 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
543 &aic3x_left_pga_mixer_controls[0],
544 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
545 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
546 &aic3x_left_line1l_mux_controls),
547 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
548 &aic3x_left_line1r_mux_controls),
549 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
550 &aic3x_left_line2_mux_controls),
551
552
553 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
554 LINE1R_2_RADC_CTRL, 2, 0),
555 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
556 &aic3x_right_pga_mixer_controls[0],
557 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
558 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
559 &aic3x_right_line1l_mux_controls),
560 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
561 &aic3x_right_line1r_mux_controls),
562 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
563 &aic3x_right_line2_mux_controls),
564
565
566
567
568
569
570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
571 AIC3X_GPIO1_REG, 4, 0xf,
572 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
573 AIC3X_GPIO1_FUNC_DISABLED),
574
575
576
577
578
579 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
580 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
581 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
582 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
583 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
584 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
585
586
587 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
588 MICBIAS_CTRL, 6, 3, 1, 0),
589 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
590 MICBIAS_CTRL, 6, 3, 2, 0),
591 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
592 MICBIAS_CTRL, 6, 3, 3, 0),
593
594
595 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
596 &aic3x_left_line_mixer_controls[0],
597 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
598 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
599 &aic3x_right_line_mixer_controls[0],
600 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
601 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
602 &aic3x_mono_mixer_controls[0],
603 ARRAY_SIZE(aic3x_mono_mixer_controls)),
604 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
605 &aic3x_left_hp_mixer_controls[0],
606 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
607 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
608 &aic3x_right_hp_mixer_controls[0],
609 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
610 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
611 &aic3x_left_hpcom_mixer_controls[0],
612 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
613 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
614 &aic3x_right_hpcom_mixer_controls[0],
615 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
616
617 SND_SOC_DAPM_OUTPUT("LLOUT"),
618 SND_SOC_DAPM_OUTPUT("RLOUT"),
619 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
620 SND_SOC_DAPM_OUTPUT("HPLOUT"),
621 SND_SOC_DAPM_OUTPUT("HPROUT"),
622 SND_SOC_DAPM_OUTPUT("HPLCOM"),
623 SND_SOC_DAPM_OUTPUT("HPRCOM"),
624
625 SND_SOC_DAPM_INPUT("MIC3L"),
626 SND_SOC_DAPM_INPUT("MIC3R"),
627 SND_SOC_DAPM_INPUT("LINE1L"),
628 SND_SOC_DAPM_INPUT("LINE1R"),
629 SND_SOC_DAPM_INPUT("LINE2L"),
630 SND_SOC_DAPM_INPUT("LINE2R"),
631
632
633
634
635
636
637
638 SND_SOC_DAPM_OUTPUT("Detection"),
639};
640
641static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
642
643 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
644 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
645
646 SND_SOC_DAPM_OUTPUT("SPOP"),
647 SND_SOC_DAPM_OUTPUT("SPOM"),
648};
649
650static const struct snd_soc_dapm_route intercon[] = {
651
652 {"Left Line1L Mux", "single-ended", "LINE1L"},
653 {"Left Line1L Mux", "differential", "LINE1L"},
654
655 {"Left Line2L Mux", "single-ended", "LINE2L"},
656 {"Left Line2L Mux", "differential", "LINE2L"},
657
658 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
659 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
660 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
661 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
662 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
663
664 {"Left ADC", NULL, "Left PGA Mixer"},
665 {"Left ADC", NULL, "GPIO1 dmic modclk"},
666
667
668 {"Right Line1R Mux", "single-ended", "LINE1R"},
669 {"Right Line1R Mux", "differential", "LINE1R"},
670
671 {"Right Line2R Mux", "single-ended", "LINE2R"},
672 {"Right Line2R Mux", "differential", "LINE2R"},
673
674 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
675 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
676 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
677 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
678 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
679
680 {"Right ADC", NULL, "Right PGA Mixer"},
681 {"Right ADC", NULL, "GPIO1 dmic modclk"},
682
683
684
685
686
687 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
688 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
689 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
690
691
692 {"Left DAC Mux", "DAC_L1", "Left DAC"},
693 {"Left DAC Mux", "DAC_L2", "Left DAC"},
694 {"Left DAC Mux", "DAC_L3", "Left DAC"},
695
696
697 {"Right DAC Mux", "DAC_R1", "Right DAC"},
698 {"Right DAC Mux", "DAC_R2", "Right DAC"},
699 {"Right DAC Mux", "DAC_R3", "Right DAC"},
700
701
702 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
703 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
704 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
705 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
706 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
707 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
708
709 {"Left Line Out", NULL, "Left Line Mixer"},
710 {"Left Line Out", NULL, "Left DAC Mux"},
711 {"LLOUT", NULL, "Left Line Out"},
712
713
714 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
715 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
716 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
717 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
718 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
719 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
720
721 {"Right Line Out", NULL, "Right Line Mixer"},
722 {"Right Line Out", NULL, "Right DAC Mux"},
723 {"RLOUT", NULL, "Right Line Out"},
724
725
726 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
727 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
728 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
729 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
730 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
731 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
732
733 {"Mono Out", NULL, "Mono Mixer"},
734 {"MONO_LOUT", NULL, "Mono Out"},
735
736
737 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
738 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
739 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
740 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
741 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
742 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
743
744 {"Left HP Out", NULL, "Left HP Mixer"},
745 {"Left HP Out", NULL, "Left DAC Mux"},
746 {"HPLOUT", NULL, "Left HP Out"},
747
748
749 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
750 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
751 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
752 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
753 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
754 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
755
756 {"Right HP Out", NULL, "Right HP Mixer"},
757 {"Right HP Out", NULL, "Right DAC Mux"},
758 {"HPROUT", NULL, "Right HP Out"},
759
760
761 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
762 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
763 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
764 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
765 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
766 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
767
768 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
769 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
770 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
771 {"Left HP Com", NULL, "Left HPCOM Mux"},
772 {"HPLCOM", NULL, "Left HP Com"},
773
774
775 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
776 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
777 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
778 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
779 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
780 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
781
782 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
783 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
784 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
785 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
786 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
787 {"Right HP Com", NULL, "Right HPCOM Mux"},
788 {"HPRCOM", NULL, "Right HP Com"},
789};
790
791static const struct snd_soc_dapm_route intercon_3007[] = {
792
793 {"Left Class-D Out", NULL, "Left Line Out"},
794 {"Right Class-D Out", NULL, "Left Line Out"},
795 {"SPOP", NULL, "Left Class-D Out"},
796 {"SPOM", NULL, "Right Class-D Out"},
797};
798
799static int aic3x_add_widgets(struct snd_soc_codec *codec)
800{
801 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
802 struct snd_soc_dapm_context *dapm = &codec->dapm;
803
804 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
805 ARRAY_SIZE(aic3x_dapm_widgets));
806
807
808 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
809
810 if (aic3x->model == AIC3X_MODEL_3007) {
811 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
812 ARRAY_SIZE(aic3007_dapm_widgets));
813 snd_soc_dapm_add_routes(dapm, intercon_3007,
814 ARRAY_SIZE(intercon_3007));
815 }
816
817 return 0;
818}
819
820static int aic3x_hw_params(struct snd_pcm_substream *substream,
821 struct snd_pcm_hw_params *params,
822 struct snd_soc_dai *dai)
823{
824 struct snd_soc_pcm_runtime *rtd = substream->private_data;
825 struct snd_soc_codec *codec =rtd->codec;
826 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
827 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
828 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
829 u16 d, pll_d = 1;
830 u8 reg;
831 int clk;
832
833
834 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
835 switch (params_format(params)) {
836 case SNDRV_PCM_FORMAT_S16_LE:
837 break;
838 case SNDRV_PCM_FORMAT_S20_3LE:
839 data |= (0x01 << 4);
840 break;
841 case SNDRV_PCM_FORMAT_S24_LE:
842 data |= (0x02 << 4);
843 break;
844 case SNDRV_PCM_FORMAT_S32_LE:
845 data |= (0x03 << 4);
846 break;
847 }
848 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
849
850
851 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
852
853
854
855 for (pll_q = 2; pll_q < 18; pll_q++)
856 if (aic3x->sysclk / (128 * pll_q) == fsref) {
857 bypass_pll = 1;
858 break;
859 }
860
861 if (bypass_pll) {
862 pll_q &= 0xf;
863 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
864 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
865
866 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
867 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
868
869 } else {
870 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
871
872 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
873 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
874 }
875
876
877
878 data = (LDAC2LCH | RDAC2RCH);
879 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
880 if (params_rate(params) >= 64000)
881 data |= DUAL_RATE_MODE;
882 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
883
884
885 data = (fsref * 20) / params_rate(params);
886 if (params_rate(params) < 64000)
887 data /= 2;
888 data /= 5;
889 data -= 2;
890 data |= (data << 4);
891 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
892
893 if (bypass_pll)
894 return 0;
895
896
897
898
899
900
901
902 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
903
904 for (r = 1; r <= 16; r++)
905 for (p = 1; p <= 8; p++) {
906 for (j = 4; j <= 55; j++) {
907
908
909
910
911 int tmp_clk = (1000 * j * r) / p;
912
913
914
915
916 if (abs(codec_clk - tmp_clk) <
917 abs(codec_clk - last_clk)) {
918 pll_j = j; pll_d = 0;
919 pll_r = r; pll_p = p;
920 last_clk = tmp_clk;
921 }
922
923
924 if (tmp_clk == codec_clk)
925 goto found;
926 }
927 }
928
929
930 for (p = 1; p <= 8; p++) {
931 j = codec_clk * p / 1000;
932
933 if (j < 4 || j > 11)
934 continue;
935
936
937 d = ((2048 * p * fsref) - j * aic3x->sysclk)
938 * 100 / (aic3x->sysclk/100);
939
940 clk = (10000 * j + d) / (10 * p);
941
942
943
944 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
945 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
946 last_clk = clk;
947 }
948
949
950 if (clk == codec_clk)
951 goto found;
952 }
953
954 if (last_clk == 0) {
955 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
956 return -EINVAL;
957 }
958
959found:
960 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
961 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
962 data | (pll_p << PLLP_SHIFT));
963 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
964 pll_r << PLLR_SHIFT);
965 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
966 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
967 (pll_d >> 6) << PLLD_MSB_SHIFT);
968 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
969 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
970
971 return 0;
972}
973
974static int aic3x_mute(struct snd_soc_dai *dai, int mute)
975{
976 struct snd_soc_codec *codec = dai->codec;
977 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
978 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
979
980 if (mute) {
981 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
982 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
983 } else {
984 snd_soc_write(codec, LDAC_VOL, ldac_reg);
985 snd_soc_write(codec, RDAC_VOL, rdac_reg);
986 }
987
988 return 0;
989}
990
991static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
992 int clk_id, unsigned int freq, int dir)
993{
994 struct snd_soc_codec *codec = codec_dai->codec;
995 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
996
997 aic3x->sysclk = freq;
998 return 0;
999}
1000
1001static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1002 unsigned int fmt)
1003{
1004 struct snd_soc_codec *codec = codec_dai->codec;
1005 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1006 u8 iface_areg, iface_breg;
1007 int delay = 0;
1008
1009 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1010 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1011
1012
1013 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1014 case SND_SOC_DAIFMT_CBM_CFM:
1015 aic3x->master = 1;
1016 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1017 break;
1018 case SND_SOC_DAIFMT_CBS_CFS:
1019 aic3x->master = 0;
1020 break;
1021 default:
1022 return -EINVAL;
1023 }
1024
1025
1026
1027
1028
1029 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1030 SND_SOC_DAIFMT_INV_MASK)) {
1031 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1032 break;
1033 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1034 delay = 1;
1035 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1036 iface_breg |= (0x01 << 6);
1037 break;
1038 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1039 iface_breg |= (0x02 << 6);
1040 break;
1041 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1042 iface_breg |= (0x03 << 6);
1043 break;
1044 default:
1045 return -EINVAL;
1046 }
1047
1048
1049 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1050 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1051 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1052
1053 return 0;
1054}
1055
1056static int aic3x_init_3007(struct snd_soc_codec *codec)
1057{
1058 u8 tmp1, tmp2, *cache = codec->reg_cache;
1059
1060
1061
1062
1063
1064 tmp1 = cache[0xD];
1065 tmp2 = cache[0x8];
1066
1067 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1068 snd_soc_write(codec, 0xD, 0x0D);
1069 snd_soc_write(codec, 0x8, 0x5C);
1070 snd_soc_write(codec, 0x8, 0x5D);
1071 snd_soc_write(codec, 0x8, 0x5C);
1072 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1073 cache[0xD] = tmp1;
1074 cache[0x8] = tmp2;
1075
1076 return 0;
1077}
1078
1079static int aic3x_regulator_event(struct notifier_block *nb,
1080 unsigned long event, void *data)
1081{
1082 struct aic3x_disable_nb *disable_nb =
1083 container_of(nb, struct aic3x_disable_nb, nb);
1084 struct aic3x_priv *aic3x = disable_nb->aic3x;
1085
1086 if (event & REGULATOR_EVENT_DISABLE) {
1087
1088
1089
1090
1091 if (gpio_is_valid(aic3x->gpio_reset))
1092 gpio_set_value(aic3x->gpio_reset, 0);
1093 aic3x->codec->cache_sync = 1;
1094 }
1095
1096 return 0;
1097}
1098
1099static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1100{
1101 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1102 int i, ret;
1103 u8 *cache = codec->reg_cache;
1104
1105 if (power) {
1106 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1107 aic3x->supplies);
1108 if (ret)
1109 goto out;
1110 aic3x->power = 1;
1111
1112
1113
1114
1115 if (!codec->cache_sync)
1116 goto out;
1117
1118 if (gpio_is_valid(aic3x->gpio_reset)) {
1119 udelay(1);
1120 gpio_set_value(aic3x->gpio_reset, 1);
1121 }
1122
1123
1124 codec->cache_only = 0;
1125 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
1126 snd_soc_write(codec, i, cache[i]);
1127 if (aic3x->model == AIC3X_MODEL_3007)
1128 aic3x_init_3007(codec);
1129 codec->cache_sync = 0;
1130 } else {
1131
1132
1133
1134
1135
1136 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1137 codec->cache_sync = 1;
1138 aic3x->power = 0;
1139
1140 codec->cache_only = 1;
1141 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1142 aic3x->supplies);
1143 }
1144out:
1145 return ret;
1146}
1147
1148static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1149 enum snd_soc_bias_level level)
1150{
1151 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1152 u8 reg;
1153
1154 switch (level) {
1155 case SND_SOC_BIAS_ON:
1156 break;
1157 case SND_SOC_BIAS_PREPARE:
1158 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1159 aic3x->master) {
1160
1161 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1162 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1163 reg | PLL_ENABLE);
1164 }
1165 break;
1166 case SND_SOC_BIAS_STANDBY:
1167 if (!aic3x->power)
1168 aic3x_set_power(codec, 1);
1169 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1170 aic3x->master) {
1171
1172 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1173 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1174 reg & ~PLL_ENABLE);
1175 }
1176 break;
1177 case SND_SOC_BIAS_OFF:
1178 if (aic3x->power)
1179 aic3x_set_power(codec, 0);
1180 break;
1181 }
1182 codec->dapm.bias_level = level;
1183
1184 return 0;
1185}
1186
1187void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1188{
1189 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1190 u8 bit = gpio ? 3: 0;
1191 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1192 snd_soc_write(codec, reg, val | (!!state << bit));
1193}
1194EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1195
1196int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1197{
1198 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1199 u8 val = 0, bit = gpio ? 2 : 1;
1200
1201 aic3x_read(codec, reg, &val);
1202 return (val >> bit) & 1;
1203}
1204EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1205
1206void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1207 int headset_debounce, int button_debounce)
1208{
1209 u8 val;
1210
1211 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1212 << AIC3X_HEADSET_DETECT_SHIFT) |
1213 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1214 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1215 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1216 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1217
1218 if (detect & AIC3X_HEADSET_DETECT_MASK)
1219 val |= AIC3X_HEADSET_DETECT_ENABLED;
1220
1221 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1222}
1223EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1224
1225int aic3x_headset_detected(struct snd_soc_codec *codec)
1226{
1227 u8 val = 0;
1228 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1229 return (val >> 4) & 1;
1230}
1231EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1232
1233int aic3x_button_pressed(struct snd_soc_codec *codec)
1234{
1235 u8 val = 0;
1236 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1237 return (val >> 5) & 1;
1238}
1239EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1240
1241#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1242#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1243 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1244
1245static struct snd_soc_dai_ops aic3x_dai_ops = {
1246 .hw_params = aic3x_hw_params,
1247 .digital_mute = aic3x_mute,
1248 .set_sysclk = aic3x_set_dai_sysclk,
1249 .set_fmt = aic3x_set_dai_fmt,
1250};
1251
1252static struct snd_soc_dai_driver aic3x_dai = {
1253 .name = "tlv320aic3x-hifi",
1254 .playback = {
1255 .stream_name = "Playback",
1256 .channels_min = 1,
1257 .channels_max = 2,
1258 .rates = AIC3X_RATES,
1259 .formats = AIC3X_FORMATS,},
1260 .capture = {
1261 .stream_name = "Capture",
1262 .channels_min = 1,
1263 .channels_max = 2,
1264 .rates = AIC3X_RATES,
1265 .formats = AIC3X_FORMATS,},
1266 .ops = &aic3x_dai_ops,
1267 .symmetric_rates = 1,
1268};
1269
1270static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
1271{
1272 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1273
1274 return 0;
1275}
1276
1277static int aic3x_resume(struct snd_soc_codec *codec)
1278{
1279 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1280
1281 return 0;
1282}
1283
1284
1285
1286
1287
1288static int aic3x_init(struct snd_soc_codec *codec)
1289{
1290 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1291 int reg;
1292
1293 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1294 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1295
1296
1297 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1298 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1299
1300
1301 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1302 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1303 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1304 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1305
1306 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1307 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1308
1309 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1310 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1311
1312
1313 reg = snd_soc_read(codec, LLOPM_CTRL);
1314 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1315 reg = snd_soc_read(codec, RLOPM_CTRL);
1316 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1317 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1318 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1319 reg = snd_soc_read(codec, HPLOUT_CTRL);
1320 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1321 reg = snd_soc_read(codec, HPROUT_CTRL);
1322 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1323 reg = snd_soc_read(codec, HPLCOM_CTRL);
1324 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1325 reg = snd_soc_read(codec, HPRCOM_CTRL);
1326 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1327
1328
1329 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1330 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1331
1332 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1333 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1334
1335
1336 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1337 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1338 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1339 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1340
1341 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1342 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1343
1344 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1345 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1346
1347
1348 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1349 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1350 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1351 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1352
1353 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1354 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1355
1356 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1357 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1358
1359 if (aic3x->model == AIC3X_MODEL_3007) {
1360 aic3x_init_3007(codec);
1361 snd_soc_write(codec, CLASSD_CTRL, 0);
1362 }
1363
1364 return 0;
1365}
1366
1367static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1368{
1369 struct aic3x_priv *a;
1370
1371 list_for_each_entry(a, &reset_list, list) {
1372 if (gpio_is_valid(aic3x->gpio_reset) &&
1373 aic3x->gpio_reset == a->gpio_reset)
1374 return true;
1375 }
1376
1377 return false;
1378}
1379
1380static int aic3x_probe(struct snd_soc_codec *codec)
1381{
1382 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1383 int ret, i;
1384
1385 INIT_LIST_HEAD(&aic3x->list);
1386 codec->control_data = aic3x->control_data;
1387 aic3x->codec = codec;
1388 codec->dapm.idle_bias_off = 1;
1389
1390 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1391 if (ret != 0) {
1392 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1393 return ret;
1394 }
1395
1396 if (gpio_is_valid(aic3x->gpio_reset) &&
1397 !aic3x_is_shared_reset(aic3x)) {
1398 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1399 if (ret != 0)
1400 goto err_gpio;
1401 gpio_direction_output(aic3x->gpio_reset, 0);
1402 }
1403
1404 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1405 aic3x->supplies[i].supply = aic3x_supply_names[i];
1406
1407 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1408 aic3x->supplies);
1409 if (ret != 0) {
1410 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1411 goto err_get;
1412 }
1413 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1414 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1415 aic3x->disable_nb[i].aic3x = aic3x;
1416 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1417 &aic3x->disable_nb[i].nb);
1418 if (ret) {
1419 dev_err(codec->dev,
1420 "Failed to request regulator notifier: %d\n",
1421 ret);
1422 goto err_notif;
1423 }
1424 }
1425
1426 codec->cache_only = 1;
1427 aic3x_init(codec);
1428
1429 if (aic3x->setup) {
1430
1431 snd_soc_write(codec, AIC3X_GPIO1_REG,
1432 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1433 snd_soc_write(codec, AIC3X_GPIO2_REG,
1434 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1435 }
1436
1437 snd_soc_add_controls(codec, aic3x_snd_controls,
1438 ARRAY_SIZE(aic3x_snd_controls));
1439 if (aic3x->model == AIC3X_MODEL_3007)
1440 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1441
1442 aic3x_add_widgets(codec);
1443 list_add(&aic3x->list, &reset_list);
1444
1445 return 0;
1446
1447err_notif:
1448 while (i--)
1449 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1450 &aic3x->disable_nb[i].nb);
1451 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1452err_get:
1453 if (gpio_is_valid(aic3x->gpio_reset) &&
1454 !aic3x_is_shared_reset(aic3x))
1455 gpio_free(aic3x->gpio_reset);
1456err_gpio:
1457 return ret;
1458}
1459
1460static int aic3x_remove(struct snd_soc_codec *codec)
1461{
1462 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1463 int i;
1464
1465 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1466 list_del(&aic3x->list);
1467 if (gpio_is_valid(aic3x->gpio_reset) &&
1468 !aic3x_is_shared_reset(aic3x)) {
1469 gpio_set_value(aic3x->gpio_reset, 0);
1470 gpio_free(aic3x->gpio_reset);
1471 }
1472 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1473 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1474 &aic3x->disable_nb[i].nb);
1475 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1476
1477 return 0;
1478}
1479
1480static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1481 .set_bias_level = aic3x_set_bias_level,
1482 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1483 .reg_word_size = sizeof(u8),
1484 .reg_cache_default = aic3x_reg,
1485 .probe = aic3x_probe,
1486 .remove = aic3x_remove,
1487 .suspend = aic3x_suspend,
1488 .resume = aic3x_resume,
1489};
1490
1491#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1492
1493
1494
1495
1496
1497static const struct i2c_device_id aic3x_i2c_id[] = {
1498 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1499 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1500 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1501 { }
1502};
1503MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1504
1505
1506
1507
1508
1509static int aic3x_i2c_probe(struct i2c_client *i2c,
1510 const struct i2c_device_id *id)
1511{
1512 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1513 struct aic3x_priv *aic3x;
1514 int ret;
1515 const struct i2c_device_id *tbl;
1516
1517 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1518 if (aic3x == NULL) {
1519 dev_err(&i2c->dev, "failed to create private data\n");
1520 return -ENOMEM;
1521 }
1522
1523 aic3x->control_data = i2c;
1524 aic3x->control_type = SND_SOC_I2C;
1525
1526 i2c_set_clientdata(i2c, aic3x);
1527 if (pdata) {
1528 aic3x->gpio_reset = pdata->gpio_reset;
1529 aic3x->setup = pdata->setup;
1530 } else {
1531 aic3x->gpio_reset = -1;
1532 }
1533
1534 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1535 if (!strcmp(tbl->name, id->name))
1536 break;
1537 }
1538 aic3x->model = tbl - aic3x_i2c_id;
1539
1540 ret = snd_soc_register_codec(&i2c->dev,
1541 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1542 if (ret < 0)
1543 kfree(aic3x);
1544 return ret;
1545}
1546
1547static int aic3x_i2c_remove(struct i2c_client *client)
1548{
1549 snd_soc_unregister_codec(&client->dev);
1550 kfree(i2c_get_clientdata(client));
1551 return 0;
1552}
1553
1554
1555static struct i2c_driver aic3x_i2c_driver = {
1556 .driver = {
1557 .name = "tlv320aic3x-codec",
1558 .owner = THIS_MODULE,
1559 },
1560 .probe = aic3x_i2c_probe,
1561 .remove = aic3x_i2c_remove,
1562 .id_table = aic3x_i2c_id,
1563};
1564#endif
1565
1566static int __init aic3x_modinit(void)
1567{
1568 int ret = 0;
1569#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1570 ret = i2c_add_driver(&aic3x_i2c_driver);
1571 if (ret != 0) {
1572 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1573 ret);
1574 }
1575#endif
1576 return ret;
1577}
1578module_init(aic3x_modinit);
1579
1580static void __exit aic3x_exit(void)
1581{
1582#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1583 i2c_del_driver(&aic3x_i2c_driver);
1584#endif
1585}
1586module_exit(aic3x_exit);
1587
1588MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1589MODULE_AUTHOR("Vladimir Barinov");
1590MODULE_LICENSE("GPL");
1591
