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11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/mm.h>
14#include <linux/sched.h>
15#include <linux/pci.h>
16#include <linux/ioport.h>
17#include <linux/timex.h>
18#include <linux/init.h>
19
20#include <asm/ptrace.h>
21#include <asm/dma.h>
22#include <asm/irq.h>
23#include <asm/mmu_context.h>
24#include <asm/io.h>
25#include <asm/pgtable.h>
26#include <asm/core_cia.h>
27#include <asm/tlbflush.h>
28
29#include "proto.h"
30#include "irq_impl.h"
31#include "pci_impl.h"
32#include "machvec_impl.h"
33
34
35static void __init
36ruffian_init_irq(void)
37{
38
39 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
40 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb();
41
42 outb(0x11,0xA0);
43 outb(0x08,0xA1);
44 outb(0x02,0xA1);
45 outb(0x01,0xA1);
46 outb(0xFF,0xA1);
47
48 outb(0x11,0x20);
49 outb(0x00,0x21);
50 outb(0x04,0x21);
51 outb(0x01,0x21);
52 outb(0xFF,0x21);
53
54
55 outb(0x20,0xA0);
56 outb(0x20,0x20);
57
58 init_i8259a_irqs();
59
60
61
62 init_pyxis_irqs(0x16f0000);
63
64 common_init_isa_dma();
65}
66
67#define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ)
68
69static void __init
70ruffian_init_rtc(void)
71{
72
73
74
75
76 outb(0x34, 0x43);
77 outb(RUFFIAN_LATCH & 0xff, 0x40);
78 outb(RUFFIAN_LATCH >> 8, 0x40);
79
80 outb(0xb6, 0x43);
81 outb(0x31, 0x42);
82 outb(0x13, 0x42);
83
84 setup_irq(0, &timer_irqaction);
85}
86
87static void
88ruffian_kill_arch (int mode)
89{
90 cia_kill_arch(mode);
91#if 0
92
93
94 *(vuip) PYXIS_RESET = 0x0000dead;
95 mb();
96#endif
97}
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120static int __init
121ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
122{
123 static char irq_tab[11][5] __initdata = {
124
125 {-1, -1, -1, -1, -1},
126 {-1, -1, -1, -1, -1},
127 {44, 44, 44, 44, 44},
128 {-1, -1, -1, -1, -1},
129 {43, 43, 42, 41, 40},
130
131 {19, 19, 18, 17, 16},
132 {31, 31, 30, 29, 28},
133 {27, 27, 26, 25, 24},
134 {39, 39, 38, 37, 36},
135 {35, 35, 34, 33, 32},
136 {20, 20, 20, 20, 20},
137 };
138 const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
139 return COMMON_TABLE_LOOKUP;
140}
141
142static u8 __init
143ruffian_swizzle(struct pci_dev *dev, u8 *pinp)
144{
145 int slot, pin = *pinp;
146
147 if (dev->bus->number == 0) {
148 slot = PCI_SLOT(dev->devfn);
149 }
150
151 else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
152 slot = PCI_SLOT(dev->devfn) + 10;
153 }
154 else
155 {
156
157 do {
158 if (PCI_SLOT(dev->bus->self->devfn) == 13) {
159 slot = PCI_SLOT(dev->devfn) + 10;
160 break;
161 }
162 pin = pci_swizzle_interrupt_pin(dev, pin);
163
164
165 dev = dev->bus->self;
166
167 slot = PCI_SLOT(dev->devfn);
168 } while (dev->bus->self);
169 }
170 *pinp = pin;
171 return slot;
172}
173
174#ifdef BUILDING_FOR_MILO
175
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179
180static unsigned long __init
181ruffian_get_bank_size(unsigned long offset)
182{
183 unsigned long bank_addr, bank, ret = 0;
184
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186
187 bank_addr = (unsigned long)PYXIS_MCR + offset;
188 bank = *(vulp)bank_addr;
189
190
191 if (bank & 0x01) {
192 static unsigned long size[] __initdata = {
193 0x40000000UL,
194 0x20000000UL,
195 0x10000000UL,
196 0x08000000UL,
197 0x04000000UL,
198 0x02000000UL,
199 0x01000000UL,
200 0x00800000UL,
201 0x80000000UL,
202 };
203
204 bank = (bank & 0x1e) >> 1;
205 if (bank < ARRAY_SIZE(size))
206 ret = size[bank];
207 }
208
209 return ret;
210}
211#endif
212
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216
217struct alpha_machine_vector ruffian_mv __initmv = {
218 .vector_name = "Ruffian",
219 DO_EV5_MMU,
220 DO_DEFAULT_RTC,
221 DO_PYXIS_IO,
222 .machine_check = cia_machine_check,
223 .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
224 .min_io_address = DEFAULT_IO_BASE,
225 .min_mem_address = DEFAULT_MEM_BASE,
226 .pci_dac_offset = PYXIS_DAC_OFFSET,
227
228 .nr_irqs = 48,
229 .device_interrupt = pyxis_device_interrupt,
230
231 .init_arch = pyxis_init_arch,
232 .init_irq = ruffian_init_irq,
233 .init_rtc = ruffian_init_rtc,
234 .init_pci = cia_init_pci,
235 .kill_arch = ruffian_kill_arch,
236 .pci_map_irq = ruffian_map_irq,
237 .pci_swizzle = ruffian_swizzle,
238};
239ALIAS_MV(ruffian)
240