1/* 2 * arch/arm/include/asm/hardware/cache-l2x0.h 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#ifndef __ASM_ARM_HARDWARE_L2X0_H 21#define __ASM_ARM_HARDWARE_L2X0_H 22 23#include <linux/errno.h> 24 25#define L2X0_CACHE_ID 0x000 26#define L2X0_CACHE_TYPE 0x004 27#define L2X0_CTRL 0x100 28#define L2X0_AUX_CTRL 0x104 29#define L2X0_TAG_LATENCY_CTRL 0x108 30#define L2X0_DATA_LATENCY_CTRL 0x10C 31#define L2X0_EVENT_CNT_CTRL 0x200 32#define L2X0_EVENT_CNT1_CFG 0x204 33#define L2X0_EVENT_CNT0_CFG 0x208 34#define L2X0_EVENT_CNT1_VAL 0x20C 35#define L2X0_EVENT_CNT0_VAL 0x210 36#define L2X0_INTR_MASK 0x214 37#define L2X0_MASKED_INTR_STAT 0x218 38#define L2X0_RAW_INTR_STAT 0x21C 39#define L2X0_INTR_CLEAR 0x220 40#define L2X0_CACHE_SYNC 0x730 41#define L2X0_DUMMY_REG 0x740 42#define L2X0_INV_LINE_PA 0x770 43#define L2X0_INV_WAY 0x77C 44#define L2X0_CLEAN_LINE_PA 0x7B0 45#define L2X0_CLEAN_LINE_IDX 0x7B8 46#define L2X0_CLEAN_WAY 0x7BC 47#define L2X0_CLEAN_INV_LINE_PA 0x7F0 48#define L2X0_CLEAN_INV_LINE_IDX 0x7F8 49#define L2X0_CLEAN_INV_WAY 0x7FC 50/* 51 * The lockdown registers repeat 8 times for L310, the L210 has only one 52 * D and one I lockdown register at 0x0900 and 0x0904. 53 */ 54#define L2X0_LOCKDOWN_WAY_D_BASE 0x900 55#define L2X0_LOCKDOWN_WAY_I_BASE 0x904 56#define L2X0_LOCKDOWN_STRIDE 0x08 57#define L2X0_ADDR_FILTER_START 0xC00 58#define L2X0_ADDR_FILTER_END 0xC04 59#define L2X0_TEST_OPERATION 0xF00 60#define L2X0_LINE_DATA 0xF10 61#define L2X0_LINE_TAG 0xF30 62#define L2X0_DEBUG_CTRL 0xF40 63#define L2X0_PREFETCH_CTRL 0xF60 64#define L2X0_POWER_CTRL 0xF80 65#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) 66#define L2X0_STNDBY_MODE_EN (1 << 0) 67 68/* Registers shifts and masks */ 69#define L2X0_CACHE_ID_PART_MASK (0xf << 6) 70#define L2X0_CACHE_ID_PART_L210 (1 << 6) 71#define L2X0_CACHE_ID_PART_L310 (3 << 6) 72#define L2X0_CACHE_ID_RTL_MASK 0x3f 73#define L2X0_CACHE_ID_RTL_R0P0 0x0 74#define L2X0_CACHE_ID_RTL_R1P0 0x2 75#define L2X0_CACHE_ID_RTL_R2P0 0x4 76#define L2X0_CACHE_ID_RTL_R3P0 0x5 77#define L2X0_CACHE_ID_RTL_R3P1 0x6 78#define L2X0_CACHE_ID_RTL_R3P2 0x8 79 80#define L2X0_AUX_CTRL_MASK 0xc0000fff 81#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 82#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 83#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 84#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3) 85#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 86#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6) 87#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 88#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9) 89#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 90#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 91#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) 92#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 93#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 94#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 95#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28 96#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 97#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 98 99#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0 100#define L2X0_LATENCY_CTRL_RD_SHIFT 4 101#define L2X0_LATENCY_CTRL_WR_SHIFT 8 102 103#define L2X0_ADDR_FILTER_EN 1 104 105#define L2X0_CTRL_EN 1 106 107#define L2X0_WAY_SIZE_SHIFT 3 108 109#ifndef __ASSEMBLY__ 110extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); 111#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) 112extern int l2x0_of_init(u32 aux_val, u32 aux_mask); 113#else 114static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) 115{ 116 return -ENODEV; 117} 118#endif 119 120struct l2x0_regs { 121 unsigned long phy_base; 122 unsigned long aux_ctrl; 123 /* 124 * Whether the following registers need to be saved/restored 125 * depends on platform 126 */ 127 unsigned long tag_latency; 128 unsigned long data_latency; 129 unsigned long filter_start; 130 unsigned long filter_end; 131 unsigned long prefetch_ctrl; 132 unsigned long pwr_ctrl; 133 unsigned long ctrl; 134}; 135 136extern struct l2x0_regs l2x0_saved_regs; 137 138#endif /* __ASSEMBLY__ */ 139 140#endif 141