1#ifndef __MACH_MX53_H__ 2#define __MACH_MX53_H__ 3 4/* 5 * IROM 6 */ 7#define MX53_IROM_BASE_ADDR 0x0 8#define MX53_IROM_SIZE SZ_64K 9 10/* TZIC */ 11#define MX53_TZIC_BASE_ADDR 0x0FFFC000 12#define MX53_TZIC_SIZE SZ_16K 13 14/* 15 * AHCI SATA 16 */ 17#define MX53_SATA_BASE_ADDR 0x10000000 18 19/* 20 * NFC 21 */ 22#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ 23#define MX53_NFC_AXI_SIZE SZ_64K 24 25/* 26 * IRAM 27 */ 28#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ 29#define MX53_IRAM_PARTITIONS 16 30#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 31 32/* 33 * Graphics Memory of GPU 34 */ 35#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 36#define MX53_GPU2D_BASE_ADDR 0x20000000 37#define MX53_GPU_BASE_ADDR 0x30000000 38#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 39 40#define MX53_DEBUG_BASE_ADDR 0x40000000 41#define MX53_DEBUG_SIZE SZ_1M 42#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) 43#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) 44#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) 45#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) 46#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) 47#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) 48#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) 49#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) 50 51/* 52 * SPBA global module enabled #0 53 */ 54#define MX53_SPBA0_BASE_ADDR 0x50000000 55#define MX53_SPBA0_SIZE SZ_1M 56 57#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) 58#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) 59#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) 60#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) 61#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) 62#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) 63#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) 64#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) 65#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) 66#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) 67#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) 68#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) 69#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) 70 71/* 72 * AIPS 1 73 */ 74#define MX53_AIPS1_BASE_ADDR 0x53F00000 75#define MX53_AIPS1_SIZE SZ_1M 76 77#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) 78#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) 79#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) 80#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) 81#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) 82#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) 83#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) 84#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) 85#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) 86#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) 87#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) 88#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) 89#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) 90#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) 91#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) 92#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) 93#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) 94#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) 95#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) 96#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) 97#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) 98#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) 99#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) 100#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) 101#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) 102#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) 103 104/* 105 * AIPS 2 106 */ 107#define MX53_AIPS2_BASE_ADDR 0x63F00000 108#define MX53_AIPS2_SIZE SZ_1M 109 110#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) 111#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) 112#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) 113#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) 114#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) 115#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) 116#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) 117#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) 118#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) 119#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) 120#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) 121#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) 122#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) 123#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) 124#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) 125#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) 126#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) 127#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) 128#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) 129#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) 130#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) 131#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) 132#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) 133#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) 134#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) 135#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) 136#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) 137#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) 138#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) 139#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) 140#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) 141#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) 142#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) 143#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) 144#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) 145 146/* 147 * Memory regions and CS 148 */ 149#define MX53_CSD0_BASE_ADDR 0x70000000 150#define MX53_CSD1_BASE_ADDR 0xB0000000 151#define MX53_CS0_BASE_ADDR 0xF0000000 152#define MX53_CS1_32MB_BASE_ADDR 0xF2000000 153#define MX53_CS1_64MB_BASE_ADDR 0xF4000000 154#define MX53_CS2_64MB_BASE_ADDR 0xF4000000 155#define MX53_CS2_96MB_BASE_ADDR 0xF6000000 156#define MX53_CS3_BASE_ADDR 0xF6000000 157 158#define MX53_IO_P2V(x) IMX_IO_P2V(x) 159#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) 160 161/* 162 * defines for SPBA modules 163 */ 164#define MX53_SPBA_SDHC1 0x04 165#define MX53_SPBA_SDHC2 0x08 166#define MX53_SPBA_UART3 0x0C 167#define MX53_SPBA_CSPI1 0x10 168#define MX53_SPBA_SSI2 0x14 169#define MX53_SPBA_SDHC3 0x20 170#define MX53_SPBA_SDHC4 0x24 171#define MX53_SPBA_SPDIF 0x28 172#define MX53_SPBA_ATA 0x30 173#define MX53_SPBA_SLIM 0x34 174#define MX53_SPBA_HSI2C 0x38 175#define MX53_SPBA_CTRL 0x3C 176 177/* 178 * DMA request assignments 179 */ 180#define MX53_DMA_REQ_SSI3_TX0 47 181#define MX53_DMA_REQ_SSI3_RX0 46 182#define MX53_DMA_REQ_SSI3_TX1 45 183#define MX53_DMA_REQ_SSI3_RX1 44 184#define MX53_DMA_REQ_UART3_TX 43 185#define MX53_DMA_REQ_UART3_RX 42 186#define MX53_DMA_REQ_ESAI_TX 41 187#define MX53_DMA_REQ_ESAI_RX 40 188#define MX53_DMA_REQ_CSPI_TX 39 189#define MX53_DMA_REQ_CSPI_RX 38 190#define MX53_DMA_REQ_ASRC_DMA6 37 191#define MX53_DMA_REQ_ASRC_DMA5 36 192#define MX53_DMA_REQ_ASRC_DMA4 35 193#define MX53_DMA_REQ_ASRC_DMA3 34 194#define MX53_DMA_REQ_ASRC_DMA2 33 195#define MX53_DMA_REQ_ASRC_DMA1 32 196#define MX53_DMA_REQ_EMI_WR 31 197#define MX53_DMA_REQ_EMI_RD 30 198#define MX53_DMA_REQ_SSI1_TX0 29 199#define MX53_DMA_REQ_SSI1_RX0 28 200#define MX53_DMA_REQ_SSI1_TX1 27 201#define MX53_DMA_REQ_SSI1_RX1 26 202#define MX53_DMA_REQ_SSI2_TX0 25 203#define MX53_DMA_REQ_SSI2_RX0 24 204#define MX53_DMA_REQ_SSI2_TX1 23 205#define MX53_DMA_REQ_SSI2_RX1 22 206#define MX53_DMA_REQ_I2C2_SDHC2 21 207#define MX53_DMA_REQ_I2C1_SDHC1 20 208#define MX53_DMA_REQ_UART1_TX 19 209#define MX53_DMA_REQ_UART1_RX 18 210#define MX53_DMA_REQ_UART5_TX 17 211#define MX53_DMA_REQ_UART5_RX 16 212#define MX53_DMA_REQ_SPDIF_TX 15 213#define MX53_DMA_REQ_SPDIF_RX 14 214#define MX53_DMA_REQ_UART2_FIRI_TX 13 215#define MX53_DMA_REQ_UART2_FIRI_RX 12 216#define MX53_DMA_REQ_SDHC4 11 217#define MX53_DMA_REQ_I2C3_SDHC3 10 218#define MX53_DMA_REQ_CSPI2_TX 9 219#define MX53_DMA_REQ_CSPI2_RX 8 220#define MX53_DMA_REQ_CSPI1_TX 7 221#define MX53_DMA_REQ_CSPI1_RX 6 222#define MX53_DMA_REQ_IPU 5 223#define MX53_DMA_REQ_ATA_TX_END 4 224#define MX53_DMA_REQ_ATA_UART4_TX 3 225#define MX53_DMA_REQ_ATA_UART4_RX 2 226#define MX53_DMA_REQ_GPC 1 227#define MX53_DMA_REQ_VPU 0 228 229/* 230 * Interrupt numbers 231 */ 232#include <asm/irq.h> 233#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0) 234#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1) 235#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2) 236#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3) 237#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4) 238#define MX53_INT_DAP (NR_IRQS_LEGACY + 5) 239#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6) 240#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7) 241#define MX53_INT_NFC (NR_IRQS_LEGACY + 8) 242#define MX53_INT_VPU (NR_IRQS_LEGACY + 9) 243#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10) 244#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11) 245#define MX53_INT_GPU (NR_IRQS_LEGACY + 12) 246#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13) 247#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14) 248#define MX53_INT_EMI (NR_IRQS_LEGACY + 15) 249#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16) 250#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17) 251#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18) 252#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) 253#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) 254#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21) 255#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22) 256#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23) 257#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) 258#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) 259#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26) 260#define MX53_INT_CSU (NR_IRQS_LEGACY + 27) 261#define MX53_INT_SATA (NR_IRQS_LEGACY + 28) 262#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29) 263#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30) 264#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31) 265#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32) 266#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33) 267#define MX53_INT_RTC (NR_IRQS_LEGACY + 34) 268#define MX53_INT_PTP (NR_IRQS_LEGACY + 35) 269#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36) 270#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37) 271#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38) 272#define MX53_INT_GPT (NR_IRQS_LEGACY + 39) 273#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40) 274#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41) 275#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) 276#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) 277#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) 278#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) 279#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) 280#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) 281#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) 282#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) 283#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) 284#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) 285#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) 286#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) 287#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) 288#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) 289#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) 290#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) 291#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58) 292#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59) 293#define MX53_INT_KPP (NR_IRQS_LEGACY + 60) 294#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61) 295#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62) 296#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63) 297#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64) 298#define MX53_INT_MLB (NR_IRQS_LEGACY + 65) 299#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66) 300#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67) 301#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68) 302#define MX53_INT_IIM (NR_IRQS_LEGACY + 69) 303#define MX53_INT_ATA (NR_IRQS_LEGACY + 70) 304#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71) 305#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72) 306#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73) 307#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74) 308#define MX53_INT_SRC (NR_IRQS_LEGACY + 75) 309#define MX53_INT_NM (NR_IRQS_LEGACY + 76) 310#define MX53_INT_PMU (NR_IRQS_LEGACY + 77) 311#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) 312#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) 313#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) 314#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81) 315#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82) 316#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83) 317#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) 318#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) 319#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86) 320#define MX53_INT_FEC (NR_IRQS_LEGACY + 87) 321#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88) 322#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) 323#define MX53_INT_SJC (NR_IRQS_LEGACY + 90) 324#define MX53_INT_TVE (NR_IRQS_LEGACY + 92) 325#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93) 326#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94) 327#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) 328#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96) 329#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) 330#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) 331#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99) 332#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) 333#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101) 334#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) 335#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) 336#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) 337#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) 338#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) 339#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107) 340#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108) 341 342#endif /* ifndef __MACH_MX53_H__ */ 343