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38#include <linux/suspend.h>
39#include <linux/sched.h>
40#include <linux/debugfs.h>
41#include <linux/seq_file.h>
42#include <linux/interrupt.h>
43#include <linux/sysfs.h>
44#include <linux/module.h>
45#include <linux/io.h>
46#include <linux/atomic.h>
47#include <linux/cpu.h>
48
49#include <asm/fncpy.h>
50#include <asm/system_misc.h>
51#include <asm/irq.h>
52#include <asm/mach/time.h>
53#include <asm/mach/irq.h>
54
55#include <mach/tc.h>
56#include <mach/mux.h>
57#include <linux/omap-dma.h>
58#include <plat/dmtimer.h>
59
60#include <mach/irqs.h>
61
62#include "iomap.h"
63#include "clock.h"
64#include "pm.h"
65#include "sram.h"
66
67static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
68static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
69static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
70static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
71static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
72static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
73
74#ifdef CONFIG_OMAP_32K_TIMER
75
76static unsigned short enable_dyn_sleep = 1;
77
78static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
79 char *buf)
80{
81 return sprintf(buf, "%hu\n", enable_dyn_sleep);
82}
83
84static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
85 const char * buf, size_t n)
86{
87 unsigned short value;
88 if (sscanf(buf, "%hu", &value) != 1 ||
89 (value != 0 && value != 1)) {
90 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
91 return -EINVAL;
92 }
93 enable_dyn_sleep = value;
94 return n;
95}
96
97static struct kobj_attribute sleep_while_idle_attr =
98 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
99
100#endif
101
102static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
103
104
105
106
107
108
109
110void omap1_pm_idle(void)
111{
112 extern __u32 arm_idlect1_mask;
113 __u32 use_idlect1 = arm_idlect1_mask;
114 int do_sleep = 0;
115
116 local_fiq_disable();
117
118#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
119#warning Enable 32kHz OS timer in order to allow sleep states in idle
120 use_idlect1 = use_idlect1 & ~(1 << 9);
121#else
122
123 while (enable_dyn_sleep) {
124
125#ifdef CONFIG_CBUS_TAHVO_USB
126 extern int vbus_active;
127
128 if (vbus_active)
129 break;
130#endif
131 do_sleep = 1;
132 break;
133 }
134
135#endif
136
137#ifdef CONFIG_OMAP_DM_TIMER
138 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
139#endif
140
141 if (omap_dma_running())
142 use_idlect1 &= ~(1 << 6);
143
144
145
146
147 if ((use_idlect1 != ~0) || !do_sleep) {
148
149 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
150 if (cpu_is_omap15xx())
151 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
152 else
153 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
154 omap_writel(use_idlect1, ARM_IDLECT1);
155 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
156 omap_writel(saved_idlect1, ARM_IDLECT1);
157
158 local_fiq_enable();
159 return;
160 }
161 omap_sram_suspend(omap_readl(ARM_IDLECT1),
162 omap_readl(ARM_IDLECT2));
163
164 local_fiq_enable();
165}
166
167
168
169
170
171
172static void omap_pm_wakeup_setup(void)
173{
174 u32 level1_wake = 0;
175 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
176
177
178
179
180
181
182
183 if (cpu_is_omap7xx())
184 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
185 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
186 else if (cpu_is_omap15xx())
187 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
188 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
189 else if (cpu_is_omap16xx())
190 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
191 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
192
193 omap_writel(~level1_wake, OMAP_IH1_MIR);
194
195 if (cpu_is_omap7xx()) {
196 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
197 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
198 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
199 OMAP_IH2_1_MIR);
200 } else if (cpu_is_omap15xx()) {
201 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
202 omap_writel(~level2_wake, OMAP_IH2_MIR);
203 } else if (cpu_is_omap16xx()) {
204 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
205 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
206
207
208 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
209 OMAP_IH2_1_MIR);
210 omap_writel(~0x0, OMAP_IH2_2_MIR);
211 omap_writel(~0x0, OMAP_IH2_3_MIR);
212 }
213
214
215 omap_writel(1, OMAP_IH2_CONTROL);
216 omap_writel(1, OMAP_IH1_CONTROL);
217}
218
219#define EN_DSPCK 13
220#define EN_APICK 6
221#define DSP_EN 1
222
223void omap1_pm_suspend(void)
224{
225 unsigned long arg0 = 0, arg1 = 0;
226
227 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
228 omap_rev());
229
230 omap_serial_wake_trigger(1);
231
232 if (!cpu_is_omap15xx())
233 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
234
235
236
237
238
239 local_irq_disable();
240 local_fiq_disable();
241
242
243
244
245
246
247
248
249
250
251
252
253 if (cpu_is_omap7xx()) {
254 MPUI7XX_SAVE(OMAP_IH1_MIR);
255 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
256 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
257 MPUI7XX_SAVE(MPUI_CTRL);
258 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
259 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
260 MPUI7XX_SAVE(EMIFS_CONFIG);
261 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
262
263 } else if (cpu_is_omap15xx()) {
264 MPUI1510_SAVE(OMAP_IH1_MIR);
265 MPUI1510_SAVE(OMAP_IH2_MIR);
266 MPUI1510_SAVE(MPUI_CTRL);
267 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
268 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
269 MPUI1510_SAVE(EMIFS_CONFIG);
270 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
271 } else if (cpu_is_omap16xx()) {
272 MPUI1610_SAVE(OMAP_IH1_MIR);
273 MPUI1610_SAVE(OMAP_IH2_0_MIR);
274 MPUI1610_SAVE(OMAP_IH2_1_MIR);
275 MPUI1610_SAVE(OMAP_IH2_2_MIR);
276 MPUI1610_SAVE(OMAP_IH2_3_MIR);
277 MPUI1610_SAVE(MPUI_CTRL);
278 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
279 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
280 MPUI1610_SAVE(EMIFS_CONFIG);
281 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
282 }
283
284 ARM_SAVE(ARM_CKCTL);
285 ARM_SAVE(ARM_IDLECT1);
286 ARM_SAVE(ARM_IDLECT2);
287 if (!(cpu_is_omap15xx()))
288 ARM_SAVE(ARM_IDLECT3);
289 ARM_SAVE(ARM_EWUPCT);
290 ARM_SAVE(ARM_RSTCT1);
291 ARM_SAVE(ARM_RSTCT2);
292 ARM_SAVE(ARM_SYSST);
293 ULPD_SAVE(ULPD_CLOCK_CTRL);
294 ULPD_SAVE(ULPD_STATUS_REQ);
295
296
297
298
299
300
301
302
303 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
304
305
306 if (!cpu_is_omap7xx())
307 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
308
309
310 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
311
312
313 DSP_SAVE(DSP_IDLECT2);
314
315
316 __raw_writew(0, DSP_IDLECT2);
317
318
319
320
321
322 omap_pm_wakeup_setup();
323
324
325
326
327
328
329 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
330 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
331
332
333
334
335
336
337
338
339
340
341
342
343
344 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
345 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
346
347
348
349
350
351
352
353 omap_sram_suspend(arg0, arg1);
354
355
356
357
358
359
360
361
362
363
364 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
365
366
367 DSP_RESTORE(DSP_IDLECT2);
368
369
370
371
372
373 if (!(cpu_is_omap15xx()))
374 ARM_RESTORE(ARM_IDLECT3);
375 ARM_RESTORE(ARM_CKCTL);
376 ARM_RESTORE(ARM_EWUPCT);
377 ARM_RESTORE(ARM_RSTCT1);
378 ARM_RESTORE(ARM_RSTCT2);
379 ARM_RESTORE(ARM_SYSST);
380 ULPD_RESTORE(ULPD_CLOCK_CTRL);
381 ULPD_RESTORE(ULPD_STATUS_REQ);
382
383 if (cpu_is_omap7xx()) {
384 MPUI7XX_RESTORE(EMIFS_CONFIG);
385 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
386 MPUI7XX_RESTORE(OMAP_IH1_MIR);
387 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
388 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
389 } else if (cpu_is_omap15xx()) {
390 MPUI1510_RESTORE(MPUI_CTRL);
391 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
392 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
393 MPUI1510_RESTORE(EMIFS_CONFIG);
394 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
395 MPUI1510_RESTORE(OMAP_IH1_MIR);
396 MPUI1510_RESTORE(OMAP_IH2_MIR);
397 } else if (cpu_is_omap16xx()) {
398 MPUI1610_RESTORE(MPUI_CTRL);
399 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
400 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
401 MPUI1610_RESTORE(EMIFS_CONFIG);
402 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
403
404 MPUI1610_RESTORE(OMAP_IH1_MIR);
405 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
406 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
407 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
408 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
409 }
410
411 if (!cpu_is_omap15xx())
412 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
413
414
415
416
417
418 local_irq_enable();
419 local_fiq_enable();
420
421 omap_serial_wake_trigger(0);
422
423 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
424 omap_rev());
425}
426
427#ifdef CONFIG_DEBUG_FS
428
429
430
431static int omap_pm_debug_show(struct seq_file *m, void *v)
432{
433 ARM_SAVE(ARM_CKCTL);
434 ARM_SAVE(ARM_IDLECT1);
435 ARM_SAVE(ARM_IDLECT2);
436 if (!(cpu_is_omap15xx()))
437 ARM_SAVE(ARM_IDLECT3);
438 ARM_SAVE(ARM_EWUPCT);
439 ARM_SAVE(ARM_RSTCT1);
440 ARM_SAVE(ARM_RSTCT2);
441 ARM_SAVE(ARM_SYSST);
442
443 ULPD_SAVE(ULPD_IT_STATUS);
444 ULPD_SAVE(ULPD_CLOCK_CTRL);
445 ULPD_SAVE(ULPD_SOFT_REQ);
446 ULPD_SAVE(ULPD_STATUS_REQ);
447 ULPD_SAVE(ULPD_DPLL_CTRL);
448 ULPD_SAVE(ULPD_POWER_CTRL);
449
450 if (cpu_is_omap7xx()) {
451 MPUI7XX_SAVE(MPUI_CTRL);
452 MPUI7XX_SAVE(MPUI_DSP_STATUS);
453 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
454 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
455 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
456 MPUI7XX_SAVE(EMIFS_CONFIG);
457 } else if (cpu_is_omap15xx()) {
458 MPUI1510_SAVE(MPUI_CTRL);
459 MPUI1510_SAVE(MPUI_DSP_STATUS);
460 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
461 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
462 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
463 MPUI1510_SAVE(EMIFS_CONFIG);
464 } else if (cpu_is_omap16xx()) {
465 MPUI1610_SAVE(MPUI_CTRL);
466 MPUI1610_SAVE(MPUI_DSP_STATUS);
467 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
468 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
469 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
470 MPUI1610_SAVE(EMIFS_CONFIG);
471 }
472
473 seq_printf(m,
474 "ARM_CKCTL_REG: 0x%-8x \n"
475 "ARM_IDLECT1_REG: 0x%-8x \n"
476 "ARM_IDLECT2_REG: 0x%-8x \n"
477 "ARM_IDLECT3_REG: 0x%-8x \n"
478 "ARM_EWUPCT_REG: 0x%-8x \n"
479 "ARM_RSTCT1_REG: 0x%-8x \n"
480 "ARM_RSTCT2_REG: 0x%-8x \n"
481 "ARM_SYSST_REG: 0x%-8x \n"
482 "ULPD_IT_STATUS_REG: 0x%-4x \n"
483 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
484 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
485 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
486 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
487 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
488 ARM_SHOW(ARM_CKCTL),
489 ARM_SHOW(ARM_IDLECT1),
490 ARM_SHOW(ARM_IDLECT2),
491 ARM_SHOW(ARM_IDLECT3),
492 ARM_SHOW(ARM_EWUPCT),
493 ARM_SHOW(ARM_RSTCT1),
494 ARM_SHOW(ARM_RSTCT2),
495 ARM_SHOW(ARM_SYSST),
496 ULPD_SHOW(ULPD_IT_STATUS),
497 ULPD_SHOW(ULPD_CLOCK_CTRL),
498 ULPD_SHOW(ULPD_SOFT_REQ),
499 ULPD_SHOW(ULPD_DPLL_CTRL),
500 ULPD_SHOW(ULPD_STATUS_REQ),
501 ULPD_SHOW(ULPD_POWER_CTRL));
502
503 if (cpu_is_omap7xx()) {
504 seq_printf(m,
505 "MPUI7XX_CTRL_REG 0x%-8x \n"
506 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
507 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
508 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
509 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
510 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
511 MPUI7XX_SHOW(MPUI_CTRL),
512 MPUI7XX_SHOW(MPUI_DSP_STATUS),
513 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
514 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
515 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
516 MPUI7XX_SHOW(EMIFS_CONFIG));
517 } else if (cpu_is_omap15xx()) {
518 seq_printf(m,
519 "MPUI1510_CTRL_REG 0x%-8x \n"
520 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
521 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
522 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
523 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
524 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
525 MPUI1510_SHOW(MPUI_CTRL),
526 MPUI1510_SHOW(MPUI_DSP_STATUS),
527 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
528 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
529 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
530 MPUI1510_SHOW(EMIFS_CONFIG));
531 } else if (cpu_is_omap16xx()) {
532 seq_printf(m,
533 "MPUI1610_CTRL_REG 0x%-8x \n"
534 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
535 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
536 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
537 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
538 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
539 MPUI1610_SHOW(MPUI_CTRL),
540 MPUI1610_SHOW(MPUI_DSP_STATUS),
541 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
542 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
543 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
544 MPUI1610_SHOW(EMIFS_CONFIG));
545 }
546
547 return 0;
548}
549
550static int omap_pm_debug_open(struct inode *inode, struct file *file)
551{
552 return single_open(file, omap_pm_debug_show,
553 &inode->i_private);
554}
555
556static const struct file_operations omap_pm_debug_fops = {
557 .open = omap_pm_debug_open,
558 .read = seq_read,
559 .llseek = seq_lseek,
560 .release = single_release,
561};
562
563static void omap_pm_init_debugfs(void)
564{
565 struct dentry *d;
566
567 d = debugfs_create_dir("pm_debug", NULL);
568 if (!d)
569 return;
570
571 (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
572 d, NULL, &omap_pm_debug_fops);
573}
574
575#endif
576
577
578
579
580
581static int omap_pm_prepare(void)
582{
583
584 cpu_idle_poll_ctrl(true);
585 return 0;
586}
587
588
589
590
591
592
593
594
595static int omap_pm_enter(suspend_state_t state)
596{
597 switch (state)
598 {
599 case PM_SUSPEND_STANDBY:
600 case PM_SUSPEND_MEM:
601 omap1_pm_suspend();
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 return 0;
608}
609
610
611
612
613
614
615
616
617
618static void omap_pm_finish(void)
619{
620 cpu_idle_poll_ctrl(false);
621}
622
623
624static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
625{
626 return IRQ_HANDLED;
627}
628
629static struct irqaction omap_wakeup_irq = {
630 .name = "peripheral wakeup",
631 .flags = IRQF_DISABLED,
632 .handler = omap_wakeup_interrupt
633};
634
635
636
637static const struct platform_suspend_ops omap_pm_ops = {
638 .prepare = omap_pm_prepare,
639 .enter = omap_pm_enter,
640 .finish = omap_pm_finish,
641 .valid = suspend_valid_only_mem,
642};
643
644static int __init omap_pm_init(void)
645{
646
647#ifdef CONFIG_OMAP_32K_TIMER
648 int error;
649#endif
650
651 if (!cpu_class_is_omap1())
652 return -ENODEV;
653
654 printk("Power Management for TI OMAP.\n");
655
656
657
658
659
660
661 if (cpu_is_omap7xx()) {
662 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
663 omap7xx_cpu_suspend_sz);
664 } else if (cpu_is_omap15xx()) {
665 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
666 omap1510_cpu_suspend_sz);
667 } else if (cpu_is_omap16xx()) {
668 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
669 omap1610_cpu_suspend_sz);
670 }
671
672 if (omap_sram_suspend == NULL) {
673 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
674 return -ENODEV;
675 }
676
677 arm_pm_idle = omap1_pm_idle;
678
679 if (cpu_is_omap7xx())
680 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
681 else if (cpu_is_omap16xx())
682 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
683
684
685
686
687 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
688
689
690 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
691
692
693 if (cpu_is_omap7xx())
694 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
695 else if (cpu_is_omap16xx())
696 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
697
698 suspend_set_ops(&omap_pm_ops);
699
700#ifdef CONFIG_DEBUG_FS
701 omap_pm_init_debugfs();
702#endif
703
704#ifdef CONFIG_OMAP_32K_TIMER
705 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
706 if (error)
707 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
708#endif
709
710 if (cpu_is_omap16xx()) {
711
712 omap_cfg_reg(T20_1610_LOW_PWR);
713 }
714
715 return 0;
716}
717__initcall(omap_pm_init);
718