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22#include <linux/kernel.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/pinctrl/machine.h>
28#include <linux/platform_device.h>
29#include <linux/gpio.h>
30#include <linux/regulator/fixed.h>
31#include <linux/regulator/machine.h>
32#include <linux/smsc911x.h>
33#include <linux/videodev2.h>
34#include <mach/common.h>
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/time.h>
39#include <asm/hardware/cache-l2x0.h>
40#include <mach/r8a7740.h>
41#include <mach/irqs.h>
42#include <video/sh_mobile_lcdc.h>
43
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81
82static struct regulator_consumer_supply dummy_supplies[] = {
83 REGULATOR_SUPPLY("vddvario", "smsc911x"),
84 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
85};
86
87
88
89
90#define IRQSR0 0x0020
91#define IRQSR1 0x0022
92#define IRQMR0 0x0030
93#define IRQMR1 0x0032
94#define BUSSWMR1 0x0070
95#define BUSSWMR2 0x0072
96#define BUSSWMR3 0x0074
97#define BUSSWMR4 0x0076
98
99#define LCDCR 0x10B4
100#define DEVRSTCR1 0x10D0
101#define DEVRSTCR2 0x10D2
102#define A1MDSR 0x10E0
103#define BVERR 0x1100
104
105
106#define FPGA_IRQ_BASE (512)
107#define FPGA_IRQ0 (FPGA_IRQ_BASE)
108#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
109#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
110static u16 bonito_fpga_read(u32 offset)
111{
112 return __raw_readw(IOMEM(0xf0003000) + offset);
113}
114
115static void bonito_fpga_write(u32 offset, u16 val)
116{
117 __raw_writew(val, IOMEM(0xf0003000) + offset);
118}
119
120static void bonito_fpga_irq_disable(struct irq_data *data)
121{
122 unsigned int irq = data->irq;
123 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
124 int shift = irq % 16;
125
126 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
127}
128
129static void bonito_fpga_irq_enable(struct irq_data *data)
130{
131 unsigned int irq = data->irq;
132 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
133 int shift = irq % 16;
134
135 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
136}
137
138static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
139 .name = "bonito FPGA",
140 .irq_mask = bonito_fpga_irq_disable,
141 .irq_unmask = bonito_fpga_irq_enable,
142};
143
144static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
145{
146 u32 val = bonito_fpga_read(IRQSR1) << 16 |
147 bonito_fpga_read(IRQSR0);
148 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
149 bonito_fpga_read(IRQMR0);
150
151 int i;
152
153 val &= ~mask;
154
155 for (i = 0; i < 32; i++) {
156 if (!(val & (1 << i)))
157 continue;
158
159 generic_handle_irq(FPGA_IRQ_BASE + i);
160 }
161}
162
163static void bonito_fpga_init(void)
164{
165 int i;
166
167 bonito_fpga_write(IRQMR0, 0xffff);
168 bonito_fpga_write(IRQMR1, 0xffff);
169
170
171 bonito_fpga_write(DEVRSTCR1,
172 (1 << 2));
173
174
175 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
176 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
177 handle_level_irq, "level");
178 set_irq_flags(i, IRQF_VALID);
179 }
180
181 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
182 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
183}
184
185
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190
191
192
193static __u8 *pmic_settings = NULL;
194static __u8 pmic_do_2A[] = {
195 0x1C, 0x09,
196 0x1A, 0x80,
197 0xff, 0xff,
198};
199
200static int __init pmic_init(void)
201{
202 struct i2c_adapter *a = i2c_get_adapter(0);
203 struct i2c_msg msg;
204 __u8 buf[2];
205 int i, ret;
206
207 if (!pmic_settings)
208 return 0;
209 if (!a)
210 return 0;
211
212 msg.addr = 0x46;
213 msg.buf = buf;
214 msg.len = 2;
215 msg.flags = 0;
216
217 for (i = 0; ; i += 2) {
218 buf[0] = pmic_settings[i + 0];
219 buf[1] = pmic_settings[i + 1];
220
221 if ((0xff == buf[0]) && (0xff == buf[1]))
222 break;
223
224 ret = i2c_transfer(a, &msg, 1);
225 if (ret < 0) {
226 pr_err("i2c transfer fail\n");
227 break;
228 }
229 }
230
231 return 0;
232}
233device_initcall(pmic_init);
234
235
236
237
238static const struct fb_videomode lcdc0_mode = {
239 .name = "WVGA Panel",
240 .xres = 800,
241 .yres = 480,
242 .left_margin = 88,
243 .right_margin = 40,
244 .hsync_len = 128,
245 .upper_margin = 20,
246 .lower_margin = 5,
247 .vsync_len = 5,
248 .sync = 0,
249};
250
251static struct sh_mobile_lcdc_info lcdc0_info = {
252 .clock_source = LCDC_CLK_BUS,
253 .ch[0] = {
254 .chan = LCDC_CHAN_MAINLCD,
255 .fourcc = V4L2_PIX_FMT_RGB565,
256 .interface_type = RGB24,
257 .clock_divider = 5,
258 .flags = 0,
259 .lcd_modes = &lcdc0_mode,
260 .num_modes = 1,
261 .panel_cfg = {
262 .width = 152,
263 .height = 91,
264 },
265 },
266};
267
268static struct resource lcdc0_resources[] = {
269 [0] = {
270 .name = "LCDC0",
271 .start = 0xfe940000,
272 .end = 0xfe943fff,
273 .flags = IORESOURCE_MEM,
274 },
275 [1] = {
276 .start = intcs_evt2irq(0x0580),
277 .flags = IORESOURCE_IRQ,
278 },
279};
280
281static struct platform_device lcdc0_device = {
282 .name = "sh_mobile_lcdc_fb",
283 .id = 0,
284 .resource = lcdc0_resources,
285 .num_resources = ARRAY_SIZE(lcdc0_resources),
286 .dev = {
287 .platform_data = &lcdc0_info,
288 .coherent_dma_mask = ~0,
289 },
290};
291
292static const struct pinctrl_map lcdc0_pinctrl_map[] = {
293
294 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
295 "lcd0_data24_1", "lcd0"),
296 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
297 "lcd0_lclk_1", "lcd0"),
298 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
299 "lcd0_sync", "lcd0"),
300};
301
302
303
304
305static struct resource smsc_resources[] = {
306 [0] = {
307 .start = 0x18010000,
308 .end = 0x18011000 - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = FPGA_ETH_IRQ,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct smsc911x_platform_config smsc_platdata = {
318 .flags = SMSC911X_USE_16BIT,
319 .phy_interface = PHY_INTERFACE_MODE_MII,
320 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
321 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
322};
323
324static struct platform_device smsc_device = {
325 .name = "smsc911x",
326 .dev = {
327 .platform_data = &smsc_platdata,
328 },
329 .resource = smsc_resources,
330 .num_resources = ARRAY_SIZE(smsc_resources),
331};
332
333
334
335
336static struct platform_device *bonito_core_devices[] __initdata = {
337};
338
339
340
341
342static struct platform_device *bonito_base_devices[] __initdata = {
343 &lcdc0_device,
344 &smsc_device,
345};
346
347
348
349
350static struct map_desc bonito_io_desc[] __initdata = {
351
352
353
354
355 {
356 .virtual = 0xf0003000,
357 .pfn = __phys_to_pfn(0x18000000),
358 .length = PAGE_SIZE * 2,
359 .type = MT_DEVICE_NONSHARED
360 }
361};
362
363static void __init bonito_map_io(void)
364{
365 r8a7740_map_io();
366 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
367}
368
369
370
371
372#define BIT_ON(sw, bit) (sw & (1 << bit))
373#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
374
375#define VCCQ1CR IOMEM(0xE6058140)
376#define VCCQ1LCDCR IOMEM(0xE6058186)
377
378static void __init bonito_init(void)
379{
380 u16 val;
381
382 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
383
384 r8a7740_pinmux_init();
385 bonito_fpga_init();
386
387 pmic_settings = pmic_do_2A;
388
389
390
391
392
393#ifdef CONFIG_CACHE_L2X0
394
395 l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
396#endif
397
398 r8a7740_add_standard_devices();
399
400 platform_add_devices(bonito_core_devices,
401 ARRAY_SIZE(bonito_core_devices));
402
403
404
405
406 gpio_request_one(176, GPIOF_IN, NULL);
407 if (!gpio_get_value(176)) {
408 u16 bsw2;
409 u16 bsw3;
410 u16 bsw4;
411
412
413
414
415 gpio_request(GPIO_FN_CS5B, NULL);
416 gpio_request(GPIO_FN_CS6A, NULL);
417 gpio_request(GPIO_FN_CS5A_PORT105, NULL);
418 gpio_request(GPIO_FN_IRQ10, NULL);
419
420 val = bonito_fpga_read(BVERR);
421 pr_info("bonito version: cpu %02x, base %02x\n",
422 ((val >> 8) & 0xFF),
423 ((val >> 0) & 0xFF));
424
425 bsw2 = bonito_fpga_read(BUSSWMR2);
426 bsw3 = bonito_fpga_read(BUSSWMR3);
427 bsw4 = bonito_fpga_read(BUSSWMR4);
428
429
430
431
432 if (BIT_OFF(bsw2, 1) &&
433 BIT_OFF(bsw3, 9) &&
434 BIT_OFF(bsw4, 4)) {
435 gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
436 gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
437 }
438
439
440
441
442 if (BIT_ON(bsw2, 3) &&
443 BIT_ON(bsw2, 2)) {
444 pinctrl_register_mappings(lcdc0_pinctrl_map,
445 ARRAY_SIZE(lcdc0_pinctrl_map));
446 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
447
448 gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
449 NULL);
450
451
452 bonito_fpga_write(LCDCR, 1);
453
454
455 __raw_writew(0x00FF , VCCQ1LCDCR);
456 __raw_writew(0xFFFF , VCCQ1CR);
457 }
458
459 platform_add_devices(bonito_base_devices,
460 ARRAY_SIZE(bonito_base_devices));
461 }
462}
463
464static void __init bonito_earlytimer_init(void)
465{
466 u16 val;
467 u8 md_ck = 0;
468
469
470 val = bonito_fpga_read(A1MDSR);
471 if (val & (1 << 10))
472 md_ck |= MD_CK2;
473 if (val & (1 << 9))
474 md_ck |= MD_CK1;
475 if (val & (1 << 8))
476 md_ck |= MD_CK0;
477
478 r8a7740_clock_init(md_ck);
479 shmobile_earlytimer_init();
480}
481
482static void __init bonito_add_early_devices(void)
483{
484 r8a7740_add_early_devices();
485}
486
487MACHINE_START(BONITO, "bonito")
488 .map_io = bonito_map_io,
489 .init_early = bonito_add_early_devices,
490 .init_irq = r8a7740_init_irq,
491 .handle_irq = shmobile_handle_irq_intc,
492 .init_machine = bonito_init,
493 .init_late = shmobile_init_late,
494 .init_time = bonito_earlytimer_init,
495MACHINE_END
496
